1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013-2015 Arcturus Networks, Inc.
4 * http://www.arcturusnetworks.com/products/ucp1020/
5 * based on include/configs/p1_p2_rdb_pc.h
6 * original copyright follows:
7 * Copyright 2009-2011 Freescale Semiconductor, Inc.
11 * QorIQ uCP1020-xx boards configuration file
16 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
17 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
18 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
19 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
20 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
22 #if defined(CONFIG_TARTGET_UCP1020T1)
24 #define CONFIG_UCP1020_REV_1_3
26 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
30 #define CONFIG_HAS_ETH0
31 #define CONFIG_HAS_ETH1
32 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
33 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
34 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
35 #define CONFIG_IPADDR 10.80.41.229
36 #define CONFIG_SERVERIP 10.80.41.227
37 #define CONFIG_NETMASK 255.255.252.0
38 #define CONFIG_ETHPRIME "eTSEC3"
40 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
42 #define CONFIG_SYS_L2_SIZE (256 << 10)
46 #if defined(CONFIG_TARGET_UCP1020)
48 #define CONFIG_UCP1020
49 #define CONFIG_UCP1020_REV_1_3
51 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
56 #define CONFIG_HAS_ETH0
57 #define CONFIG_HAS_ETH1
58 #define CONFIG_HAS_ETH2
59 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
60 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
61 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
62 #define CONFIG_IPADDR 192.168.1.81
63 #define CONFIG_IPADDR1 192.168.1.82
64 #define CONFIG_IPADDR2 192.168.1.83
65 #define CONFIG_SERVERIP 192.168.1.80
66 #define CONFIG_GATEWAYIP 102.168.1.1
67 #define CONFIG_NETMASK 255.255.255.0
68 #define CONFIG_ETHPRIME "eTSEC1"
70 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
72 #define CONFIG_SYS_L2_SIZE (256 << 10)
77 #define CONFIG_RAMBOOT_SDCARD
78 #define CONFIG_SYS_RAMBOOT
79 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
82 #ifdef CONFIG_SPIFLASH
83 #define CONFIG_RAMBOOT_SPIFLASH
84 #define CONFIG_SYS_RAMBOOT
85 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
88 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
90 #ifndef CONFIG_RESET_VECTOR_ADDRESS
91 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
94 #ifndef CONFIG_SYS_MONITOR_BASE
95 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
98 #define CONFIG_ENV_OVERWRITE
100 #define CONFIG_SYS_SATA_MAX_DEVICE 2
103 #define CONFIG_SYS_CLK_FREQ 66666666
104 #define CONFIG_DDR_CLK_FREQ 66666666
106 #define CONFIG_HWCONFIG
109 * These can be toggled for performance analysis, otherwise use default.
111 #define CONFIG_L2_CACHE
114 #define CONFIG_ENABLE_36BIT_PHYS
116 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
117 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
119 #define CONFIG_SYS_CCSRBAR 0xffe00000
120 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
122 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
124 #ifdef CONFIG_SPL_BUILD
125 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
129 #define CONFIG_DDR_ECC_ENABLE
130 #ifndef CONFIG_DDR_ECC_ENABLE
131 #define CONFIG_SYS_DDR_RAW_TIMING
132 #define CONFIG_DDR_SPD
134 #define CONFIG_SYS_SPD_BUS_NUM 1
136 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
137 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
138 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
140 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
142 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
144 /* Default settings for DDR3 */
145 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
146 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
147 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
148 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
149 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
150 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
152 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
153 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
154 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
155 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
157 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
158 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
159 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
160 #define CONFIG_SYS_DDR_RCW_1 0x00000000
161 #define CONFIG_SYS_DDR_RCW_2 0x00000000
162 #ifdef CONFIG_DDR_ECC_ENABLE
163 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
165 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
167 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
168 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
169 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
171 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
172 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
173 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
174 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
175 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
176 #define CONFIG_SYS_DDR_MODE_1 0x40461520
177 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
178 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
180 #undef CONFIG_CLOCKS_IN_MHZ
185 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
186 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
187 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
188 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
190 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
191 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
192 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
196 * Local Bus Definitions
198 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
199 #define CONFIG_SYS_FLASH_BASE 0xec000000
201 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
203 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
206 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
208 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
209 #define CONFIG_SYS_FLASH_QUIET_TEST
210 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
212 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
214 #undef CONFIG_SYS_FLASH_CHECKSUM
215 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
216 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
218 #define CONFIG_SYS_FLASH_EMPTY_INFO
220 #define CONFIG_SYS_INIT_RAM_LOCK
221 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
222 /* Initial L1 address */
223 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
224 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
226 /* Size of used area in RAM */
227 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
229 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
230 GENERATED_GBL_DATA_SIZE)
231 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
233 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
234 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
236 #define CONFIG_SYS_PMC_BASE 0xff980000
237 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
238 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
240 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
241 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
244 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
245 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
246 #ifdef CONFIG_NAND_FSL_ELBC
247 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
248 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
251 /* Serial Port - controlled on board with jumper J8
255 #undef CONFIG_SERIAL_SOFTWARE_FIFO
256 #define CONFIG_SYS_NS16550_SERIAL
257 #define CONFIG_SYS_NS16550_REG_SIZE 1
258 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
259 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
260 #define CONFIG_NS16550_MIN_FUNCTIONS
263 #define CONFIG_SYS_BAUDRATE_TABLE \
264 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
266 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
267 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
270 #define CONFIG_SYS_I2C
271 #define CONFIG_SYS_I2C_FSL
272 #define CONFIG_SYS_FSL_I2C_SPEED 400000
273 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
274 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
275 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
276 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
277 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
278 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
279 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
281 #define CONFIG_RTC_DS1337
282 #define CONFIG_RTC_DS1337_NOOSC
283 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
284 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
285 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
286 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
288 #if defined(CONFIG_PCI)
291 * Memory space is mapped 1-1, but I/O space must start from 0.
294 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
295 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
296 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
297 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
298 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
299 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
300 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
301 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
302 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
303 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
305 /* controller 1, Slot 2, tgtid 1, Base address a000 */
306 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
307 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
308 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
309 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
310 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
311 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
312 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
313 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
314 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
316 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
317 #endif /* CONFIG_PCI */
322 #ifdef CONFIG_ENV_FIT_UCBOOT
324 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
325 #define CONFIG_ENV_SIZE 0x20000
326 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
331 #ifdef CONFIG_RAMBOOT_SPIFLASH
333 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
334 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
335 #define CONFIG_ENV_SECT_SIZE 0x1000
337 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
338 /* Address and size of Redundant Environment Sector */
339 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
340 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
343 #elif defined(CONFIG_RAMBOOT_SDCARD)
344 #define CONFIG_FSL_FIXED_MMC_LOCATION
345 #define CONFIG_ENV_SIZE 0x2000
346 #define CONFIG_SYS_MMC_ENV_DEV 0
348 #elif defined(CONFIG_SYS_RAMBOOT)
349 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
350 #define CONFIG_ENV_SIZE 0x2000
353 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
354 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
355 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
356 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
357 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
358 /* Address and size of Redundant Environment Sector */
359 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
360 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
365 #endif /* CONFIG_ENV_FIT_UCBOOT */
367 #define CONFIG_LOADS_ECHO /* echo on for serial download */
368 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
373 #define CONFIG_HAS_FSL_DR_USB
375 #if defined(CONFIG_HAS_FSL_DR_USB)
376 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
378 #ifdef CONFIG_USB_EHCI_HCD
379 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
380 #define CONFIG_USB_EHCI_FSL
384 #undef CONFIG_WATCHDOG /* watchdog disabled */
387 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
388 #define CONFIG_MMC_SPI
391 /* Misc Extra Settings */
392 #undef CONFIG_WATCHDOG /* watchdog disabled */
395 * Miscellaneous configurable options
397 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
398 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
401 * For booting Linux, the board info and command line data
402 * have to be in the first 64 MB of memory, since this is
403 * the maximum mapped by the Linux kernel during initialization.
405 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
406 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
408 #if defined(CONFIG_CMD_KGDB)
409 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
410 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
414 * Environment Configuration
417 #if defined(CONFIG_TSEC_ENET)
419 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
421 #error "UCP1020 module revision is not defined !!!"
424 #define CONFIG_BOOTP_SERVERIP
426 #define CONFIG_TSEC1_NAME "eTSEC1"
427 #define CONFIG_TSEC2_NAME "eTSEC2"
428 #define CONFIG_TSEC3_NAME "eTSEC3"
430 #define TSEC1_PHY_ADDR 4
431 #define TSEC2_PHY_ADDR 0
432 #define TSEC2_PHY_ADDR_SGMII 0x00
433 #define TSEC3_PHY_ADDR 6
435 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
436 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
437 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
439 #define TSEC1_PHYIDX 0
440 #define TSEC2_PHYIDX 0
441 #define TSEC3_PHYIDX 0
445 #define CONFIG_HOSTNAME "UCP1020"
446 #define CONFIG_ROOTPATH "/opt/nfsroot"
447 #define CONFIG_BOOTFILE "uImage"
448 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
450 /* default location for tftp and bootm */
451 #define CONFIG_LOADADDR 1000000
453 #if defined(CONFIG_DONGLE)
455 #define CONFIG_EXTRA_ENV_SETTINGS \
456 "bootcmd=run prog_spi_mbrbootcramfs\0" \
457 "bootfile=uImage\0" \
458 "consoledev=ttyS0\0" \
459 "cramfsfile=image.cramfs\0" \
460 "dtbaddr=0x00c00000\0" \
461 "dtbfile=image.dtb\0" \
462 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
463 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
464 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
465 "fileaddr=0x01000000\0" \
466 "filesize=0x00080000\0" \
467 "flashmbr=sf probe 0; " \
468 "tftp $loadaddr $mbr; " \
469 "sf erase $mbr_offset +$filesize; " \
470 "sf write $loadaddr $mbr_offset $filesize\0" \
471 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
472 "protect off $nor_recoveryaddr +$filesize; " \
473 "erase $nor_recoveryaddr +$filesize; " \
474 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
475 "protect on $nor_recoveryaddr +$filesize\0 " \
476 "flashuboot=tftp $ubootaddr $ubootfile; " \
477 "protect off $nor_ubootaddr +$filesize; " \
478 "erase $nor_ubootaddr +$filesize; " \
479 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
480 "protect on $nor_ubootaddr +$filesize\0 " \
481 "flashworking=tftp $workingaddr $cramfsfile; " \
482 "protect off $nor_workingaddr +$filesize; " \
483 "erase $nor_workingaddr +$filesize; " \
484 "cp.b $workingaddr $nor_workingaddr $filesize; " \
485 "protect on $nor_workingaddr +$filesize\0 " \
486 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
487 "kerneladdr=0x01100000\0" \
488 "kernelfile=uImage\0" \
489 "loadaddr=0x01000000\0" \
490 "mbr=uCP1020d.mbr\0" \
491 "mbr_offset=0x00000000\0" \
492 "mmbr=uCP1020Quiet.mbr\0" \
494 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
496 "mmc write $loadaddr 1 1\0" \
497 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
498 "mmc erase 0x40 0x400; " \
499 "mmc write $loadaddr 0x40 0x400\0" \
501 "nor_recoveryaddr=0xEC0A0000\0" \
502 "nor_ubootaddr=0xEFF80000\0" \
503 "nor_workingaddr=0xECFA0000\0" \
504 "norbootrecovery=setenv bootargs $recoverybootargs" \
505 " console=$consoledev,$baudrate $othbootargs; " \
506 "run norloadrecovery; " \
507 "bootm $kerneladdr - $dtbaddr\0" \
508 "norbootworking=setenv bootargs $workingbootargs" \
509 " console=$consoledev,$baudrate $othbootargs; " \
510 "run norloadworking; " \
511 "bootm $kerneladdr - $dtbaddr\0" \
512 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
513 "setenv cramfsaddr $nor_recoveryaddr; " \
514 "cramfsload $dtbaddr $dtbfile; " \
515 "cramfsload $kerneladdr $kernelfile\0" \
516 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
517 "setenv cramfsaddr $nor_workingaddr; " \
518 "cramfsload $dtbaddr $dtbfile; " \
519 "cramfsload $kerneladdr $kernelfile\0" \
520 "prog_spi_mbr=run spi__mbr\0" \
521 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
522 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
523 "run spi__cramfs\0" \
524 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
525 " console=$consoledev,$baudrate $othbootargs; " \
526 "tftp $rootfsaddr $rootfsfile; " \
527 "tftp $loadaddr $kernelfile; " \
528 "tftp $dtbaddr $dtbfile; " \
529 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
530 "ramdisk_size=120000\0" \
531 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
532 "recoveryaddr=0x02F00000\0" \
533 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
534 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
535 "mw.l 0xffe0f008 0x00400000\0" \
536 "rootfsaddr=0x02F00000\0" \
537 "rootfsfile=rootfs.ext2.gz.uboot\0" \
538 "rootpath=/opt/nfsroot\0" \
539 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
540 "protect off 0xeC000000 +$filesize; " \
541 "erase 0xEC000000 +$filesize; " \
542 "cp.b $loadaddr 0xEC000000 $filesize; " \
543 "cmp.b $loadaddr 0xEC000000 $filesize; " \
544 "protect on 0xeC000000 +$filesize\0" \
545 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
546 "protect off 0xeFF80000 +$filesize; " \
547 "erase 0xEFF80000 +$filesize; " \
548 "cp.b $loadaddr 0xEFF80000 $filesize; " \
549 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
550 "protect on 0xeFF80000 +$filesize\0" \
551 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
552 "sf probe 0; sf erase 0x8000 +$filesize; " \
553 "sf write $loadaddr 0x8000 $filesize\0" \
554 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
555 "protect off 0xec0a0000 +$filesize; " \
556 "erase 0xeC0A0000 +$filesize; " \
557 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
558 "protect on 0xec0a0000 +$filesize\0" \
559 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
560 "sf probe 1; sf erase 0 +$filesize; " \
561 "sf write $loadaddr 0 $filesize\0" \
562 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
563 "sf probe 0; sf erase 0 +$filesize; " \
564 "sf write $loadaddr 0 $filesize\0" \
565 "tftpflash=tftpboot $loadaddr $uboot; " \
566 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
567 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
568 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
569 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
570 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
571 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
572 "ubootaddr=0x01000000\0" \
573 "ubootfile=u-boot.bin\0" \
574 "ubootd=u-boot4dongle.bin\0" \
575 "upgrade=run flashworking\0" \
576 "usb_phy_type=ulpi\0 " \
577 "workingaddr=0x02F00000\0" \
578 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
582 #if defined(CONFIG_UCP1020T1)
584 #define CONFIG_EXTRA_ENV_SETTINGS \
585 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
586 "bootfile=uImage\0" \
587 "consoledev=ttyS0\0" \
588 "cramfsfile=image.cramfs\0" \
589 "dtbaddr=0x00c00000\0" \
590 "dtbfile=image.dtb\0" \
591 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
592 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
593 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
594 "fileaddr=0x01000000\0" \
595 "filesize=0x00080000\0" \
596 "flashmbr=sf probe 0; " \
597 "tftp $loadaddr $mbr; " \
598 "sf erase $mbr_offset +$filesize; " \
599 "sf write $loadaddr $mbr_offset $filesize\0" \
600 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
601 "protect off $nor_recoveryaddr +$filesize; " \
602 "erase $nor_recoveryaddr +$filesize; " \
603 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
604 "protect on $nor_recoveryaddr +$filesize\0 " \
605 "flashuboot=tftp $ubootaddr $ubootfile; " \
606 "protect off $nor_ubootaddr +$filesize; " \
607 "erase $nor_ubootaddr +$filesize; " \
608 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
609 "protect on $nor_ubootaddr +$filesize\0 " \
610 "flashworking=tftp $workingaddr $cramfsfile; " \
611 "protect off $nor_workingaddr +$filesize; " \
612 "erase $nor_workingaddr +$filesize; " \
613 "cp.b $workingaddr $nor_workingaddr $filesize; " \
614 "protect on $nor_workingaddr +$filesize\0 " \
615 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
616 "kerneladdr=0x01100000\0" \
617 "kernelfile=uImage\0" \
618 "loadaddr=0x01000000\0" \
619 "mbr=uCP1020.mbr\0" \
620 "mbr_offset=0x00000000\0" \
622 "nor_recoveryaddr=0xEC0A0000\0" \
623 "nor_ubootaddr=0xEFF80000\0" \
624 "nor_workingaddr=0xECFA0000\0" \
625 "norbootrecovery=setenv bootargs $recoverybootargs" \
626 " console=$consoledev,$baudrate $othbootargs; " \
627 "run norloadrecovery; " \
628 "bootm $kerneladdr - $dtbaddr\0" \
629 "norbootworking=setenv bootargs $workingbootargs" \
630 " console=$consoledev,$baudrate $othbootargs; " \
631 "run norloadworking; " \
632 "bootm $kerneladdr - $dtbaddr\0" \
633 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
634 "setenv cramfsaddr $nor_recoveryaddr; " \
635 "cramfsload $dtbaddr $dtbfile; " \
636 "cramfsload $kerneladdr $kernelfile\0" \
637 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
638 "setenv cramfsaddr $nor_workingaddr; " \
639 "cramfsload $dtbaddr $dtbfile; " \
640 "cramfsload $kerneladdr $kernelfile\0" \
641 "othbootargs=quiet\0" \
642 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
643 " console=$consoledev,$baudrate $othbootargs; " \
644 "tftp $rootfsaddr $rootfsfile; " \
645 "tftp $loadaddr $kernelfile; " \
646 "tftp $dtbaddr $dtbfile; " \
647 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
648 "ramdisk_size=120000\0" \
649 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
650 "recoveryaddr=0x02F00000\0" \
651 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
652 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
653 "mw.l 0xffe0f008 0x00400000\0" \
654 "rootfsaddr=0x02F00000\0" \
655 "rootfsfile=rootfs.ext2.gz.uboot\0" \
656 "rootpath=/opt/nfsroot\0" \
658 "tftpflash=tftpboot $loadaddr $uboot; " \
659 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
660 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
661 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
662 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
663 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
664 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
665 "ubootaddr=0x01000000\0" \
666 "ubootfile=u-boot.bin\0" \
667 "upgrade=run flashworking\0" \
668 "workingaddr=0x02F00000\0" \
669 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
671 #else /* For Arcturus Modules */
673 #define CONFIG_EXTRA_ENV_SETTINGS \
674 "bootcmd=run norkernel\0" \
675 "bootfile=uImage\0" \
676 "consoledev=ttyS0\0" \
677 "dtbaddr=0x00c00000\0" \
678 "dtbfile=image.dtb\0" \
679 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
680 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
681 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
682 "fileaddr=0x01000000\0" \
683 "filesize=0x00080000\0" \
684 "flashmbr=sf probe 0; " \
685 "tftp $loadaddr $mbr; " \
686 "sf erase $mbr_offset +$filesize; " \
687 "sf write $loadaddr $mbr_offset $filesize\0" \
688 "flashuboot=tftp $loadaddr $ubootfile; " \
689 "protect off $nor_ubootaddr0 +$filesize; " \
690 "erase $nor_ubootaddr0 +$filesize; " \
691 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
692 "protect on $nor_ubootaddr0 +$filesize; " \
693 "protect off $nor_ubootaddr1 +$filesize; " \
694 "erase $nor_ubootaddr1 +$filesize; " \
695 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
696 "protect on $nor_ubootaddr1 +$filesize\0 " \
697 "format0=protect off $part0base +$part0size; " \
698 "erase $part0base +$part0size\0" \
699 "format1=protect off $part1base +$part1size; " \
700 "erase $part1base +$part1size\0" \
701 "format2=protect off $part2base +$part2size; " \
702 "erase $part2base +$part2size\0" \
703 "format3=protect off $part3base +$part3size; " \
704 "erase $part3base +$part3size\0" \
705 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
706 "kerneladdr=0x01100000\0" \
707 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
708 "kernelfile=uImage\0" \
709 "loadaddr=0x01000000\0" \
710 "mbr=uCP1020.mbr\0" \
711 "mbr_offset=0x00000000\0" \
713 "nor_ubootaddr0=0xEC000000\0" \
714 "nor_ubootaddr1=0xEFF80000\0" \
715 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
716 "run norkernelload; " \
717 "bootm $kerneladdr - $dtbaddr\0" \
718 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
719 "setenv cramfsaddr $part0base; " \
720 "cramfsload $dtbaddr $dtbfile; " \
721 "cramfsload $kerneladdr $kernelfile\0" \
722 "part0base=0xEC100000\0" \
723 "part0size=0x00700000\0" \
724 "part1base=0xEC800000\0" \
725 "part1size=0x02000000\0" \
726 "part2base=0xEE800000\0" \
727 "part2size=0x00800000\0" \
728 "part3base=0xEF000000\0" \
729 "part3size=0x00F80000\0" \
730 "partENVbase=0xEC080000\0" \
731 "partENVsize=0x00080000\0" \
732 "program0=tftp part0-000000.bin; " \
733 "protect off $part0base +$filesize; " \
734 "erase $part0base +$filesize; " \
735 "cp.b $loadaddr $part0base $filesize; " \
736 "echo Verifying...; " \
737 "cmp.b $loadaddr $part0base $filesize\0" \
738 "program1=tftp part1-000000.bin; " \
739 "protect off $part1base +$filesize; " \
740 "erase $part1base +$filesize; " \
741 "cp.b $loadaddr $part1base $filesize; " \
742 "echo Verifying...; " \
743 "cmp.b $loadaddr $part1base $filesize\0" \
744 "program2=tftp part2-000000.bin; " \
745 "protect off $part2base +$filesize; " \
746 "erase $part2base +$filesize; " \
747 "cp.b $loadaddr $part2base $filesize; " \
748 "echo Verifying...; " \
749 "cmp.b $loadaddr $part2base $filesize\0" \
750 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
751 " console=$consoledev,$baudrate $othbootargs; " \
752 "tftp $rootfsaddr $rootfsfile; " \
753 "tftp $loadaddr $kernelfile; " \
754 "tftp $dtbaddr $dtbfile; " \
755 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
756 "ramdisk_size=120000\0" \
757 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
758 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
759 "mw.l 0xffe0f008 0x00400000\0" \
760 "rootfsaddr=0x02F00000\0" \
761 "rootfsfile=rootfs.ext2.gz.uboot\0" \
762 "rootpath=/opt/nfsroot\0" \
763 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
764 "sf probe 0; sf erase 0 +$filesize; " \
765 "sf write $loadaddr 0 $filesize\0" \
766 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
767 "protect off 0xeC000000 +$filesize; " \
768 "erase 0xEC000000 +$filesize; " \
769 "cp.b $loadaddr 0xEC000000 $filesize; " \
770 "cmp.b $loadaddr 0xEC000000 $filesize; " \
771 "protect on 0xeC000000 +$filesize\0" \
772 "tftpflash=tftpboot $loadaddr $uboot; " \
773 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
774 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
775 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
776 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
777 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
778 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
779 "ubootfile=u-boot.bin\0" \
780 "upgrade=run flashuboot\0" \
781 "usb_phy_type=ulpi\0 " \
783 "setenv bootargs root=/dev/nfs rw " \
784 "nfsroot=$serverip:$rootpath " \
785 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
786 "console=$consoledev,$baudrate $othbootargs;" \
787 "tftp $loadaddr $bootfile;" \
788 "tftp $fdtaddr $fdtfile;" \
789 "bootm $loadaddr - $fdtaddr\0" \
791 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
792 "console=$consoledev,$baudrate $othbootargs;" \
794 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
795 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
796 "bootm $loadaddr - $fdtaddr\0" \
798 "setenv bootargs root=/dev/ram rw " \
799 "console=$consoledev,$baudrate $othbootargs " \
800 "ramdisk_size=$ramdisk_size;" \
802 "fatload usb 0:2 $loadaddr $bootfile;" \
803 "fatload usb 0:2 $fdtaddr $fdtfile;" \
804 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
805 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
807 "setenv bootargs root=/dev/ram rw " \
808 "console=$consoledev,$baudrate $othbootargs " \
809 "ramdisk_size=$ramdisk_size;" \
811 "ext2load usb 0:4 $loadaddr $bootfile;" \
812 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
813 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
814 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
816 "setenv bootargs root=/dev/$jffs2nor rw " \
817 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
818 "bootm $norbootaddr - $norfdtaddr\0 " \
820 "setenv bootargs root=/dev/ram rw " \
821 "console=$consoledev,$baudrate $othbootargs " \
822 "ramdisk_size=$ramdisk_size;" \
823 "tftp $ramdiskaddr $ramdiskfile;" \
824 "tftp $loadaddr $bootfile;" \
825 "tftp $fdtaddr $fdtfile;" \
826 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
831 #endif /* __CONFIG_H */