1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013-2019 Arcturus Networks, Inc.
4 * https://www.arcturusnetworks.com/products/ucp1020/
5 * based on include/configs/p1_p2_rdb_pc.h
6 * original copyright follows:
7 * Copyright 2009-2011 Freescale Semiconductor, Inc.
11 * QorIQ uCP1020-xx boards configuration file
16 #include <linux/stringify.h>
18 /*** Arcturus FirmWare Environment */
20 #define MAX_SERIAL_SIZE 15
21 #define MAX_HWADDR_SIZE 17
23 #define MAX_FWENV_ADDR 4
26 #define FWENV_SPI_FLASH 2
27 #define FWENV_NOR_FLASH 3
29 #define FWENV_TYPE FWENV_MMC
30 #define FWENV_TYPE FWENV_SPI_FLASH
32 #define FWENV_TYPE FWENV_NOR_FLASH
34 #if (FWENV_TYPE == FWENV_MMC)
35 #define FWENV_ADDR1 -1
36 #define FWENV_ADDR2 -1
37 #define FWENV_ADDR3 -1
38 #define FWENV_ADDR4 -1
42 #if (FWENV_TYPE == FWENV_SPI_FLASH)
43 #ifndef CONFIG_SF_DEFAULT_SPEED
44 #define CONFIG_SF_DEFAULT_SPEED 1000000
46 #ifndef CONFIG_SF_DEFAULT_MODE
47 #define CONFIG_SF_DEFAULT_MODE SPI_MODE0
49 #ifndef CONFIG_SF_DEFAULT_CS
50 #define CONFIG_SF_DEFAULT_CS 0
52 #ifndef CONFIG_SF_DEFAULT_BUS
53 #define CONFIG_SF_DEFAULT_BUS 0
55 #define FWENV_ADDR1 (0x200 - sizeof(smac))
56 #define FWENV_ADDR2 (0x400 - sizeof(smac))
57 #define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
58 #define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
59 #define EMPY_CHAR 0xff
62 #if (FWENV_TYPE == FWENV_NOR_FLASH)
63 #define FWENV_ADDR1 0xEC080000
64 #define FWENV_ADDR2 -1
65 #define FWENV_ADDR3 -1
66 #define FWENV_ADDR4 -1
67 #define EMPY_CHAR 0xff
69 /***********************************/
71 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
72 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
73 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
74 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
75 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
77 #if defined(CONFIG_TARTGET_UCP1020T1)
79 #define CONFIG_UCP1020_REV_1_3
81 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
85 #define CONFIG_HAS_ETH0
86 #define CONFIG_HAS_ETH1
87 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
88 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
89 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
90 #define CONFIG_IPADDR 10.80.41.229
91 #define CONFIG_SERVERIP 10.80.41.227
92 #define CONFIG_NETMASK 255.255.252.0
93 #define CONFIG_ETHPRIME "eTSEC3"
95 #define CONFIG_SYS_L2_SIZE (256 << 10)
99 #if defined(CONFIG_TARGET_UCP1020)
101 #define CONFIG_UCP1020
102 #define CONFIG_UCP1020_REV_1_3
104 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
108 #define CONFIG_HAS_ETH0
109 #define CONFIG_HAS_ETH1
110 #define CONFIG_HAS_ETH2
111 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
112 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
113 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
114 #define CONFIG_IPADDR 192.168.1.81
115 #define CONFIG_IPADDR1 192.168.1.82
116 #define CONFIG_IPADDR2 192.168.1.83
117 #define CONFIG_SERVERIP 192.168.1.80
118 #define CONFIG_GATEWAYIP 102.168.1.1
119 #define CONFIG_NETMASK 255.255.255.0
120 #define CONFIG_ETHPRIME "eTSEC1"
122 #define CONFIG_SYS_L2_SIZE (256 << 10)
127 #define CONFIG_RAMBOOT_SDCARD
128 #define CONFIG_SYS_RAMBOOT
129 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
132 #ifdef CONFIG_SPIFLASH
133 #define CONFIG_RAMBOOT_SPIFLASH
134 #define CONFIG_SYS_RAMBOOT
135 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
138 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
140 #ifndef CONFIG_RESET_VECTOR_ADDRESS
141 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
144 #ifndef CONFIG_SYS_MONITOR_BASE
145 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
148 #define CONFIG_SYS_SATA_MAX_DEVICE 2
151 #define CONFIG_SYS_CLK_FREQ 66666666
152 #define CONFIG_DDR_CLK_FREQ 66666666
154 #define CONFIG_HWCONFIG
157 * These can be toggled for performance analysis, otherwise use default.
159 #define CONFIG_L2_CACHE
162 #define CONFIG_ENABLE_36BIT_PHYS
164 #define CONFIG_SYS_CCSRBAR 0xffe00000
165 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
167 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
169 #ifdef CONFIG_SPL_BUILD
170 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
174 #define CONFIG_SYS_SPD_BUS_NUM 1
176 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
177 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
178 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
179 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
180 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
182 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
184 /* Default settings for DDR3 */
185 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
186 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
187 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
188 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
189 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
190 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
192 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
193 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
194 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
195 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
197 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
198 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
199 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
200 #define CONFIG_SYS_DDR_RCW_1 0x00000000
201 #define CONFIG_SYS_DDR_RCW_2 0x00000000
202 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
203 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
204 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
205 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
207 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
208 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
209 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
210 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
211 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
212 #define CONFIG_SYS_DDR_MODE_1 0x40461520
213 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
214 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
219 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
220 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
221 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
222 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
224 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
225 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
226 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
230 * Local Bus Definitions
232 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
233 #define CONFIG_SYS_FLASH_BASE 0xec000000
235 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
237 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
240 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
242 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
243 #define CONFIG_SYS_FLASH_QUIET_TEST
244 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
246 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
248 #undef CONFIG_SYS_FLASH_CHECKSUM
249 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
250 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
252 #define CONFIG_SYS_FLASH_EMPTY_INFO
254 #define CONFIG_SYS_INIT_RAM_LOCK
255 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
256 /* Initial L1 address */
257 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
258 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
259 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
260 /* Size of used area in RAM */
261 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
263 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
264 GENERATED_GBL_DATA_SIZE)
265 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
267 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
268 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
270 #define CONFIG_SYS_PMC_BASE 0xff980000
271 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
272 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
274 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
275 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
278 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
279 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
280 #ifdef CONFIG_NAND_FSL_ELBC
281 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
282 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
285 /* Serial Port - controlled on board with jumper J8
289 #undef CONFIG_SERIAL_SOFTWARE_FIFO
290 #define CONFIG_SYS_NS16550_SERIAL
291 #define CONFIG_SYS_NS16550_REG_SIZE 1
292 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
293 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
294 #define CONFIG_NS16550_MIN_FUNCTIONS
297 #define CONFIG_SYS_BAUDRATE_TABLE \
298 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
300 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
301 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
304 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
305 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
307 #define CONFIG_RTC_DS1337
308 #define CONFIG_RTC_DS1337_NOOSC
309 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
310 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
311 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
312 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
314 #if defined(CONFIG_PCI)
317 * Memory space is mapped 1-1, but I/O space must start from 0.
320 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
321 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
322 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
323 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
324 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
325 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
326 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
327 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
328 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
329 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
331 /* controller 1, Slot 2, tgtid 1, Base address a000 */
332 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
333 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
334 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
335 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
336 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
337 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
338 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
339 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
340 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
342 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
343 #endif /* CONFIG_PCI */
348 #if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD)
349 #define CONFIG_FSL_FIXED_MMC_LOCATION
352 #define CONFIG_LOADS_ECHO /* echo on for serial download */
353 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
358 #define CONFIG_HAS_FSL_DR_USB
360 #if defined(CONFIG_HAS_FSL_DR_USB)
361 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
363 #ifdef CONFIG_USB_EHCI_HCD
364 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
365 #define CONFIG_USB_EHCI_FSL
369 #undef CONFIG_WATCHDOG /* watchdog disabled */
372 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
375 /* Misc Extra Settings */
376 #undef CONFIG_WATCHDOG /* watchdog disabled */
379 * Miscellaneous configurable options
381 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
382 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
385 * For booting Linux, the board info and command line data
386 * have to be in the first 64 MB of memory, since this is
387 * the maximum mapped by the Linux kernel during initialization.
389 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
390 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
392 #if defined(CONFIG_CMD_KGDB)
393 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
394 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
398 * Environment Configuration
401 #if defined(CONFIG_TSEC_ENET)
403 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
405 #error "UCP1020 module revision is not defined !!!"
408 #define CONFIG_BOOTP_SERVERIP
410 #define CONFIG_TSEC1_NAME "eTSEC1"
411 #define CONFIG_TSEC2_NAME "eTSEC2"
412 #define CONFIG_TSEC3_NAME "eTSEC3"
414 #define TSEC1_PHY_ADDR 4
415 #define TSEC2_PHY_ADDR 0
416 #define TSEC2_PHY_ADDR_SGMII 0x00
417 #define TSEC3_PHY_ADDR 6
419 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
420 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
421 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
423 #define TSEC1_PHYIDX 0
424 #define TSEC2_PHYIDX 0
425 #define TSEC3_PHYIDX 0
429 #define CONFIG_HOSTNAME "UCP1020"
430 #define CONFIG_ROOTPATH "/opt/nfsroot"
431 #define CONFIG_BOOTFILE "uImage"
432 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
434 /* default location for tftp and bootm */
435 #define CONFIG_LOADADDR 1000000
437 #if defined(CONFIG_DONGLE)
439 #define CONFIG_EXTRA_ENV_SETTINGS \
440 "bootcmd=run prog_spi_mbrbootcramfs\0" \
441 "bootfile=uImage\0" \
442 "consoledev=ttyS0\0" \
443 "cramfsfile=image.cramfs\0" \
444 "dtbaddr=0x00c00000\0" \
445 "dtbfile=image.dtb\0" \
446 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
447 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
448 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
449 "fileaddr=0x01000000\0" \
450 "filesize=0x00080000\0" \
451 "flashmbr=sf probe 0; " \
452 "tftp $loadaddr $mbr; " \
453 "sf erase $mbr_offset +$filesize; " \
454 "sf write $loadaddr $mbr_offset $filesize\0" \
455 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
456 "protect off $nor_recoveryaddr +$filesize; " \
457 "erase $nor_recoveryaddr +$filesize; " \
458 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
459 "protect on $nor_recoveryaddr +$filesize\0 " \
460 "flashuboot=tftp $ubootaddr $ubootfile; " \
461 "protect off $nor_ubootaddr +$filesize; " \
462 "erase $nor_ubootaddr +$filesize; " \
463 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
464 "protect on $nor_ubootaddr +$filesize\0 " \
465 "flashworking=tftp $workingaddr $cramfsfile; " \
466 "protect off $nor_workingaddr +$filesize; " \
467 "erase $nor_workingaddr +$filesize; " \
468 "cp.b $workingaddr $nor_workingaddr $filesize; " \
469 "protect on $nor_workingaddr +$filesize\0 " \
470 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
471 "kerneladdr=0x01100000\0" \
472 "kernelfile=uImage\0" \
473 "loadaddr=0x01000000\0" \
474 "mbr=uCP1020d.mbr\0" \
475 "mbr_offset=0x00000000\0" \
476 "mmbr=uCP1020Quiet.mbr\0" \
478 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
480 "mmc write $loadaddr 1 1\0" \
481 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
482 "mmc erase 0x40 0x400; " \
483 "mmc write $loadaddr 0x40 0x400\0" \
485 "nor_recoveryaddr=0xEC0A0000\0" \
486 "nor_ubootaddr=0xEFF80000\0" \
487 "nor_workingaddr=0xECFA0000\0" \
488 "norbootrecovery=setenv bootargs $recoverybootargs" \
489 " console=$consoledev,$baudrate $othbootargs; " \
490 "run norloadrecovery; " \
491 "bootm $kerneladdr - $dtbaddr\0" \
492 "norbootworking=setenv bootargs $workingbootargs" \
493 " console=$consoledev,$baudrate $othbootargs; " \
494 "run norloadworking; " \
495 "bootm $kerneladdr - $dtbaddr\0" \
496 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
497 "setenv cramfsaddr $nor_recoveryaddr; " \
498 "cramfsload $dtbaddr $dtbfile; " \
499 "cramfsload $kerneladdr $kernelfile\0" \
500 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
501 "setenv cramfsaddr $nor_workingaddr; " \
502 "cramfsload $dtbaddr $dtbfile; " \
503 "cramfsload $kerneladdr $kernelfile\0" \
504 "prog_spi_mbr=run spi__mbr\0" \
505 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
506 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
507 "run spi__cramfs\0" \
508 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
509 " console=$consoledev,$baudrate $othbootargs; " \
510 "tftp $rootfsaddr $rootfsfile; " \
511 "tftp $loadaddr $kernelfile; " \
512 "tftp $dtbaddr $dtbfile; " \
513 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
514 "ramdisk_size=120000\0" \
515 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
516 "recoveryaddr=0x02F00000\0" \
517 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
518 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
519 "mw.l 0xffe0f008 0x00400000\0" \
520 "rootfsaddr=0x02F00000\0" \
521 "rootfsfile=rootfs.ext2.gz.uboot\0" \
522 "rootpath=/opt/nfsroot\0" \
523 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
524 "protect off 0xeC000000 +$filesize; " \
525 "erase 0xEC000000 +$filesize; " \
526 "cp.b $loadaddr 0xEC000000 $filesize; " \
527 "cmp.b $loadaddr 0xEC000000 $filesize; " \
528 "protect on 0xeC000000 +$filesize\0" \
529 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
530 "protect off 0xeFF80000 +$filesize; " \
531 "erase 0xEFF80000 +$filesize; " \
532 "cp.b $loadaddr 0xEFF80000 $filesize; " \
533 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
534 "protect on 0xeFF80000 +$filesize\0" \
535 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
536 "sf probe 0; sf erase 0x8000 +$filesize; " \
537 "sf write $loadaddr 0x8000 $filesize\0" \
538 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
539 "protect off 0xec0a0000 +$filesize; " \
540 "erase 0xeC0A0000 +$filesize; " \
541 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
542 "protect on 0xec0a0000 +$filesize\0" \
543 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
544 "sf probe 1; sf erase 0 +$filesize; " \
545 "sf write $loadaddr 0 $filesize\0" \
546 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
547 "sf probe 0; sf erase 0 +$filesize; " \
548 "sf write $loadaddr 0 $filesize\0" \
549 "tftpflash=tftpboot $loadaddr $uboot; " \
550 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
551 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
552 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
553 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
554 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
555 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
556 "ubootaddr=0x01000000\0" \
557 "ubootfile=u-boot.bin\0" \
558 "ubootd=u-boot4dongle.bin\0" \
559 "upgrade=run flashworking\0" \
560 "usb_phy_type=ulpi\0 " \
561 "workingaddr=0x02F00000\0" \
562 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
566 #if defined(CONFIG_UCP1020T1)
568 #define CONFIG_EXTRA_ENV_SETTINGS \
569 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
570 "bootfile=uImage\0" \
571 "consoledev=ttyS0\0" \
572 "cramfsfile=image.cramfs\0" \
573 "dtbaddr=0x00c00000\0" \
574 "dtbfile=image.dtb\0" \
575 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
576 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
577 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
578 "fileaddr=0x01000000\0" \
579 "filesize=0x00080000\0" \
580 "flashmbr=sf probe 0; " \
581 "tftp $loadaddr $mbr; " \
582 "sf erase $mbr_offset +$filesize; " \
583 "sf write $loadaddr $mbr_offset $filesize\0" \
584 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
585 "protect off $nor_recoveryaddr +$filesize; " \
586 "erase $nor_recoveryaddr +$filesize; " \
587 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
588 "protect on $nor_recoveryaddr +$filesize\0 " \
589 "flashuboot=tftp $ubootaddr $ubootfile; " \
590 "protect off $nor_ubootaddr +$filesize; " \
591 "erase $nor_ubootaddr +$filesize; " \
592 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
593 "protect on $nor_ubootaddr +$filesize\0 " \
594 "flashworking=tftp $workingaddr $cramfsfile; " \
595 "protect off $nor_workingaddr +$filesize; " \
596 "erase $nor_workingaddr +$filesize; " \
597 "cp.b $workingaddr $nor_workingaddr $filesize; " \
598 "protect on $nor_workingaddr +$filesize\0 " \
599 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
600 "kerneladdr=0x01100000\0" \
601 "kernelfile=uImage\0" \
602 "loadaddr=0x01000000\0" \
603 "mbr=uCP1020.mbr\0" \
604 "mbr_offset=0x00000000\0" \
606 "nor_recoveryaddr=0xEC0A0000\0" \
607 "nor_ubootaddr=0xEFF80000\0" \
608 "nor_workingaddr=0xECFA0000\0" \
609 "norbootrecovery=setenv bootargs $recoverybootargs" \
610 " console=$consoledev,$baudrate $othbootargs; " \
611 "run norloadrecovery; " \
612 "bootm $kerneladdr - $dtbaddr\0" \
613 "norbootworking=setenv bootargs $workingbootargs" \
614 " console=$consoledev,$baudrate $othbootargs; " \
615 "run norloadworking; " \
616 "bootm $kerneladdr - $dtbaddr\0" \
617 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
618 "setenv cramfsaddr $nor_recoveryaddr; " \
619 "cramfsload $dtbaddr $dtbfile; " \
620 "cramfsload $kerneladdr $kernelfile\0" \
621 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
622 "setenv cramfsaddr $nor_workingaddr; " \
623 "cramfsload $dtbaddr $dtbfile; " \
624 "cramfsload $kerneladdr $kernelfile\0" \
625 "othbootargs=quiet\0" \
626 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
627 " console=$consoledev,$baudrate $othbootargs; " \
628 "tftp $rootfsaddr $rootfsfile; " \
629 "tftp $loadaddr $kernelfile; " \
630 "tftp $dtbaddr $dtbfile; " \
631 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
632 "ramdisk_size=120000\0" \
633 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
634 "recoveryaddr=0x02F00000\0" \
635 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
636 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
637 "mw.l 0xffe0f008 0x00400000\0" \
638 "rootfsaddr=0x02F00000\0" \
639 "rootfsfile=rootfs.ext2.gz.uboot\0" \
640 "rootpath=/opt/nfsroot\0" \
642 "tftpflash=tftpboot $loadaddr $uboot; " \
643 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
644 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
645 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
646 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
647 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
648 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
649 "ubootaddr=0x01000000\0" \
650 "ubootfile=u-boot.bin\0" \
651 "upgrade=run flashworking\0" \
652 "workingaddr=0x02F00000\0" \
653 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
655 #else /* For Arcturus Modules */
657 #define CONFIG_EXTRA_ENV_SETTINGS \
658 "bootcmd=run norkernel\0" \
659 "bootfile=uImage\0" \
660 "consoledev=ttyS0\0" \
661 "dtbaddr=0x00c00000\0" \
662 "dtbfile=image.dtb\0" \
663 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
664 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
665 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
666 "fileaddr=0x01000000\0" \
667 "filesize=0x00080000\0" \
668 "flashmbr=sf probe 0; " \
669 "tftp $loadaddr $mbr; " \
670 "sf erase $mbr_offset +$filesize; " \
671 "sf write $loadaddr $mbr_offset $filesize\0" \
672 "flashuboot=tftp $loadaddr $ubootfile; " \
673 "protect off $nor_ubootaddr0 +$filesize; " \
674 "erase $nor_ubootaddr0 +$filesize; " \
675 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
676 "protect on $nor_ubootaddr0 +$filesize; " \
677 "protect off $nor_ubootaddr1 +$filesize; " \
678 "erase $nor_ubootaddr1 +$filesize; " \
679 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
680 "protect on $nor_ubootaddr1 +$filesize\0 " \
681 "format0=protect off $part0base +$part0size; " \
682 "erase $part0base +$part0size\0" \
683 "format1=protect off $part1base +$part1size; " \
684 "erase $part1base +$part1size\0" \
685 "format2=protect off $part2base +$part2size; " \
686 "erase $part2base +$part2size\0" \
687 "format3=protect off $part3base +$part3size; " \
688 "erase $part3base +$part3size\0" \
689 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
690 "kerneladdr=0x01100000\0" \
691 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
692 "kernelfile=uImage\0" \
693 "loadaddr=0x01000000\0" \
694 "mbr=uCP1020.mbr\0" \
695 "mbr_offset=0x00000000\0" \
697 "nor_ubootaddr0=0xEC000000\0" \
698 "nor_ubootaddr1=0xEFF80000\0" \
699 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
700 "run norkernelload; " \
701 "bootm $kerneladdr - $dtbaddr\0" \
702 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
703 "setenv cramfsaddr $part0base; " \
704 "cramfsload $dtbaddr $dtbfile; " \
705 "cramfsload $kerneladdr $kernelfile\0" \
706 "part0base=0xEC100000\0" \
707 "part0size=0x00700000\0" \
708 "part1base=0xEC800000\0" \
709 "part1size=0x02000000\0" \
710 "part2base=0xEE800000\0" \
711 "part2size=0x00800000\0" \
712 "part3base=0xEF000000\0" \
713 "part3size=0x00F80000\0" \
714 "partENVbase=0xEC080000\0" \
715 "partENVsize=0x00080000\0" \
716 "program0=tftp part0-000000.bin; " \
717 "protect off $part0base +$filesize; " \
718 "erase $part0base +$filesize; " \
719 "cp.b $loadaddr $part0base $filesize; " \
720 "echo Verifying...; " \
721 "cmp.b $loadaddr $part0base $filesize\0" \
722 "program1=tftp part1-000000.bin; " \
723 "protect off $part1base +$filesize; " \
724 "erase $part1base +$filesize; " \
725 "cp.b $loadaddr $part1base $filesize; " \
726 "echo Verifying...; " \
727 "cmp.b $loadaddr $part1base $filesize\0" \
728 "program2=tftp part2-000000.bin; " \
729 "protect off $part2base +$filesize; " \
730 "erase $part2base +$filesize; " \
731 "cp.b $loadaddr $part2base $filesize; " \
732 "echo Verifying...; " \
733 "cmp.b $loadaddr $part2base $filesize\0" \
734 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
735 " console=$consoledev,$baudrate $othbootargs; " \
736 "tftp $rootfsaddr $rootfsfile; " \
737 "tftp $loadaddr $kernelfile; " \
738 "tftp $dtbaddr $dtbfile; " \
739 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
740 "ramdisk_size=120000\0" \
741 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
742 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
743 "mw.l 0xffe0f008 0x00400000\0" \
744 "rootfsaddr=0x02F00000\0" \
745 "rootfsfile=rootfs.ext2.gz.uboot\0" \
746 "rootpath=/opt/nfsroot\0" \
747 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
748 "sf probe 0; sf erase 0 +$filesize; " \
749 "sf write $loadaddr 0 $filesize\0" \
750 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
751 "protect off 0xeC000000 +$filesize; " \
752 "erase 0xEC000000 +$filesize; " \
753 "cp.b $loadaddr 0xEC000000 $filesize; " \
754 "cmp.b $loadaddr 0xEC000000 $filesize; " \
755 "protect on 0xeC000000 +$filesize\0" \
756 "tftpflash=tftpboot $loadaddr $uboot; " \
757 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
758 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
759 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
760 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
761 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
762 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
763 "ubootfile=u-boot.bin\0" \
764 "upgrade=run flashuboot\0" \
765 "usb_phy_type=ulpi\0 " \
767 "setenv bootargs root=/dev/nfs rw " \
768 "nfsroot=$serverip:$rootpath " \
769 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
770 "console=$consoledev,$baudrate $othbootargs;" \
771 "tftp $loadaddr $bootfile;" \
772 "tftp $fdtaddr $fdtfile;" \
773 "bootm $loadaddr - $fdtaddr\0" \
775 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
776 "console=$consoledev,$baudrate $othbootargs;" \
778 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
779 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
780 "bootm $loadaddr - $fdtaddr\0" \
782 "setenv bootargs root=/dev/ram rw " \
783 "console=$consoledev,$baudrate $othbootargs " \
784 "ramdisk_size=$ramdisk_size;" \
786 "fatload usb 0:2 $loadaddr $bootfile;" \
787 "fatload usb 0:2 $fdtaddr $fdtfile;" \
788 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
789 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
791 "setenv bootargs root=/dev/ram rw " \
792 "console=$consoledev,$baudrate $othbootargs " \
793 "ramdisk_size=$ramdisk_size;" \
795 "ext2load usb 0:4 $loadaddr $bootfile;" \
796 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
797 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
798 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
800 "setenv bootargs root=/dev/$jffs2nor rw " \
801 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
802 "bootm $norbootaddr - $norfdtaddr\0 " \
804 "setenv bootargs root=/dev/ram rw " \
805 "console=$consoledev,$baudrate $othbootargs " \
806 "ramdisk_size=$ramdisk_size;" \
807 "tftp $ramdiskaddr $ramdiskfile;" \
808 "tftp $loadaddr $bootfile;" \
809 "tftp $fdtaddr $fdtfile;" \
810 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
815 #endif /* __CONFIG_H */