77bfd50cc99bb7b49f5e7916eb8a2058a6fd3daf
[platform/kernel/u-boot.git] / include / configs / UCP1020.h
1 /*
2  * Copyright 2013-2015 Arcturus Networks, Inc.
3  *           http://www.arcturusnetworks.com/products/ucp1020/
4  * based on include/configs/p1_p2_rdb_pc.h
5  * original copyright follows:
6  * Copyright 2009-2011 Freescale Semiconductor, Inc.
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 /*
12  * QorIQ uCP1020-xx boards configuration file
13  */
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16
17 #define CONFIG_PCIE1    /* PCIE controller 1 (slot 1) */
18 #define CONFIG_PCIE2    /* PCIE controller 2 (slot 2) */
19 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
20 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
21 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
22 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
23
24 #if defined(CONFIG_TARTGET_UCP1020T1)
25
26 #define CONFIG_UCP1020_REV_1_3
27
28 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
29
30 #define CONFIG_TSEC_ENET
31 #define CONFIG_TSEC1
32 #define CONFIG_TSEC3
33 #define CONFIG_HAS_ETH0
34 #define CONFIG_HAS_ETH1
35 #define CONFIG_ETHADDR          00:19:D3:FF:FF:FF
36 #define CONFIG_ETH1ADDR         00:19:D3:FF:FF:FE
37 #define CONFIG_ETH2ADDR         00:19:D3:FF:FF:FD
38 #define CONFIG_IPADDR           10.80.41.229
39 #define CONFIG_SERVERIP         10.80.41.227
40 #define CONFIG_NETMASK          255.255.252.0
41 #define CONFIG_ETHPRIME         "eTSEC3"
42
43 #ifndef CONFIG_SPI_FLASH
44 #endif
45 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
46
47 #define CONFIG_SYS_L2_SIZE      (256 << 10)
48
49 #define CONFIG_LAST_STAGE_INIT
50
51 #endif
52
53 #if defined(CONFIG_TARGET_UCP1020)
54
55 #define CONFIG_UCP1020
56 #define CONFIG_UCP1020_REV_1_3
57
58 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
59
60 #define CONFIG_TSEC_ENET
61 #define CONFIG_TSEC1
62 #define CONFIG_TSEC2
63 #define CONFIG_TSEC3
64 #define CONFIG_HAS_ETH0
65 #define CONFIG_HAS_ETH1
66 #define CONFIG_HAS_ETH2
67 #define CONFIG_ETHADDR          00:06:3B:FF:FF:FF
68 #define CONFIG_ETH1ADDR         00:06:3B:FF:FF:FE
69 #define CONFIG_ETH2ADDR         00:06:3B:FF:FF:FD
70 #define CONFIG_IPADDR           192.168.1.81
71 #define CONFIG_IPADDR1          192.168.1.82
72 #define CONFIG_IPADDR2          192.168.1.83
73 #define CONFIG_SERVERIP         192.168.1.80
74 #define CONFIG_GATEWAYIP        102.168.1.1
75 #define CONFIG_NETMASK          255.255.255.0
76 #define CONFIG_ETHPRIME         "eTSEC1"
77
78 #ifndef CONFIG_SPI_FLASH
79 #endif
80 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
81
82 #define CONFIG_SYS_L2_SIZE      (256 << 10)
83
84 #define CONFIG_LAST_STAGE_INIT
85
86 #endif
87
88 #ifdef CONFIG_SDCARD
89 #define CONFIG_RAMBOOT_SDCARD
90 #define CONFIG_SYS_RAMBOOT
91 #define CONFIG_SYS_EXTRA_ENV_RELOC
92 #define CONFIG_SYS_TEXT_BASE            0x11000000
93 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
94 #endif
95
96 #ifdef CONFIG_SPIFLASH
97 #define CONFIG_RAMBOOT_SPIFLASH
98 #define CONFIG_SYS_RAMBOOT
99 #define CONFIG_SYS_EXTRA_ENV_RELOC
100 #define CONFIG_SYS_TEXT_BASE            0x11000000
101 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
102 #endif
103
104 #ifndef CONFIG_SYS_TEXT_BASE
105 #define CONFIG_SYS_TEXT_BASE            0xeff80000
106 #endif
107 #define CONFIG_SYS_TEXT_BASE_NOR        0xeff80000
108
109 #ifndef CONFIG_RESET_VECTOR_ADDRESS
110 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
111 #endif
112
113 #ifndef CONFIG_SYS_MONITOR_BASE
114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
115 #endif
116
117 #define CONFIG_MP
118
119 #define CONFIG_ENV_OVERWRITE
120
121 #define CONFIG_SYS_SATA_MAX_DEVICE      2
122 #define CONFIG_LBA48
123
124 #define CONFIG_SYS_CLK_FREQ     66666666
125 #define CONFIG_DDR_CLK_FREQ     66666666
126
127 #define CONFIG_HWCONFIG
128
129 /*
130  * These can be toggled for performance analysis, otherwise use default.
131  */
132 #define CONFIG_L2_CACHE
133 #define CONFIG_BTB
134
135 #define CONFIG_ENABLE_36BIT_PHYS
136
137 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
138 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
139
140 #define CONFIG_SYS_CCSRBAR              0xffe00000
141 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
142
143 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
144        SPL code*/
145 #ifdef CONFIG_SPL_BUILD
146 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
147 #endif
148
149 /* DDR Setup */
150 #define CONFIG_DDR_ECC_ENABLE
151 #ifndef CONFIG_DDR_ECC_ENABLE
152 #define CONFIG_SYS_DDR_RAW_TIMING
153 #define CONFIG_DDR_SPD
154 #endif
155 #define CONFIG_SYS_SPD_BUS_NUM 1
156 #undef CONFIG_FSL_DDR_INTERACTIVE
157
158 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_512M
159 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
160 #define CONFIG_SYS_SDRAM_SIZE           (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
161 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
162 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
163
164 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
165
166 /* Default settings for DDR3 */
167 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
168 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
169 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
170 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007f
171 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014302
172 #define CONFIG_SYS_DDR_CS1_CONFIG_2     0x00000000
173
174 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
175 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
176 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
177 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
178
179 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
180 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8655A608
181 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
182 #define CONFIG_SYS_DDR_RCW_1            0x00000000
183 #define CONFIG_SYS_DDR_RCW_2            0x00000000
184 #ifdef CONFIG_DDR_ECC_ENABLE
185 #define CONFIG_SYS_DDR_CONTROL          0xE70C0000      /* Type = DDR3 & ECC */
186 #else
187 #define CONFIG_SYS_DDR_CONTROL          0xC70C0000      /* Type = DDR3 */
188 #endif
189 #define CONFIG_SYS_DDR_CONTROL_2        0x04401050
190 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
191 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
192
193 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
194 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
195 #define CONFIG_SYS_DDR_TIMING_1         0x6f6B4846
196 #define CONFIG_SYS_DDR_TIMING_2         0x0FA8C8CF
197 #define CONFIG_SYS_DDR_CLK_CTRL         0x03000000
198 #define CONFIG_SYS_DDR_MODE_1           0x40461520
199 #define CONFIG_SYS_DDR_MODE_2           0x8000c000
200 #define CONFIG_SYS_DDR_INTERVAL         0x0C300000
201
202 #undef CONFIG_CLOCKS_IN_MHZ
203
204 /*
205  * Memory map
206  *
207  * 0x0000_0000 0x7fff_ffff      DDR             Up to 2GB cacheable
208  * 0x8000_0000 0xdfff_ffff      PCI Express Mem 1G non-cacheable(PCIe * 2)
209  * 0xec00_0000 0xefff_ffff      NOR flash       Up to 64M non-cacheable CS0/1
210  * 0xf8f8_0000 0xf8ff_ffff      L2 SRAM         Up to 256K cacheable
211  *   (early boot only)
212  * 0xffc0_0000 0xffc3_ffff      PCI IO range    256k non-cacheable
213  * 0xffd0_0000 0xffd0_3fff      L1 for stack    16K cacheable
214  * 0xffe0_0000 0xffef_ffff      CCSR            1M non-cacheable
215  */
216
217 /*
218  * Local Bus Definitions
219  */
220 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
221 #define CONFIG_SYS_FLASH_BASE           0xec000000
222
223 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
224
225 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
226         | BR_PS_16 | BR_V)
227
228 #define CONFIG_FLASH_OR_PRELIM          0xfc000ff7
229
230 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
231 #define CONFIG_SYS_FLASH_QUIET_TEST
232 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
233
234 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
235
236 #undef CONFIG_SYS_FLASH_CHECKSUM
237 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
238 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
239
240 #define CONFIG_FLASH_CFI_DRIVER
241 #define CONFIG_SYS_FLASH_CFI
242 #define CONFIG_SYS_FLASH_EMPTY_INFO
243 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
244
245 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
246
247 #define CONFIG_SYS_INIT_RAM_LOCK
248 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
249 /* Initial L1 address */
250 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
251 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
252 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
253 /* Size of used area in RAM */
254 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
255
256 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
257                                         GENERATED_GBL_DATA_SIZE)
258 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
259
260 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)/* Reserve 256 kB for Mon */
261 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)/* Reserved for malloc */
262
263 #define CONFIG_SYS_PMC_BASE     0xff980000
264 #define CONFIG_SYS_PMC_BASE_PHYS        CONFIG_SYS_PMC_BASE
265 #define CONFIG_PMC_BR_PRELIM    (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
266                                         BR_PS_8 | BR_V)
267 #define CONFIG_PMC_OR_PRELIM    (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
268                                  OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
269                                  OR_GPCM_EAD)
270
271 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
272 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
273 #ifdef CONFIG_NAND_FSL_ELBC
274 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
275 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
276 #endif
277
278 /* Serial Port - controlled on board with jumper J8
279  * open - index 2
280  * shorted - index 1
281  */
282 #define CONFIG_CONS_INDEX               1
283 #undef CONFIG_SERIAL_SOFTWARE_FIFO
284 #define CONFIG_SYS_NS16550_SERIAL
285 #define CONFIG_SYS_NS16550_REG_SIZE     1
286 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
287 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
288 #define CONFIG_NS16550_MIN_FUNCTIONS
289 #endif
290
291 #define CONFIG_SYS_BAUDRATE_TABLE       \
292         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
293
294 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
295 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
296
297 /* I2C */
298 #define CONFIG_SYS_I2C
299 #define CONFIG_SYS_I2C_FSL
300 #define CONFIG_SYS_FSL_I2C_SPEED        400000
301 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
302 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
303 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
304 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
305 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
306 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
307 #define CONFIG_SYS_SPD_BUS_NUM          1 /* For rom_loc and flash bank */
308
309 #define CONFIG_RTC_DS1337
310 #define CONFIG_RTC_DS1337_NOOSC
311 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
312 #define CONFIG_SYS_I2C_PCA9557_ADDR     0x18
313 #define CONFIG_SYS_I2C_NCT72_ADDR       0x4C
314 #define CONFIG_SYS_I2C_IDT6V49205B      0x69
315
316 /*
317  * eSPI - Enhanced SPI
318  */
319 #define CONFIG_HARD_SPI
320
321 #define CONFIG_SF_DEFAULT_SPEED         10000000
322 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
323
324 #if defined(CONFIG_PCI)
325 /*
326  * General PCI
327  * Memory space is mapped 1-1, but I/O space must start from 0.
328  */
329
330 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
331 #define CONFIG_SYS_PCIE2_NAME           "PCIe SLOT CON9"
332 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
333 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
334 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
335 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
336 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
337 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
338 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
339 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
340
341 /* controller 1, Slot 2, tgtid 1, Base address a000 */
342 #define CONFIG_SYS_PCIE1_NAME           "PCIe SLOT CON10"
343 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
344 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
345 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
346 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
347 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
348 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
349 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
350 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
351
352 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
353 #endif /* CONFIG_PCI */
354
355 /*
356  * Environment
357  */
358 #ifdef CONFIG_ENV_FIT_UCBOOT
359
360 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x20000)
361 #define CONFIG_ENV_SIZE         0x20000
362 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
363
364 #else
365
366 #define CONFIG_ENV_SPI_BUS      0
367 #define CONFIG_ENV_SPI_CS       0
368 #define CONFIG_ENV_SPI_MAX_HZ   10000000
369 #define CONFIG_ENV_SPI_MODE     0
370
371 #ifdef CONFIG_RAMBOOT_SPIFLASH
372
373 #define CONFIG_ENV_SIZE         0x3000          /* 12KB */
374 #define CONFIG_ENV_OFFSET       0x2000          /* 8KB */
375 #define CONFIG_ENV_SECT_SIZE    0x1000
376
377 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
378 /* Address and size of Redundant Environment Sector     */
379 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
380 #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
381 #endif
382
383 #elif defined(CONFIG_RAMBOOT_SDCARD)
384 #define CONFIG_FSL_FIXED_MMC_LOCATION
385 #define CONFIG_ENV_SIZE         0x2000
386 #define CONFIG_SYS_MMC_ENV_DEV  0
387
388 #elif defined(CONFIG_SYS_RAMBOOT)
389 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
390 #define CONFIG_ENV_SIZE         0x2000
391
392 #else
393 #define CONFIG_ENV_BASE         (CONFIG_SYS_FLASH_BASE)
394 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
395 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
396 #define CONFIG_ENV_ADDR         (CONFIG_ENV_BASE + 0xC0000)
397 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
398 /* Address and size of Redundant Environment Sector     */
399 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
400 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
401 #endif
402
403 #endif
404
405 #endif  /* CONFIG_ENV_FIT_UCBOOT */
406
407 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
408 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
409
410 /*
411  * USB
412  */
413 #define CONFIG_HAS_FSL_DR_USB
414
415 #if defined(CONFIG_HAS_FSL_DR_USB)
416 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
417
418 #ifdef CONFIG_USB_EHCI_HCD
419 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
420 #define CONFIG_USB_EHCI_FSL
421 #endif
422 #endif
423
424 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
425
426 #ifdef CONFIG_MMC
427 #define CONFIG_FSL_ESDHC
428 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
429 #define CONFIG_MMC_SPI
430 #endif
431
432 /* Misc Extra Settings */
433 #undef CONFIG_WATCHDOG  /* watchdog disabled */
434
435 /*
436  * Miscellaneous configurable options
437  */
438 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
439 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
440 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
441 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms tick */
442
443 /*
444  * For booting Linux, the board info and command line data
445  * have to be in the first 64 MB of memory, since this is
446  * the maximum mapped by the Linux kernel during initialization.
447  */
448 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux*/
449 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
450
451 #if defined(CONFIG_CMD_KGDB)
452 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
453 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
454 #endif
455
456 /*
457  * Environment Configuration
458  */
459
460 #if defined(CONFIG_TSEC_ENET)
461
462 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
463 #else
464 #error "UCP1020 module revision is not defined !!!"
465 #endif
466
467 #define CONFIG_BOOTP_SERVERIP
468
469 #define CONFIG_MII              /* MII PHY management */
470 #define CONFIG_TSEC1_NAME       "eTSEC1"
471 #define CONFIG_TSEC2_NAME       "eTSEC2"
472 #define CONFIG_TSEC3_NAME       "eTSEC3"
473
474 #define TSEC1_PHY_ADDR  4
475 #define TSEC2_PHY_ADDR  0
476 #define TSEC2_PHY_ADDR_SGMII    0x00
477 #define TSEC3_PHY_ADDR  6
478
479 #define TSEC1_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
480 #define TSEC2_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
481 #define TSEC3_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
482
483 #define TSEC1_PHYIDX    0
484 #define TSEC2_PHYIDX    0
485 #define TSEC3_PHYIDX    0
486
487 #endif
488
489 #define CONFIG_HOSTNAME         UCP1020
490 #define CONFIG_ROOTPATH         "/opt/nfsroot"
491 #define CONFIG_BOOTFILE         "uImage"
492 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
493
494 /* default location for tftp and bootm */
495 #define CONFIG_LOADADDR         1000000
496
497 #if defined(CONFIG_DONGLE)
498
499 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
500 "bootcmd=run prog_spi_mbrbootcramfs\0"                                  \
501 "bootfile=uImage\0"                                                     \
502 "consoledev=ttyS0\0"                                                    \
503 "cramfsfile=image.cramfs\0"                                             \
504 "dtbaddr=0x00c00000\0"                                                  \
505 "dtbfile=image.dtb\0"                                                   \
506 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"                             \
507 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"                           \
508 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"                           \
509 "fileaddr=0x01000000\0"                                                 \
510 "filesize=0x00080000\0"                                                 \
511 "flashmbr=sf probe 0; "                                                 \
512         "tftp $loadaddr $mbr; "                                         \
513         "sf erase $mbr_offset +$filesize; "                             \
514         "sf write $loadaddr $mbr_offset $filesize\0"                    \
515 "flashrecovery=tftp $recoveryaddr $cramfsfile; "                        \
516         "protect off $nor_recoveryaddr +$filesize; "                    \
517         "erase $nor_recoveryaddr +$filesize; "                          \
518         "cp.b $recoveryaddr $nor_recoveryaddr $filesize; "              \
519         "protect on $nor_recoveryaddr +$filesize\0 "                    \
520 "flashuboot=tftp $ubootaddr $ubootfile; "                               \
521         "protect off $nor_ubootaddr +$filesize; "                       \
522         "erase $nor_ubootaddr +$filesize; "                             \
523         "cp.b $ubootaddr $nor_ubootaddr $filesize; "                    \
524         "protect on $nor_ubootaddr +$filesize\0 "                       \
525 "flashworking=tftp $workingaddr $cramfsfile; "                          \
526         "protect off $nor_workingaddr +$filesize; "                     \
527         "erase $nor_workingaddr +$filesize; "                           \
528         "cp.b $workingaddr $nor_workingaddr $filesize; "                \
529         "protect on $nor_workingaddr +$filesize\0 "                     \
530 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 "                           \
531 "kerneladdr=0x01100000\0"                                               \
532 "kernelfile=uImage\0"                                                   \
533 "loadaddr=0x01000000\0"                                                 \
534 "mbr=uCP1020d.mbr\0"                                                    \
535 "mbr_offset=0x00000000\0"                                               \
536 "mmbr=uCP1020Quiet.mbr\0"                                               \
537 "mmcpart=0:2\0"                                                         \
538 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; "                       \
539         "mmc erase 1 1; "                                               \
540         "mmc write $loadaddr 1 1\0"                                     \
541 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; "                \
542         "mmc erase 0x40 0x400; "                                        \
543         "mmc write $loadaddr 0x40 0x400\0"                              \
544 "netdev=eth0\0"                                                         \
545 "nor_recoveryaddr=0xEC0A0000\0"                                         \
546 "nor_ubootaddr=0xEFF80000\0"                                            \
547 "nor_workingaddr=0xECFA0000\0"                                          \
548 "norbootrecovery=setenv bootargs $recoverybootargs"                     \
549         " console=$consoledev,$baudrate $othbootargs; "                 \
550         "run norloadrecovery; "                                         \
551         "bootm $kerneladdr - $dtbaddr\0"                                \
552 "norbootworking=setenv bootargs $workingbootargs"                       \
553         " console=$consoledev,$baudrate $othbootargs; "                 \
554         "run norloadworking; "                                          \
555         "bootm $kerneladdr - $dtbaddr\0"                                \
556 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; "                     \
557         "setenv cramfsaddr $nor_recoveryaddr; "                         \
558         "cramfsload $dtbaddr $dtbfile; "                                \
559         "cramfsload $kerneladdr $kernelfile\0"                          \
560 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; "                      \
561         "setenv cramfsaddr $nor_workingaddr; "                          \
562         "cramfsload $dtbaddr $dtbfile; "                                \
563         "cramfsload $kerneladdr $kernelfile\0"                          \
564 "prog_spi_mbr=run spi__mbr\0"                                           \
565 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0"       \
566 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
567         "run spi__cramfs\0"                                             \
568 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro"   \
569         " console=$consoledev,$baudrate $othbootargs; "                 \
570         "tftp $rootfsaddr $rootfsfile; "                                \
571         "tftp $loadaddr $kernelfile; "                                  \
572         "tftp $dtbaddr $dtbfile; "                                      \
573         "bootm $loadaddr $rootfsaddr $dtbaddr\0"                        \
574 "ramdisk_size=120000\0"                                                 \
575 "ramdiskfile=rootfs.ext2.gz.uboot\0"                                    \
576 "recoveryaddr=0x02F00000\0"                                             \
577 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0"           \
578 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; "  \
579         "mw.l 0xffe0f008 0x00400000\0"                                  \
580 "rootfsaddr=0x02F00000\0"                                               \
581 "rootfsfile=rootfs.ext2.gz.uboot\0"                                     \
582 "rootpath=/opt/nfsroot\0"                                               \
583 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; "                \
584         "protect off 0xeC000000 +$filesize; "                           \
585         "erase 0xEC000000 +$filesize; "                                 \
586         "cp.b $loadaddr 0xEC000000 $filesize; "                         \
587         "cmp.b $loadaddr 0xEC000000 $filesize; "                        \
588         "protect on 0xeC000000 +$filesize\0"                            \
589 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; "                \
590         "protect off 0xeFF80000 +$filesize; "                           \
591         "erase 0xEFF80000 +$filesize; "                                 \
592         "cp.b $loadaddr 0xEFF80000 $filesize; "                         \
593         "cmp.b $loadaddr 0xEFF80000 $filesize; "                        \
594         "protect on 0xeFF80000 +$filesize\0"                            \
595 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; "                   \
596         "sf probe 0; sf erase 0x8000 +$filesize; "                      \
597         "sf write $loadaddr 0x8000 $filesize\0"                         \
598 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; "             \
599         "protect off 0xec0a0000 +$filesize; "                           \
600         "erase 0xeC0A0000 +$filesize; "                                 \
601         "cp.b $loadaddr 0xeC0A0000 $filesize; "                         \
602         "protect on 0xec0a0000 +$filesize\0"                            \
603 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; "                       \
604         "sf probe 1; sf erase 0 +$filesize; "                           \
605         "sf write $loadaddr 0 $filesize\0"                              \
606 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; "                       \
607         "sf probe 0; sf erase 0 +$filesize; "                           \
608         "sf write $loadaddr 0 $filesize\0"                              \
609 "tftpflash=tftpboot $loadaddr $uboot; "                                 \
610         "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
611         "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; "  \
612         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
613         "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
614         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
615 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0"                            \
616 "ubootaddr=0x01000000\0"                                                \
617 "ubootfile=u-boot.bin\0"                                                \
618 "ubootd=u-boot4dongle.bin\0"                                            \
619 "upgrade=run flashworking\0"                                            \
620 "usb_phy_type=ulpi\0 "                                                  \
621 "workingaddr=0x02F00000\0"                                              \
622 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
623
624 #else
625
626 #if defined(CONFIG_UCP1020T1)
627
628 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
629 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0"  \
630 "bootfile=uImage\0"                                                     \
631 "consoledev=ttyS0\0"                                                    \
632 "cramfsfile=image.cramfs\0"                                             \
633 "dtbaddr=0x00c00000\0"                                                  \
634 "dtbfile=image.dtb\0"                                                   \
635 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"                             \
636 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"                           \
637 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"                           \
638 "fileaddr=0x01000000\0"                                                 \
639 "filesize=0x00080000\0"                                                 \
640 "flashmbr=sf probe 0; "                                                 \
641         "tftp $loadaddr $mbr; "                                         \
642         "sf erase $mbr_offset +$filesize; "                             \
643         "sf write $loadaddr $mbr_offset $filesize\0"                    \
644 "flashrecovery=tftp $recoveryaddr $cramfsfile; "                        \
645         "protect off $nor_recoveryaddr +$filesize; "                    \
646         "erase $nor_recoveryaddr +$filesize; "                          \
647         "cp.b $recoveryaddr $nor_recoveryaddr $filesize; "              \
648         "protect on $nor_recoveryaddr +$filesize\0 "                    \
649 "flashuboot=tftp $ubootaddr $ubootfile; "                               \
650         "protect off $nor_ubootaddr +$filesize; "                       \
651         "erase $nor_ubootaddr +$filesize; "                             \
652         "cp.b $ubootaddr $nor_ubootaddr $filesize; "                    \
653         "protect on $nor_ubootaddr +$filesize\0 "                       \
654 "flashworking=tftp $workingaddr $cramfsfile; "                          \
655         "protect off $nor_workingaddr +$filesize; "                     \
656         "erase $nor_workingaddr +$filesize; "                           \
657         "cp.b $workingaddr $nor_workingaddr $filesize; "                \
658         "protect on $nor_workingaddr +$filesize\0 "                     \
659 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 "                           \
660 "kerneladdr=0x01100000\0"                                               \
661 "kernelfile=uImage\0"                                                   \
662 "loadaddr=0x01000000\0"                                                 \
663 "mbr=uCP1020.mbr\0"                                                     \
664 "mbr_offset=0x00000000\0"                                               \
665 "netdev=eth0\0"                                                         \
666 "nor_recoveryaddr=0xEC0A0000\0"                                         \
667 "nor_ubootaddr=0xEFF80000\0"                                            \
668 "nor_workingaddr=0xECFA0000\0"                                          \
669 "norbootrecovery=setenv bootargs $recoverybootargs"                     \
670         " console=$consoledev,$baudrate $othbootargs; "                 \
671         "run norloadrecovery; "                                         \
672         "bootm $kerneladdr - $dtbaddr\0"                                \
673 "norbootworking=setenv bootargs $workingbootargs"                       \
674         " console=$consoledev,$baudrate $othbootargs; "                 \
675         "run norloadworking; "                                          \
676         "bootm $kerneladdr - $dtbaddr\0"                                \
677 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; "                     \
678         "setenv cramfsaddr $nor_recoveryaddr; "                         \
679         "cramfsload $dtbaddr $dtbfile; "                                \
680         "cramfsload $kerneladdr $kernelfile\0"                          \
681 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; "                      \
682         "setenv cramfsaddr $nor_workingaddr; "                          \
683         "cramfsload $dtbaddr $dtbfile; "                                \
684         "cramfsload $kerneladdr $kernelfile\0"                          \
685 "othbootargs=quiet\0"                                                   \
686 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro"   \
687         " console=$consoledev,$baudrate $othbootargs; "                 \
688         "tftp $rootfsaddr $rootfsfile; "                                \
689         "tftp $loadaddr $kernelfile; "                                  \
690         "tftp $dtbaddr $dtbfile; "                                      \
691         "bootm $loadaddr $rootfsaddr $dtbaddr\0"                        \
692 "ramdisk_size=120000\0"                                                 \
693 "ramdiskfile=rootfs.ext2.gz.uboot\0"                                    \
694 "recoveryaddr=0x02F00000\0"                                             \
695 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0"           \
696 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; "  \
697         "mw.l 0xffe0f008 0x00400000\0"                                  \
698 "rootfsaddr=0x02F00000\0"                                               \
699 "rootfsfile=rootfs.ext2.gz.uboot\0"                                     \
700 "rootpath=/opt/nfsroot\0"                                               \
701 "silent=1\0"                                                            \
702 "tftpflash=tftpboot $loadaddr $uboot; "                                 \
703         "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
704         "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; "  \
705         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
706         "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
707         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
708 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0"                            \
709 "ubootaddr=0x01000000\0"                                                \
710 "ubootfile=u-boot.bin\0"                                                \
711 "upgrade=run flashworking\0"                                            \
712 "workingaddr=0x02F00000\0"                                              \
713 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
714
715 #else /* For Arcturus Modules */
716
717 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
718 "bootcmd=run norkernel\0"                                               \
719 "bootfile=uImage\0"                                                     \
720 "consoledev=ttyS0\0"                                                    \
721 "dtbaddr=0x00c00000\0"                                                  \
722 "dtbfile=image.dtb\0"                                                   \
723 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"                             \
724 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"                           \
725 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"                           \
726 "fileaddr=0x01000000\0"                                                 \
727 "filesize=0x00080000\0"                                                 \
728 "flashmbr=sf probe 0; "                                                 \
729         "tftp $loadaddr $mbr; "                                         \
730         "sf erase $mbr_offset +$filesize; "                             \
731         "sf write $loadaddr $mbr_offset $filesize\0"                    \
732 "flashuboot=tftp $loadaddr $ubootfile; "                                \
733         "protect off $nor_ubootaddr0 +$filesize; "                      \
734         "erase $nor_ubootaddr0 +$filesize; "                            \
735         "cp.b $loadaddr $nor_ubootaddr0 $filesize; "                    \
736         "protect on $nor_ubootaddr0 +$filesize; "                       \
737         "protect off $nor_ubootaddr1 +$filesize; "                      \
738         "erase $nor_ubootaddr1 +$filesize; "                            \
739         "cp.b $loadaddr $nor_ubootaddr1 $filesize; "                    \
740         "protect on $nor_ubootaddr1 +$filesize\0 "                      \
741 "format0=protect off $part0base +$part0size; "                          \
742         "erase $part0base +$part0size\0"                                \
743 "format1=protect off $part1base +$part1size; "                          \
744         "erase $part1base +$part1size\0"                                \
745 "format2=protect off $part2base +$part2size; "                          \
746         "erase $part2base +$part2size\0"                                \
747 "format3=protect off $part3base +$part3size; "                          \
748         "erase $part3base +$part3size\0"                                \
749 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 "                           \
750 "kerneladdr=0x01100000\0"                                               \
751 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"                 \
752 "kernelfile=uImage\0"                                                   \
753 "loadaddr=0x01000000\0"                                                 \
754 "mbr=uCP1020.mbr\0"                                                     \
755 "mbr_offset=0x00000000\0"                                               \
756 "netdev=eth0\0"                                                         \
757 "nor_ubootaddr0=0xEC000000\0"                                           \
758 "nor_ubootaddr1=0xEFF80000\0"                                           \
759 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
760         "run norkernelload; "                                           \
761         "bootm $kerneladdr - $dtbaddr\0"                                \
762 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; "                       \
763         "setenv cramfsaddr $part0base; "                                \
764         "cramfsload $dtbaddr $dtbfile; "                                \
765         "cramfsload $kerneladdr $kernelfile\0"                          \
766 "part0base=0xEC100000\0"                                                \
767 "part0size=0x00700000\0"                                                \
768 "part1base=0xEC800000\0"                                                \
769 "part1size=0x02000000\0"                                                \
770 "part2base=0xEE800000\0"                                                \
771 "part2size=0x00800000\0"                                                \
772 "part3base=0xEF000000\0"                                                \
773 "part3size=0x00F80000\0"                                                \
774 "partENVbase=0xEC080000\0"                                              \
775 "partENVsize=0x00080000\0"                                              \
776 "program0=tftp part0-000000.bin; "                                      \
777         "protect off $part0base +$filesize; "                           \
778         "erase $part0base +$filesize; "                                 \
779         "cp.b $loadaddr $part0base $filesize; "                         \
780         "echo Verifying...; "                                           \
781         "cmp.b $loadaddr $part0base $filesize\0"                        \
782 "program1=tftp part1-000000.bin; "                                      \
783         "protect off $part1base +$filesize; "                           \
784         "erase $part1base +$filesize; "                                 \
785         "cp.b $loadaddr $part1base $filesize; "                         \
786         "echo Verifying...; "                                           \
787         "cmp.b $loadaddr $part1base $filesize\0"                        \
788 "program2=tftp part2-000000.bin; "                                      \
789         "protect off $part2base +$filesize; "                           \
790         "erase $part2base +$filesize; "                                 \
791         "cp.b $loadaddr $part2base $filesize; "                         \
792         "echo Verifying...; "                                           \
793         "cmp.b $loadaddr $part2base $filesize\0"                        \
794 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro"   \
795         "  console=$consoledev,$baudrate $othbootargs; "                \
796         "tftp $rootfsaddr $rootfsfile; "                                \
797         "tftp $loadaddr $kernelfile; "                                  \
798         "tftp $dtbaddr $dtbfile; "                                      \
799         "bootm $loadaddr $rootfsaddr $dtbaddr\0"                        \
800 "ramdisk_size=120000\0"                                                 \
801 "ramdiskfile=rootfs.ext2.gz.uboot\0"                                    \
802 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; "  \
803         "mw.l 0xffe0f008 0x00400000\0"                                  \
804 "rootfsaddr=0x02F00000\0"                                               \
805 "rootfsfile=rootfs.ext2.gz.uboot\0"                                     \
806 "rootpath=/opt/nfsroot\0"                                               \
807 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; "                       \
808         "sf probe 0; sf erase 0 +$filesize; "                           \
809         "sf write $loadaddr 0 $filesize\0"                              \
810 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; "                 \
811         "protect off 0xeC000000 +$filesize; "                           \
812         "erase 0xEC000000 +$filesize; "                                 \
813         "cp.b $loadaddr 0xEC000000 $filesize; "                         \
814         "cmp.b $loadaddr 0xEC000000 $filesize; "                        \
815         "protect on 0xeC000000 +$filesize\0"                            \
816 "tftpflash=tftpboot $loadaddr $uboot; "                                 \
817         "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
818         "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; "  \
819         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
820         "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
821         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
822 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0"                            \
823 "ubootfile=u-boot.bin\0"                                                \
824 "upgrade=run flashuboot\0"                                              \
825 "usb_phy_type=ulpi\0 "                                                  \
826 "boot_nfs= "                                                            \
827         "setenv bootargs root=/dev/nfs rw "                             \
828         "nfsroot=$serverip:$rootpath "                                  \
829         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
830         "console=$consoledev,$baudrate $othbootargs;"                   \
831         "tftp $loadaddr $bootfile;"                                     \
832         "tftp $fdtaddr $fdtfile;"                                       \
833         "bootm $loadaddr - $fdtaddr\0"                                  \
834 "boot_hd = "                                                            \
835         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "              \
836         "console=$consoledev,$baudrate $othbootargs;"                   \
837         "usb start;"                                                    \
838         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"                   \
839         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"                     \
840         "bootm $loadaddr - $fdtaddr\0"                                  \
841 "boot_usb_fat = "                                                       \
842         "setenv bootargs root=/dev/ram rw "                             \
843         "console=$consoledev,$baudrate $othbootargs "                   \
844         "ramdisk_size=$ramdisk_size;"                                   \
845         "usb start;"                                                    \
846         "fatload usb 0:2 $loadaddr $bootfile;"                          \
847         "fatload usb 0:2 $fdtaddr $fdtfile;"                            \
848         "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"                    \
849         "bootm $loadaddr $ramdiskaddr $fdtaddr\0 "                      \
850 "boot_usb_ext2 = "                                                      \
851         "setenv bootargs root=/dev/ram rw "                             \
852         "console=$consoledev,$baudrate $othbootargs "                   \
853         "ramdisk_size=$ramdisk_size;"                                   \
854         "usb start;"                                                    \
855         "ext2load usb 0:4 $loadaddr $bootfile;"                         \
856         "ext2load usb 0:4 $fdtaddr $fdtfile;"                           \
857         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"                   \
858         "bootm $loadaddr $ramdiskaddr $fdtaddr\0 "                      \
859 "boot_nor = "                                                           \
860         "setenv bootargs root=/dev/$jffs2nor rw "                       \
861         "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
862         "bootm $norbootaddr - $norfdtaddr\0 "                           \
863 "boot_ram = "                                                           \
864         "setenv bootargs root=/dev/ram rw "                             \
865         "console=$consoledev,$baudrate $othbootargs "                   \
866         "ramdisk_size=$ramdisk_size;"                                   \
867         "tftp $ramdiskaddr $ramdiskfile;"                               \
868         "tftp $loadaddr $bootfile;"                                     \
869         "tftp $fdtaddr $fdtfile;"                                       \
870         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
871
872 #endif
873 #endif
874
875 #endif /* __CONFIG_H */