2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
8 * SPDX-License-Identifier: GPL-2.0+
12 * board/config.h - configuration options, board specific
19 * High Level Configuration Options
23 #define CONFIG_MPC885 1 /* This is a MPC885 CPU */
24 #define CONFIG_TQM885D 1 /* ...on a TQM88D module */
26 #define CONFIG_SYS_TEXT_BASE 0x40000000
28 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
29 #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
30 #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
31 #define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
32 /* (it will be used if there is no */
33 /* 'cpuclk' variable with valid value) */
35 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
36 #define CONFIG_SYS_SMC_RXBUFLEN 128
37 #define CONFIG_SYS_MAXIDLE 10
38 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
40 #define CONFIG_BOOTCOUNT_LIMIT
42 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
44 #define CONFIG_BOARD_TYPES 1 /* support board types */
46 #define CONFIG_PREBOOT "echo;" \
47 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
50 #undef CONFIG_BOOTARGS
52 #define CONFIG_EXTRA_ENV_SETTINGS \
54 "nfsargs=setenv bootargs root=/dev/nfs rw " \
55 "nfsroot=${serverip}:${rootpath}\0" \
56 "ramargs=setenv bootargs root=/dev/ram rw\0" \
57 "addip=setenv bootargs ${bootargs} " \
58 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
59 ":${hostname}:${netdev}:off panic=1\0" \
60 "flash_nfs=run nfsargs addip;" \
61 "bootm ${kernel_addr}\0" \
62 "flash_self=run ramargs addip;" \
63 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
64 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
65 "rootpath=/opt/eldk/ppc_8xx\0" \
66 "bootfile=/tftpboot/TQM885D/uImage\0" \
67 "fdt_addr=400C0000\0" \
68 "kernel_addr=40100000\0" \
69 "ramdisk_addr=40280000\0" \
70 "load=tftp 200000 ${u-boot}\0" \
71 "update=protect off 40000000 +${filesize};" \
72 "erase 40000000 +${filesize};" \
73 "cp.b 200000 40000000 ${filesize};" \
74 "protect on 40000000 +${filesize}\0" \
76 #define CONFIG_BOOTCOMMAND "run flash_self"
78 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
79 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
81 #undef CONFIG_WATCHDOG /* watchdog disabled */
83 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
85 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
87 /* enable I2C and select the hardware/software driver */
88 #define CONFIG_SYS_I2C
89 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
90 #define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
91 #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
93 * Software (bit-bang) I2C driver configuration
95 #define PB_SCL 0x00000020 /* PB 26 */
96 #define PB_SDA 0x00000010 /* PB 27 */
98 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
99 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
100 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
101 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
102 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
103 else immr->im_cpm.cp_pbdat &= ~PB_SDA
104 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
105 else immr->im_cpm.cp_pbdat &= ~PB_SCL
106 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
108 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
109 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
110 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
111 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
113 # define CONFIG_RTC_DS1337 1
114 # define CONFIG_SYS_I2C_RTC_ADDR 0x68
119 #define CONFIG_BOOTP_SUBNETMASK
120 #define CONFIG_BOOTP_GATEWAY
121 #define CONFIG_BOOTP_HOSTNAME
122 #define CONFIG_BOOTP_BOOTPATH
123 #define CONFIG_BOOTP_BOOTFILESIZE
126 #define CONFIG_MAC_PARTITION
127 #define CONFIG_DOS_PARTITION
129 #undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
131 #define CONFIG_TIMESTAMP /* but print image timestmps */
135 * Command line configuration.
137 #include <config_cmd_default.h>
139 #define CONFIG_CMD_ASKENV
140 #define CONFIG_CMD_DATE
141 #define CONFIG_CMD_DHCP
142 #define CONFIG_CMD_EEPROM
143 #define CONFIG_CMD_EXT2
144 #define CONFIG_CMD_I2C
145 #define CONFIG_CMD_IDE
146 #define CONFIG_CMD_MII
147 #define CONFIG_CMD_NFS
148 #define CONFIG_CMD_PING
152 * Miscellaneous configurable options
154 #define CONFIG_SYS_LONGHELP /* undef to save memory */
156 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
157 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
159 #if defined(CONFIG_CMD_KGDB)
160 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
162 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
164 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
165 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
166 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
168 #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
169 #define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
170 #define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive
173 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
176 * Enable loopw command.
181 * Low Level Configuration Settings
182 * (address mappings, register initial values, etc.)
183 * You should know what you are doing if you make changes here.
185 /*-----------------------------------------------------------------------
186 * Internal Memory Mapped Register
188 #define CONFIG_SYS_IMMR 0xFFF00000
190 /*-----------------------------------------------------------------------
191 * Definitions for initial stack pointer and data area (in DPRAM)
193 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
194 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
195 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
196 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
198 /*-----------------------------------------------------------------------
199 * Start addresses for the final memory configuration
200 * (Set up by the startup code)
201 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
203 #define CONFIG_SYS_SDRAM_BASE 0x00000000
204 #define CONFIG_SYS_FLASH_BASE 0x40000000
205 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
206 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
207 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
210 * For booting Linux, the board info and command line data
211 * have to be in the first 8 MB of memory, since this is
212 * the maximum mapped by the Linux kernel during initialization.
214 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
216 /*-----------------------------------------------------------------------
220 /* use CFI flash driver */
221 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
222 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
223 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
224 #define CONFIG_SYS_FLASH_EMPTY_INFO
225 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
226 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
227 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
229 #define CONFIG_ENV_IS_IN_FLASH 1
230 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
231 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
232 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
234 /* Address and size of Redundant Environment Sector */
235 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
236 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
238 /*-----------------------------------------------------------------------
239 * Hardware Information Block
241 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
242 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
243 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
245 /*-----------------------------------------------------------------------
246 * Cache Configuration
248 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
249 #if defined(CONFIG_CMD_KGDB)
250 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
253 /*-----------------------------------------------------------------------
254 * SYPCR - System Protection Control 11-9
255 * SYPCR can only be written once after reset!
256 *-----------------------------------------------------------------------
257 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
259 #if defined(CONFIG_WATCHDOG)
260 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
261 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
263 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
266 /*-----------------------------------------------------------------------
267 * SIUMCR - SIU Module Configuration 11-6
268 *-----------------------------------------------------------------------
269 * PCMCIA config., multi-function pin tri-state
271 #ifndef CONFIG_CAN_DRIVER
272 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
273 #else /* we must activate GPL5 in the SIUMCR for CAN */
274 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
275 #endif /* CONFIG_CAN_DRIVER */
277 /*-----------------------------------------------------------------------
278 * TBSCR - Time Base Status and Control 11-26
279 *-----------------------------------------------------------------------
280 * Clear Reference Interrupt Status, Timebase freezing enabled
282 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
284 /*-----------------------------------------------------------------------
285 * PISCR - Periodic Interrupt Status and Control 11-31
286 *-----------------------------------------------------------------------
287 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
289 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
291 /*-----------------------------------------------------------------------
292 * SCCR - System Clock and reset Control Register 15-27
293 *-----------------------------------------------------------------------
294 * Set clock output, timebase and RTC source and divider,
295 * power management and some other internal clocks
297 #define SCCR_MASK SCCR_EBDF11
298 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
299 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
302 /*-----------------------------------------------------------------------
304 *-----------------------------------------------------------------------
307 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
308 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
309 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
310 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
311 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
312 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
313 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
314 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
316 /*-----------------------------------------------------------------------
317 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
318 *-----------------------------------------------------------------------
321 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
322 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
324 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
325 #undef CONFIG_IDE_LED /* LED for ide not supported */
326 #undef CONFIG_IDE_RESET /* reset for ide not supported */
328 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
329 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
331 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
333 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
335 /* Offset for data I/O */
336 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
338 /* Offset for normal register accesses */
339 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
341 /* Offset for alternate registers */
342 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
344 /*-----------------------------------------------------------------------
346 *-----------------------------------------------------------------------
349 #define CONFIG_SYS_DER 0
352 * Init Memory Controller:
354 * BR0/1 and OR0/1 (FLASH)
357 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
358 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
360 /* used to re-map FLASH both when starting from SRAM or FLASH:
361 * restrict access enough to keep SRAM working (if any)
362 * but not too much to meddle with FLASH accesses
364 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
365 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
368 * FLASH timing: Default value of OR0 after reset
370 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
371 OR_SCY_6_CLK | OR_TRLX)
373 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
374 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
375 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
377 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
378 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
379 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
382 * BR2/3 and OR2/3 (SDRAM)
385 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
386 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
387 #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
389 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
390 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
392 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
393 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
395 #ifndef CONFIG_CAN_DRIVER
396 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
397 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
398 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
399 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
400 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
401 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
402 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
403 BR_PS_8 | BR_MS_UPMB | BR_V )
404 #endif /* CONFIG_CAN_DRIVER */
407 * 4096 Rows from SDRAM example configuration
408 * 1000 factor s -> ms
409 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
410 * 4 Number of refresh cycles per period
411 * 64 Refresh cycle in ms per number of rows
413 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
416 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
418 * CPUclock(MHz) * 31.2
419 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
420 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
422 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
423 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
424 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
425 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
427 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
428 * be met also in the default configuration, i.e. if environment variable
429 * 'cpuclk' is not set.
431 #define CONFIG_SYS_MAMR_PTA 128
434 * Memory Periodic Timer Prescaler Register (MPTPR) values.
436 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
437 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
438 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
439 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
442 * MAMR settings for SDRAM
446 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
447 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
448 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
450 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
451 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
452 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
453 /* 10 column SDRAM */
454 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
455 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
456 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
459 * Network configuration
461 #define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
462 #define CONFIG_FEC_ENET /* enable ethernet on FEC */
463 #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
464 #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
466 #if defined(CONFIG_CMD_MII)
467 #define CONFIG_SYS_DISCOVER_PHY
468 #define CONFIG_MII_INIT 1
471 #define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
472 switching to another netwok (if the
473 tried network is unreachable) */
475 #define CONFIG_ETHPRIME "SCC"
477 /* pass open firmware flat tree */
478 #define CONFIG_OF_LIBFDT 1
479 #define CONFIG_OF_BOARD_SETUP 1
480 #define CONFIG_HWCONFIG 1
482 #endif /* __CONFIG_H */