2 * (C) Copyright 2000-2014
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_MPC860 1
21 #define CONFIG_MPC860T 1
22 #define CONFIG_MPC862 1
24 #define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
26 #define CONFIG_SYS_TEXT_BASE 0x40000000
28 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
29 #define CONFIG_SYS_SMC_RXBUFLEN 128
30 #define CONFIG_SYS_MAXIDLE 10
32 #define CONFIG_BOOTCOUNT_LIMIT
35 #define CONFIG_BOARD_TYPES 1 /* support board types */
37 #define CONFIG_PREBOOT "echo;" \
38 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
41 #undef CONFIG_BOOTARGS
43 #define CONFIG_EXTRA_ENV_SETTINGS \
45 "nfsargs=setenv bootargs root=/dev/nfs rw " \
46 "nfsroot=${serverip}:${rootpath}\0" \
47 "ramargs=setenv bootargs root=/dev/ram rw\0" \
48 "addip=setenv bootargs ${bootargs} " \
49 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
50 ":${hostname}:${netdev}:off panic=1\0" \
51 "flash_nfs=run nfsargs addip;" \
52 "bootm ${kernel_addr}\0" \
53 "flash_self=run ramargs addip;" \
54 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
55 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
56 "rootpath=/opt/eldk/ppc_8xx\0" \
57 "hostname=TQM862M\0" \
58 "bootfile=TQM862M/uImage\0" \
59 "fdt_addr=40080000\0" \
60 "kernel_addr=400A0000\0" \
61 "ramdisk_addr=40280000\0" \
62 "u-boot=TQM862M/u-image.bin\0" \
63 "load=tftp 200000 ${u-boot}\0" \
64 "update=prot off 40000000 +${filesize};" \
65 "era 40000000 +${filesize};" \
66 "cp.b 200000 40000000 ${filesize};" \
67 "sete filesize;save\0" \
69 #define CONFIG_BOOTCOMMAND "run flash_self"
71 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
72 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
74 #undef CONFIG_WATCHDOG /* watchdog disabled */
76 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
81 #define CONFIG_BOOTP_SUBNETMASK
82 #define CONFIG_BOOTP_GATEWAY
83 #define CONFIG_BOOTP_HOSTNAME
84 #define CONFIG_BOOTP_BOOTPATH
85 #define CONFIG_BOOTP_BOOTFILESIZE
87 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
90 * Command line configuration.
93 #define CONFIG_NETCONSOLE
96 * Miscellaneous configurable options
98 #define CONFIG_SYS_LONGHELP /* undef to save memory */
100 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
102 #if defined(CONFIG_CMD_KGDB)
103 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
105 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
107 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
108 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
109 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
111 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
112 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
114 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
117 * Low Level Configuration Settings
118 * (address mappings, register initial values, etc.)
119 * You should know what you are doing if you make changes here.
121 /*-----------------------------------------------------------------------
122 * Internal Memory Mapped Register
124 #define CONFIG_SYS_IMMR 0xFFF00000
126 /*-----------------------------------------------------------------------
127 * Definitions for initial stack pointer and data area (in DPRAM)
129 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
130 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
131 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
132 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
134 /*-----------------------------------------------------------------------
135 * Start addresses for the final memory configuration
136 * (Set up by the startup code)
137 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
139 #define CONFIG_SYS_SDRAM_BASE 0x00000000
140 #define CONFIG_SYS_FLASH_BASE 0x40000000
141 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
143 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
146 * For booting Linux, the board info and command line data
147 * have to be in the first 8 MB of memory, since this is
148 * the maximum mapped by the Linux kernel during initialization.
150 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
152 /*-----------------------------------------------------------------------
156 /* use CFI flash driver */
157 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
158 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
159 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
160 #define CONFIG_SYS_FLASH_EMPTY_INFO
161 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
162 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
163 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
165 #define CONFIG_ENV_IS_IN_FLASH 1
166 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
167 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
168 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
170 /* Address and size of Redundant Environment Sector */
171 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
172 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
174 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
176 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
178 /*-----------------------------------------------------------------------
179 * Dynamic MTD partition support
181 #define CONFIG_CMD_MTDPARTS
182 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
183 #define CONFIG_FLASH_CFI_MTD
184 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
186 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
192 /*-----------------------------------------------------------------------
193 * Hardware Information Block
195 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
196 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
197 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
199 /*-----------------------------------------------------------------------
200 * Cache Configuration
202 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
203 #if defined(CONFIG_CMD_KGDB)
204 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
207 /*-----------------------------------------------------------------------
208 * SYPCR - System Protection Control 11-9
209 * SYPCR can only be written once after reset!
210 *-----------------------------------------------------------------------
211 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
213 #if defined(CONFIG_WATCHDOG)
214 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
215 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
217 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
220 /*-----------------------------------------------------------------------
221 * SIUMCR - SIU Module Configuration 11-6
222 *-----------------------------------------------------------------------
223 * PCMCIA config., multi-function pin tri-state
225 #ifndef CONFIG_CAN_DRIVER
226 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
227 #else /* we must activate GPL5 in the SIUMCR for CAN */
228 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
229 #endif /* CONFIG_CAN_DRIVER */
231 /*-----------------------------------------------------------------------
232 * TBSCR - Time Base Status and Control 11-26
233 *-----------------------------------------------------------------------
234 * Clear Reference Interrupt Status, Timebase freezing enabled
236 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
238 /*-----------------------------------------------------------------------
239 * RTCSC - Real-Time Clock Status and Control Register 11-27
240 *-----------------------------------------------------------------------
242 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
244 /*-----------------------------------------------------------------------
245 * PISCR - Periodic Interrupt Status and Control 11-31
246 *-----------------------------------------------------------------------
247 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
249 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
251 /*-----------------------------------------------------------------------
252 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
253 *-----------------------------------------------------------------------
254 * Reset PLL lock status sticky bit, timer expired status bit and timer
255 * interrupt status bit
257 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
259 /*-----------------------------------------------------------------------
260 * SCCR - System Clock and reset Control Register 15-27
261 *-----------------------------------------------------------------------
262 * Set clock output, timebase and RTC source and divider,
263 * power management and some other internal clocks
265 #define SCCR_MASK SCCR_EBDF11
266 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
267 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
270 /*-----------------------------------------------------------------------
272 *-----------------------------------------------------------------------
275 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
276 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
277 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
278 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
279 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
280 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
281 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
282 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
284 /*-----------------------------------------------------------------------
285 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
286 *-----------------------------------------------------------------------
289 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
290 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
292 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
293 #undef CONFIG_IDE_LED /* LED for ide not supported */
294 #undef CONFIG_IDE_RESET /* reset for ide not supported */
296 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
297 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
299 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
301 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
303 /* Offset for data I/O */
304 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
306 /* Offset for normal register accesses */
307 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
309 /* Offset for alternate registers */
310 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
312 /*-----------------------------------------------------------------------
314 *-----------------------------------------------------------------------
317 #define CONFIG_SYS_DER 0
320 * Init Memory Controller:
322 * BR0/1 and OR0/1 (FLASH)
325 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
326 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
328 /* used to re-map FLASH both when starting from SRAM or FLASH:
329 * restrict access enough to keep SRAM working (if any)
330 * but not too much to meddle with FLASH accesses
332 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
333 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
338 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
339 OR_SCY_3_CLK | OR_EHTR | OR_BI)
341 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
342 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
343 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
345 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
346 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
347 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
350 * BR2/3 and OR2/3 (SDRAM)
353 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
354 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
355 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
357 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
358 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
360 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
361 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
363 #ifndef CONFIG_CAN_DRIVER
364 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
365 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
366 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
367 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
368 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
369 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
370 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
371 BR_PS_8 | BR_MS_UPMB | BR_V )
372 #endif /* CONFIG_CAN_DRIVER */
375 * Memory Periodic Timer Prescaler
377 * The Divider for PTA (refresh timer) configuration is based on an
378 * example SDRAM configuration (64 MBit, one bank). The adjustment to
379 * the number of chip selects (NCS) and the actually needed refresh
380 * rate is done by setting MPTPR.
382 * PTA is calculated from
383 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
385 * gclk CPU clock (not bus clock!)
386 * Trefresh Refresh cycle * 4 (four word bursts used)
388 * 4096 Rows from SDRAM example configuration
389 * 1000 factor s -> ms
390 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
391 * 4 Number of refresh cycles per period
392 * 64 Refresh cycle in ms per number of rows
393 * --------------------------------------------
394 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
396 * 50 MHz => 50.000.000 / Divider = 98
397 * 66 Mhz => 66.000.000 / Divider = 129
398 * 80 Mhz => 80.000.000 / Divider = 156
399 * 100 Mhz => 100.000.000 / Divider = 195
402 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
403 #define CONFIG_SYS_MAMR_PTA 98
406 * For 16 MBit, refresh rates could be 31.3 us
407 * (= 64 ms / 2K = 125 / quad bursts).
408 * For a simpler initialization, 15.6 us is used instead.
410 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
411 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
413 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
414 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
416 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
417 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
418 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
421 * MAMR settings for SDRAM
425 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
426 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
427 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
429 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
430 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
431 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
433 #define CONFIG_SCC1_ENET
434 #define CONFIG_FEC_ENET
435 #define CONFIG_ETHPRIME "SCC"
437 #define CONFIG_HWCONFIG 1
439 #endif /* __CONFIG_H */