2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37 #define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40 #undef CONFIG_8xx_CONS_SMC2
41 #undef CONFIG_8xx_CONS_NONE
43 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
45 #define CONFIG_BOOTCOUNT_LIMIT
47 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49 #define CONFIG_BOARD_TYPES 1 /* support board types */
51 #define CONFIG_PREBOOT "echo;" \
52 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
55 #undef CONFIG_BOOTARGS
57 #define CONFIG_EXTRA_ENV_SETTINGS \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
60 "nfsroot=$(serverip):$(rootpath)\0" \
61 "ramargs=setenv bootargs root=/dev/ram rw\0" \
62 "addip=setenv bootargs $(bootargs) " \
63 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
64 ":$(hostname):$(netdev):off panic=1\0" \
65 "flash_nfs=run nfsargs addip;" \
66 "bootm $(kernel_addr)\0" \
67 "flash_self=run ramargs addip;" \
68 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
69 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
70 "rootpath=/opt/eldk/ppc_8xx\0" \
71 "bootfile=/tftpboot/TQM860M/uImage\0" \
72 "kernel_addr=40080000\0" \
73 "ramdisk_addr=40180000\0" \
75 #define CONFIG_BOOTCOMMAND "run flash_self"
77 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
78 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
80 #undef CONFIG_WATCHDOG /* watchdog disabled */
82 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
84 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
86 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
88 #define CONFIG_MAC_PARTITION
89 #define CONFIG_DOS_PARTITION
91 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
93 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
100 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
101 #include <cmd_confdefs.h>
104 * Miscellaneous configurable options
106 #define CFG_LONGHELP /* undef to save memory */
107 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
110 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
112 #ifdef CFG_HUSH_PARSER
113 #define CFG_PROMPT_HUSH_PS2 "> "
116 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
117 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
119 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
121 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
122 #define CFG_MAXARGS 16 /* max number of command args */
123 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
125 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
126 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
128 #define CFG_LOAD_ADDR 0x100000 /* default load address */
130 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
132 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
135 * Low Level Configuration Settings
136 * (address mappings, register initial values, etc.)
137 * You should know what you are doing if you make changes here.
139 /*-----------------------------------------------------------------------
140 * Internal Memory Mapped Register
142 #define CFG_IMMR 0xFFF00000
144 /*-----------------------------------------------------------------------
145 * Definitions for initial stack pointer and data area (in DPRAM)
147 #define CFG_INIT_RAM_ADDR CFG_IMMR
148 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
149 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
150 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
151 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
153 /*-----------------------------------------------------------------------
154 * Start addresses for the final memory configuration
155 * (Set up by the startup code)
156 * Please note that CFG_SDRAM_BASE _must_ start at 0
158 #define CFG_SDRAM_BASE 0x00000000
159 #define CFG_FLASH_BASE 0x40000000
160 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
161 #define CFG_MONITOR_BASE CFG_FLASH_BASE
162 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
165 * For booting Linux, the board info and command line data
166 * have to be in the first 8 MB of memory, since this is
167 * the maximum mapped by the Linux kernel during initialization.
169 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
171 /*-----------------------------------------------------------------------
174 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
175 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
177 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
178 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
180 #define CFG_ENV_IS_IN_FLASH 1
181 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
182 #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
183 #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
185 /* Address and size of Redundant Environment Sector */
186 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
187 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
189 /*-----------------------------------------------------------------------
190 * Hardware Information Block
192 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
193 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
194 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
196 /*-----------------------------------------------------------------------
197 * Cache Configuration
199 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
200 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
201 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
204 /*-----------------------------------------------------------------------
205 * SYPCR - System Protection Control 11-9
206 * SYPCR can only be written once after reset!
207 *-----------------------------------------------------------------------
208 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
210 #if defined(CONFIG_WATCHDOG)
211 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
212 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
214 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
217 /*-----------------------------------------------------------------------
218 * SIUMCR - SIU Module Configuration 11-6
219 *-----------------------------------------------------------------------
220 * PCMCIA config., multi-function pin tri-state
222 #ifndef CONFIG_CAN_DRIVER
223 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
224 #else /* we must activate GPL5 in the SIUMCR for CAN */
225 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
226 #endif /* CONFIG_CAN_DRIVER */
228 /*-----------------------------------------------------------------------
229 * TBSCR - Time Base Status and Control 11-26
230 *-----------------------------------------------------------------------
231 * Clear Reference Interrupt Status, Timebase freezing enabled
233 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
235 /*-----------------------------------------------------------------------
236 * RTCSC - Real-Time Clock Status and Control Register 11-27
237 *-----------------------------------------------------------------------
239 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
241 /*-----------------------------------------------------------------------
242 * PISCR - Periodic Interrupt Status and Control 11-31
243 *-----------------------------------------------------------------------
244 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
246 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
248 /*-----------------------------------------------------------------------
249 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
250 *-----------------------------------------------------------------------
251 * Reset PLL lock status sticky bit, timer expired status bit and timer
252 * interrupt status bit
254 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
256 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
258 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
259 #else /* up to 66 MHz we use a 1:1 clock */
260 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
261 #endif /* CONFIG_80MHz */
263 /*-----------------------------------------------------------------------
264 * SCCR - System Clock and reset Control Register 15-27
265 *-----------------------------------------------------------------------
266 * Set clock output, timebase and RTC source and divider,
267 * power management and some other internal clocks
269 #define SCCR_MASK SCCR_EBDF11
270 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
271 #define CFG_SCCR (/* SCCR_TBS | */ \
272 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
273 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
275 #else /* up to 66 MHz we use a 1:1 clock */
276 #define CFG_SCCR (SCCR_TBS | \
277 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
278 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
280 #endif /* CONFIG_80MHz */
282 /*-----------------------------------------------------------------------
284 *-----------------------------------------------------------------------
287 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
288 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
289 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
290 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
291 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
292 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
293 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
294 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
296 /*-----------------------------------------------------------------------
297 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
298 *-----------------------------------------------------------------------
301 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
303 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
304 #undef CONFIG_IDE_LED /* LED for ide not supported */
305 #undef CONFIG_IDE_RESET /* reset for ide not supported */
307 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
308 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
310 #define CFG_ATA_IDE0_OFFSET 0x0000
312 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
314 /* Offset for data I/O */
315 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
317 /* Offset for normal register accesses */
318 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
320 /* Offset for alternate registers */
321 #define CFG_ATA_ALT_OFFSET 0x0100
323 /*-----------------------------------------------------------------------
325 *-----------------------------------------------------------------------
331 * Init Memory Controller:
333 * BR0/1 and OR0/1 (FLASH)
336 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
337 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
339 /* used to re-map FLASH both when starting from SRAM or FLASH:
340 * restrict access enough to keep SRAM working (if any)
341 * but not too much to meddle with FLASH accesses
343 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
344 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
349 #if defined(CONFIG_80MHz)
350 /* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
351 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
352 OR_SCY_3_CLK | OR_EHTR | OR_BI)
353 #elif defined(CONFIG_66MHz)
354 /* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
355 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
356 OR_SCY_3_CLK | OR_EHTR | OR_BI)
358 /* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
359 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
360 OR_SCY_2_CLK | OR_EHTR | OR_BI)
361 #endif /*CONFIG_??MHz */
363 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
364 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
365 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
367 #define CFG_OR1_REMAP CFG_OR0_REMAP
368 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
369 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
372 * BR2/3 and OR2/3 (SDRAM)
375 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
376 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
377 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
379 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
380 #define CFG_OR_TIMING_SDRAM 0x00000A00
382 #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
383 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
385 #ifndef CONFIG_CAN_DRIVER
386 #define CFG_OR3_PRELIM CFG_OR2_PRELIM
387 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
388 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
389 #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
390 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
391 #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
392 #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
393 BR_PS_8 | BR_MS_UPMB | BR_V )
394 #endif /* CONFIG_CAN_DRIVER */
397 * Memory Periodic Timer Prescaler
399 * The Divider for PTA (refresh timer) configuration is based on an
400 * example SDRAM configuration (64 MBit, one bank). The adjustment to
401 * the number of chip selects (NCS) and the actually needed refresh
402 * rate is done by setting MPTPR.
404 * PTA is calculated from
405 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
407 * gclk CPU clock (not bus clock!)
408 * Trefresh Refresh cycle * 4 (four word bursts used)
410 * 4096 Rows from SDRAM example configuration
411 * 1000 factor s -> ms
412 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
413 * 4 Number of refresh cycles per period
414 * 64 Refresh cycle in ms per number of rows
415 * --------------------------------------------
416 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
418 * 50 MHz => 50.000.000 / Divider = 98
419 * 66 Mhz => 66.000.000 / Divider = 129
420 * 80 Mhz => 80.000.000 / Divider = 156
422 #if defined(CONFIG_80MHz)
423 #define CFG_MAMR_PTA 156
424 #elif defined(CONFIG_66MHz)
425 #define CFG_MAMR_PTA 129
427 #define CFG_MAMR_PTA 98
428 #endif /*CONFIG_??MHz */
431 * For 16 MBit, refresh rates could be 31.3 us
432 * (= 64 ms / 2K = 125 / quad bursts).
433 * For a simpler initialization, 15.6 us is used instead.
435 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
436 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
438 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
439 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
441 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
442 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
443 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
446 * MAMR settings for SDRAM
450 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
451 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
452 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
454 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
455 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
456 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
460 * Internal Definitions
464 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
465 #define BOOTFLAG_WARM 0x02 /* Software reboot */
467 #define CONFIG_SCC1_ENET
468 #define CONFIG_FEC_ENET
469 #define CONFIG_ETHPRIME "SCC ETHERNET"
471 #endif /* __CONFIG_H */