include/configs/TQM834x.h

   1 /*
   2  * (C) Copyright 2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * TQM8349 board configuration file
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  */
  34 #define CONFIG_E300             1       /* E300 Family */
  35 #define CONFIG_MPC83XX          1       /* MPC83XX family */
  36 #define CONFIG_MPC834X          1       /* MPC834X specific */
  37 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  38 #define CONFIG_TQM834X          1       /* TQM834X board specific */
  39
  40 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */
  41 #define CONFIG_SYS_IMMR         0xff400000
  42
  43 /* System clock. Primary input clock when in PCI host mode */
  44 #define CONFIG_83XX_CLKIN       66666000        /* 66,666 MHz */
  45
  46 /*
  47  * Local Bus LCRR
  48  *    LCRR:  DLL bypass, Clock divider is 8
  49  *
  50  *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
  51  *
  52  * External Local Bus rate is
  53  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  54  */
  55 #define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_CLKDIV_8)
  56
  57 /* board pre init: do not call, nothing to do */
  58 #undef CONFIG_BOARD_EARLY_INIT_F
  59
  60 /* detect the number of flash banks */
  61 #define CONFIG_BOARD_EARLY_INIT_R
  62
  63 /*
  64  * DDR Setup
  65  */
  66 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  67 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  68 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  69 #define DDR_CASLAT_25                           /* CASLAT set to 2.5 */
  70 #undef CONFIG_DDR_ECC                           /* only for ECC DDR module */
  71 #undef CONFIG_SPD_EEPROM                        /* do not use SPD EEPROM for DDR setup */
  72
  73 #undef CONFIG_SYS_DRAM_TEST                             /* memory test, takes time */
  74 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  75 #define CONFIG_SYS_MEMTEST_END          0x00100000
  76
  77 /*
  78  * FLASH on the Local Bus
  79  */
  80 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
  81 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
  82 #undef CONFIG_SYS_FLASH_CHECKSUM
  83 #define CONFIG_SYS_FLASH_BASE           0x80000000      /* start of FLASH   */
  84 #define CONFIG_SYS_FLASH_SIZE           8               /* FLASH size in MB */
  85
  86 /* buffered writes in the AMD chip set is not supported yet */
  87 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  88
  89 /*
  90  * FLASH bank number detection
  91  */
  92
  93 /*
  94  * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
  95  * banks has to be determined at runtime and stored in a gloabl variable
  96  * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is only
  97  * used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array flash_info, and
  98  * should be made sufficiently large to accomodate the number of banks that
  99  * might actually be detected.  Since most (all?) Flash related functions use
 100  * CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on the board, it is
 101  * defined as tqm834x_num_flash_banks.
 102  */
 103 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       2
 104 #ifndef __ASSEMBLY__
 105 extern int tqm834x_num_flash_banks;
 106 #endif
 107 #define CONFIG_SYS_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
 108
 109 #define CONFIG_SYS_MAX_FLASH_SECT               512     /* max sectors per device */
 110
 111 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
 112 #define CONFIG_SYS_BR0_PRELIM           ((CONFIG_SYS_FLASH_BASE & BR_BA) | \
 113                                         BR_MS_GPCM | BR_PS_32 | BR_V)
 114
 115 /* FLASH timing (0x0000_0c54) */
 116 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
 117                                         OR_GPCM_SCY_5 | OR_GPCM_TRLX)
 118
 119 #define CONFIG_SYS_PRELIM_OR_AM 0xc0000000      /* OR addr mask: 1 GiB */
 120
 121 #define CONFIG_SYS_OR0_PRELIM           (CONFIG_SYS_PRELIM_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 122
 123 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000001D      /* 1 GiB window size (2^(size + 1)) */
 124
 125 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE   /* Window base at flash base */
 126
 127 /* disable remaining mappings */
 128 #define CONFIG_SYS_BR1_PRELIM           0x00000000
 129 #define CONFIG_SYS_OR1_PRELIM           0x00000000
 130 #define CONFIG_SYS_LBLAWBAR1_PRELIM     0x00000000
 131 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x00000000
 132
 133 #define CONFIG_SYS_BR2_PRELIM           0x00000000
 134 #define CONFIG_SYS_OR2_PRELIM           0x00000000
 135 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0x00000000
 136 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x00000000
 137
 138 #define CONFIG_SYS_BR3_PRELIM           0x00000000
 139 #define CONFIG_SYS_OR3_PRELIM           0x00000000
 140 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0x00000000
 141 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x00000000
 142
 143 #define CONFIG_SYS_BR4_PRELIM           0x00000000
 144 #define CONFIG_SYS_OR4_PRELIM           0x00000000
 145 #define CONFIG_SYS_LBLAWBAR4_PRELIM     0x00000000
 146 #define CONFIG_SYS_LBLAWAR4_PRELIM      0x00000000
 147
 148 #define CONFIG_SYS_BR5_PRELIM           0x00000000
 149 #define CONFIG_SYS_OR5_PRELIM           0x00000000
 150 #define CONFIG_SYS_LBLAWBAR5_PRELIM     0x00000000
 151 #define CONFIG_SYS_LBLAWAR5_PRELIM      0x00000000
 152
 153 #define CONFIG_SYS_BR6_PRELIM           0x00000000
 154 #define CONFIG_SYS_OR6_PRELIM           0x00000000
 155 #define CONFIG_SYS_LBLAWBAR6_PRELIM     0x00000000
 156 #define CONFIG_SYS_LBLAWAR6_PRELIM      0x00000000
 157
 158 #define CONFIG_SYS_BR7_PRELIM           0x00000000
 159 #define CONFIG_SYS_OR7_PRELIM           0x00000000
 160 #define CONFIG_SYS_LBLAWBAR7_PRELIM     0x00000000
 161 #define CONFIG_SYS_LBLAWAR7_PRELIM      0x00000000
 162
 163 /*
 164  * Monitor config
 165  */
 166 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 167
 168 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 169 #define CONFIG_SYS_RAMBOOT
 170 #else
 171 #undef  CONFIG_SYS_RAMBOOT
 172 #endif
 173
 174 #define CONFIG_L1_INIT_RAM
 175 #define CONFIG_SYS_INIT_RAM_LOCK        1
 176 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000      /* Initial RAM address */
 177 #define CONFIG_SYS_INIT_RAM_END 0x1000          /* End of used area in RAM*/
 178
 179 #define CONFIG_SYS_GBL_DATA_SIZE        0x100           /* num bytes initial data */
 180 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 181 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 182
 183 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 184 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024) /* Reserve 256 kB for malloc */
 185
 186 /*
 187  * Serial Port
 188  */
 189 #define CONFIG_CONS_INDEX       1
 190 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 191 #define CONFIG_SYS_NS16550
 192 #define CONFIG_SYS_NS16550_SERIAL
 193 #define CONFIG_SYS_NS16550_REG_SIZE     1
 194 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 195
 196 #define CONFIG_SYS_BAUDRATE_TABLE  \
 197         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 198
 199 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 200 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 201
 202 /*
 203  * I2C
 204  */
 205 #define CONFIG_HARD_I2C                         /* I2C with hardware support    */
 206 #undef CONFIG_SOFT_I2C                          /* I2C bit-banged               */
 207 #define CONFIG_FSL_I2C
 208 #define CONFIG_SYS_I2C_SPEED                    400000  /* I2C speed: 400KHz            */
 209 #define CONFIG_SYS_I2C_SLAVE                    0x7F    /* slave address                */
 210 #define CONFIG_SYS_I2C_OFFSET                   0x3000
 211
 212 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
 213 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x                     */
 214 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16 bit                       */
 215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32 bytes per write           */
 216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12      /* 10ms +/- 20%                 */
 217 #define CONFIG_SYS_I2C_MULTI_EEPROMS            1       /* more than one eeprom         */
 218
 219 /* I2C RTC */
 220 #define CONFIG_RTC_DS1337                       /* use ds1337 rtc via i2c       */
 221 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68              */
 222
 223 /* I2C SYSMON (LM75) */
 224 #define CONFIG_DTT_LM75                 1       /* ON Semi's LM75               */
 225 #define CONFIG_DTT_SENSORS              {0}     /* Sensor addresses             */
 226 #define CONFIG_SYS_DTT_MAX_TEMP         70
 227 #define CONFIG_SYS_DTT_LOW_TEMP         -30
 228 #define CONFIG_SYS_DTT_HYSTERESIS               3
 229
 230 /*
 231  * TSEC
 232  */
 233 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
 234 #define CONFIG_MII
 235
 236 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 237 #define CONFIG_SYS_TSEC1                (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 238 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 239 #define CONFIG_SYS_TSEC2                (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 240
 241 #if defined(CONFIG_TSEC_ENET)
 242
 243 #ifndef CONFIG_NET_MULTI
 244 #define CONFIG_NET_MULTI
 245 #endif
 246
 247 #define CONFIG_TSEC1            1
 248 #define CONFIG_TSEC1_NAME       "TSEC0"
 249 #define CONFIG_TSEC2            1
 250 #define CONFIG_TSEC2_NAME       "TSEC1"
 251 #define TSEC1_PHY_ADDR                  2
 252 #define TSEC2_PHY_ADDR                  1
 253 #define TSEC1_PHYIDX                    0
 254 #define TSEC2_PHYIDX                    0
 255 #define TSEC1_FLAGS             TSEC_GIGABIT
 256 #define TSEC2_FLAGS             TSEC_GIGABIT
 257
 258 /* Options are: TSEC[0-1] */
 259 #define CONFIG_ETHPRIME                 "TSEC0"
 260
 261 #endif  /* CONFIG_TSEC_ENET */
 262
 263 /*
 264  * General PCI
 265  * Addresses are mapped 1-1.
 266  */
 267 #define CONFIG_PCI
 268
 269 #if defined(CONFIG_PCI)
 270
 271 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 272 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 273
 274 /* PCI1 host bridge */
 275 #define CONFIG_SYS_PCI1_MEM_BASE       0xc0000000
 276 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
 277 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
 278 #define CONFIG_SYS_PCI1_IO_BASE        0xe2000000
 279 #define CONFIG_SYS_PCI1_IO_PHYS        CONFIG_SYS_PCI1_IO_BASE
 280 #define CONFIG_SYS_PCI1_IO_SIZE        0x1000000       /* 16M */
 281
 282 #undef CONFIG_EEPRO100
 283 #define CONFIG_EEPRO100
 284 #undef CONFIG_TULIP
 285
 286 #if !defined(CONFIG_PCI_PNP)
 287         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
 288         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_MEM_BASE
 289         #define PCI_IDSEL_NUMBER        0x1c    /* slot0 (IDSEL) = 28 */
 290 #endif
 291
 292 #define CONFIG_SYS_PCI_SUBSYS_VENDORID          0x1957  /* Freescale */
 293
 294 #endif  /* CONFIG_PCI */
 295
 296 /*
 297  * Environment
 298  */
 299 #define CONFIG_ENV_OVERWRITE
 300
 301 #ifndef CONFIG_SYS_RAMBOOT
 302         #define CONFIG_ENV_IS_IN_FLASH  1
 303         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 304         #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 305         #define CONFIG_ENV_SIZE         0x2000
 306 #else
 307         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 308         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 309         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 310         #define CONFIG_ENV_SIZE         0x2000
 311 #endif
 312
 313 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 314 #define CONFIG_SYS_LOADS_BAUD_CHANGE            1       /* allow baudrate change */
 315
 316 /*
 317  * BOOTP options
 318  */
 319 #define CONFIG_BOOTP_BOOTFILESIZE
 320 #define CONFIG_BOOTP_BOOTPATH
 321 #define CONFIG_BOOTP_GATEWAY
 322 #define CONFIG_BOOTP_HOSTNAME
 323
 324
 325 /*
 326  * Command line configuration.
 327  */
 328 #include <config_cmd_default.h>
 329
 330 #define CONFIG_CMD_DATE
 331 #define CONFIG_CMD_DTT
 332 #define CONFIG_CMD_EEPROM
 333 #define CONFIG_CMD_I2C
 334 #define CONFIG_CMD_JFFS2
 335 #define CONFIG_CMD_MII
 336 #define CONFIG_CMD_PING
 337 #define CONFIG_CMD_DHCP
 338
 339 #if defined(CONFIG_PCI)
 340     #define CONFIG_CMD_PCI
 341 #endif
 342
 343 #if defined(CONFIG_SYS_RAMBOOT)
 344     #undef CONFIG_CMD_ENV
 345     #undef CONFIG_CMD_LOADS
 346 #endif
 347
 348 /*
 349  * Miscellaneous configurable options
 350  */
 351 #define CONFIG_SYS_LONGHELP                             /* undef to save memory */
 352 #define CONFIG_SYS_LOAD_ADDR            0x2000000       /* default load address */
 353 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt */
 354
 355 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 356 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 357 #ifdef  CONFIG_SYS_HUSH_PARSER
 358 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 359 #endif
 360
 361 #if defined(CONFIG_CMD_KGDB)
 362         #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 363 #else
 364         #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 365 #endif
 366
 367 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 368 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 369 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 370 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1ms ticks */
 371
 372 #undef CONFIG_WATCHDOG                          /* watchdog disabled */
 373
 374 /*
 375  * For booting Linux, the board info and command line data
 376  * have to be in the first 8 MB of memory, since this is
 377  * the maximum mapped by the Linux kernel during initialization.
 378  */
 379 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 380
 381 #define CONFIG_SYS_HRCW_LOW (\
 382         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 383         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 384         HRCWL_CSB_TO_CLKIN_4X1 |\
 385         HRCWL_VCO_1X2 |\
 386         HRCWL_CORE_TO_CSB_2X1)
 387
 388 #if defined(PCI_64BIT)
 389 #define CONFIG_SYS_HRCW_HIGH (\
 390         HRCWH_PCI_HOST |\
 391         HRCWH_64_BIT_PCI |\
 392         HRCWH_PCI1_ARBITER_ENABLE |\
 393         HRCWH_PCI2_ARBITER_DISABLE |\
 394         HRCWH_CORE_ENABLE |\
 395         HRCWH_FROM_0X00000100 |\
 396         HRCWH_BOOTSEQ_DISABLE |\
 397         HRCWH_SW_WATCHDOG_DISABLE |\
 398         HRCWH_ROM_LOC_LOCAL_16BIT |\
 399         HRCWH_TSEC1M_IN_GMII |\
 400         HRCWH_TSEC2M_IN_GMII )
 401 #else
 402 #define CONFIG_SYS_HRCW_HIGH (\
 403         HRCWH_PCI_HOST |\
 404         HRCWH_32_BIT_PCI |\
 405         HRCWH_PCI1_ARBITER_ENABLE |\
 406         HRCWH_PCI2_ARBITER_DISABLE |\
 407         HRCWH_CORE_ENABLE |\
 408         HRCWH_FROM_0X00000100 |\
 409         HRCWH_BOOTSEQ_DISABLE |\
 410         HRCWH_SW_WATCHDOG_DISABLE |\
 411         HRCWH_ROM_LOC_LOCAL_16BIT |\
 412         HRCWH_TSEC1M_IN_GMII |\
 413         HRCWH_TSEC2M_IN_GMII )
 414 #endif
 415
 416 /* System IO Config */
 417 #define CONFIG_SYS_SICRH        SICRH_TSOBI1
 418 #define CONFIG_SYS_SICRL        SICRL_LDP_A
 419
 420 /* i-cache and d-cache disabled */
 421 #define CONFIG_SYS_HID0_INIT    0x000000000
 422 #define CONFIG_SYS_HID0_FINAL   CONFIG_SYS_HID0_INIT
 423 #define CONFIG_SYS_HID2 HID2_HBE
 424
 425 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 426
 427 /* DDR 0 - 512M */
 428 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 429 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 430 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
 431 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 432
 433 /* stack in DCACHE @ 512M (no backing mem) */
 434 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 435 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 436
 437 /* PCI */
 438 #ifdef CONFIG_PCI
 439 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 440 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 441 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
 442 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 443 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 444 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
 445 #else
 446 #define CONFIG_SYS_IBAT3L       (0)
 447 #define CONFIG_SYS_IBAT3U       (0)
 448 #define CONFIG_SYS_IBAT4L       (0)
 449 #define CONFIG_SYS_IBAT4U       (0)
 450 #define CONFIG_SYS_IBAT5L       (0)
 451 #define CONFIG_SYS_IBAT5U       (0)
 452 #endif
 453
 454 /* IMMRBAR */
 455 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 456 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
 457
 458 /* FLASH */
 459 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 460 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 461
 462 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 463 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 464 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 465 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 466 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 467 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 468 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 469 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 470 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 471 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 472 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 473 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 474 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 475 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 476 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 477 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 478
 479 /*
 480  * Internal Definitions
 481  *
 482  * Boot Flags
 483  */
 484 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 485 #define BOOTFLAG_WARM           0x02    /* Software reboot */
 486
 487 #if defined(CONFIG_CMD_KGDB)
 488 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 489 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 490 #endif
 491
 492 /*
 493  * Environment Configuration
 494  */
 495
 496 #define CONFIG_LOADADDR         400000  /* default location for tftp and bootm */
 497
 498 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 499 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 500
 501 #define CONFIG_BAUDRATE         115200
 502
 503 #define CONFIG_PREBOOT  "echo;" \
 504         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 505         "echo"
 506
 507 #undef  CONFIG_BOOTARGS
 508
 509 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 510         "netdev=eth0\0"                                                 \
 511         "hostname=tqm834x\0"                                            \
 512         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 513                 "nfsroot=${serverip}:${rootpath}\0"                     \
 514         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 515         "addip=setenv bootargs ${bootargs} "                            \
 516                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 517                 ":${hostname}:${netdev}:off panic=1\0"                  \
 518         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 519         "flash_nfs=run nfsargs addip addtty;"                           \
 520                 "bootm ${kernel_addr}\0"                                \
 521         "flash_self=run ramargs addip addtty;"                          \
 522                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 523         "net_nfs=tftp 400000 ${bootfile};run nfsargs addip addtty;"     \
 524                 "bootm\0"                                               \
 525         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 526         "bootfile=/tftpboot/tqm834x/uImage\0"                           \
 527         "kernel_addr=80060000\0"                                        \
 528         "ramdisk_addr=80160000\0"                                       \
 529         "load=tftp 100000 /tftpboot/tqm834x/u-boot.bin\0"               \
 530         "update=protect off 80000000 8003ffff; "                        \
 531                 "era 80000000 8003ffff; cp.b 100000 80000000 40000\0"   \
 532         "upd=run load update\0"                                         \
 533         ""
 534
 535 #define CONFIG_BOOTCOMMAND      "run flash_self"
 536
 537 /*
 538  * JFFS2 partitions
 539  */
 540 /* mtdparts command line support */
 541 #define CONFIG_JFFS2_CMDLINE
 542 #define MTDIDS_DEFAULT          "nor0=TQM834x-0"
 543
 544 /* default mtd partition table */
 545 #define MTDPARTS_DEFAULT        "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
 546                                                 "1m(kernel),2m(initrd),"\
 547                                                 "-(user);"\
 548
 549 #endif  /* __CONFIG_H */