3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * TQM8349 board configuration file
32 * High Level Configuration Options
34 #define CONFIG_E300 1 /* E300 Family */
35 #define CONFIG_MPC83XX 1 /* MPC83XX family */
36 #define CONFIG_MPC834X 1 /* MPC834X specific */
37 #define CONFIG_MPC8349 1 /* MPC8349 specific */
38 #define CONFIG_TQM834X 1 /* TQM834X board specific */
40 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */
41 #define CONFIG_SYS_IMMR 0xff400000
43 /* System clock. Primary input clock when in PCI host mode */
44 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
48 * LCRR: DLL bypass, Clock divider is 8
50 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
52 * External Local Bus rate is
53 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
55 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
57 /* board pre init: do not call, nothing to do */
58 #undef CONFIG_BOARD_EARLY_INIT_F
60 /* detect the number of flash banks */
61 #define CONFIG_BOARD_EARLY_INIT_R
66 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
67 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
68 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
69 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */
70 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
71 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
73 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
74 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
75 #define CONFIG_SYS_MEMTEST_END 0x00100000
78 * FLASH on the Local Bus
80 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
81 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
82 #undef CONFIG_SYS_FLASH_CHECKSUM
83 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
84 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
86 /* buffered writes in the AMD chip set is not supported yet */
87 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
90 * FLASH bank number detection
94 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
95 * banks has to be determined at runtime and stored in a gloabl variable
96 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is only
97 * used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array flash_info, and
98 * should be made sufficiently large to accomodate the number of banks that
99 * might actually be detected. Since most (all?) Flash related functions use
100 * CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on the board, it is
101 * defined as tqm834x_num_flash_banks.
103 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
105 extern int tqm834x_num_flash_banks;
107 #define CONFIG_SYS_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
109 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
111 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
112 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) | \
113 BR_MS_GPCM | BR_PS_32 | BR_V)
115 /* FLASH timing (0x0000_0c54) */
116 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
117 OR_GPCM_SCY_5 | OR_GPCM_TRLX)
119 #define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
121 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
123 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
125 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
127 /* disable remaining mappings */
128 #define CONFIG_SYS_BR1_PRELIM 0x00000000
129 #define CONFIG_SYS_OR1_PRELIM 0x00000000
130 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
131 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
133 #define CONFIG_SYS_BR2_PRELIM 0x00000000
134 #define CONFIG_SYS_OR2_PRELIM 0x00000000
135 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
136 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
138 #define CONFIG_SYS_BR3_PRELIM 0x00000000
139 #define CONFIG_SYS_OR3_PRELIM 0x00000000
140 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
141 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
143 #define CONFIG_SYS_BR4_PRELIM 0x00000000
144 #define CONFIG_SYS_OR4_PRELIM 0x00000000
145 #define CONFIG_SYS_LBLAWBAR4_PRELIM 0x00000000
146 #define CONFIG_SYS_LBLAWAR4_PRELIM 0x00000000
148 #define CONFIG_SYS_BR5_PRELIM 0x00000000
149 #define CONFIG_SYS_OR5_PRELIM 0x00000000
150 #define CONFIG_SYS_LBLAWBAR5_PRELIM 0x00000000
151 #define CONFIG_SYS_LBLAWAR5_PRELIM 0x00000000
153 #define CONFIG_SYS_BR6_PRELIM 0x00000000
154 #define CONFIG_SYS_OR6_PRELIM 0x00000000
155 #define CONFIG_SYS_LBLAWBAR6_PRELIM 0x00000000
156 #define CONFIG_SYS_LBLAWAR6_PRELIM 0x00000000
158 #define CONFIG_SYS_BR7_PRELIM 0x00000000
159 #define CONFIG_SYS_OR7_PRELIM 0x00000000
160 #define CONFIG_SYS_LBLAWBAR7_PRELIM 0x00000000
161 #define CONFIG_SYS_LBLAWAR7_PRELIM 0x00000000
166 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
168 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
169 #define CONFIG_SYS_RAMBOOT
171 #undef CONFIG_SYS_RAMBOOT
174 #define CONFIG_SYS_INIT_RAM_LOCK 1
175 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
176 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
178 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
179 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
180 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
182 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
183 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */
188 #define CONFIG_CONS_INDEX 1
189 #undef CONFIG_SERIAL_SOFTWARE_FIFO
190 #define CONFIG_SYS_NS16550
191 #define CONFIG_SYS_NS16550_SERIAL
192 #define CONFIG_SYS_NS16550_REG_SIZE 1
193 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
195 #define CONFIG_SYS_BAUDRATE_TABLE \
196 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
198 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
199 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
204 #define CONFIG_HARD_I2C /* I2C with hardware support */
205 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
206 #define CONFIG_FSL_I2C
207 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
208 #define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
209 #define CONFIG_SYS_I2C_OFFSET 0x3000
211 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
212 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
213 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
216 #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
219 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
220 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
222 /* I2C SYSMON (LM75) */
223 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
224 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
225 #define CONFIG_SYS_DTT_MAX_TEMP 70
226 #define CONFIG_SYS_DTT_LOW_TEMP -30
227 #define CONFIG_SYS_DTT_HYSTERESIS 3
232 #define CONFIG_TSEC_ENET /* tsec ethernet support */
235 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
236 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
237 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
238 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
240 #if defined(CONFIG_TSEC_ENET)
242 #ifndef CONFIG_NET_MULTI
243 #define CONFIG_NET_MULTI
246 #define CONFIG_TSEC1 1
247 #define CONFIG_TSEC1_NAME "TSEC0"
248 #define CONFIG_TSEC2 1
249 #define CONFIG_TSEC2_NAME "TSEC1"
250 #define TSEC1_PHY_ADDR 2
251 #define TSEC2_PHY_ADDR 1
252 #define TSEC1_PHYIDX 0
253 #define TSEC2_PHYIDX 0
254 #define TSEC1_FLAGS TSEC_GIGABIT
255 #define TSEC2_FLAGS TSEC_GIGABIT
257 /* Options are: TSEC[0-1] */
258 #define CONFIG_ETHPRIME "TSEC0"
260 #endif /* CONFIG_TSEC_ENET */
264 * Addresses are mapped 1-1.
268 #if defined(CONFIG_PCI)
270 #define CONFIG_PCI_PNP /* do pci plug-and-play */
271 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
273 /* PCI1 host bridge */
274 #define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000
275 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
276 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
277 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
278 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
279 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
281 #undef CONFIG_EEPRO100
282 #define CONFIG_EEPRO100
285 #if !defined(CONFIG_PCI_PNP)
286 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
287 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
288 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
291 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
293 #endif /* CONFIG_PCI */
298 #define CONFIG_ENV_OVERWRITE
300 #ifndef CONFIG_SYS_RAMBOOT
301 #define CONFIG_ENV_IS_IN_FLASH 1
302 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
303 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
304 #define CONFIG_ENV_SIZE 0x2000
306 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
307 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
308 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
309 #define CONFIG_ENV_SIZE 0x2000
312 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
313 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
318 #define CONFIG_BOOTP_BOOTFILESIZE
319 #define CONFIG_BOOTP_BOOTPATH
320 #define CONFIG_BOOTP_GATEWAY
321 #define CONFIG_BOOTP_HOSTNAME
325 * Command line configuration.
327 #include <config_cmd_default.h>
329 #define CONFIG_CMD_DATE
330 #define CONFIG_CMD_DTT
331 #define CONFIG_CMD_EEPROM
332 #define CONFIG_CMD_I2C
333 #define CONFIG_CMD_JFFS2
334 #define CONFIG_CMD_MII
335 #define CONFIG_CMD_PING
336 #define CONFIG_CMD_DHCP
338 #if defined(CONFIG_PCI)
339 #define CONFIG_CMD_PCI
342 #if defined(CONFIG_SYS_RAMBOOT)
343 #undef CONFIG_CMD_SAVEENV
344 #undef CONFIG_CMD_LOADS
348 * Miscellaneous configurable options
350 #define CONFIG_SYS_LONGHELP /* undef to save memory */
351 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
352 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
354 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
355 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
356 #ifdef CONFIG_SYS_HUSH_PARSER
357 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
360 #if defined(CONFIG_CMD_KGDB)
361 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
363 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
366 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
367 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
368 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
369 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
371 #undef CONFIG_WATCHDOG /* watchdog disabled */
374 * For booting Linux, the board info and command line data
375 * have to be in the first 8 MB of memory, since this is
376 * the maximum mapped by the Linux kernel during initialization.
378 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
380 #define CONFIG_SYS_HRCW_LOW (\
381 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
382 HRCWL_DDR_TO_SCB_CLK_1X1 |\
383 HRCWL_CSB_TO_CLKIN_4X1 |\
385 HRCWL_CORE_TO_CSB_2X1)
387 #if defined(PCI_64BIT)
388 #define CONFIG_SYS_HRCW_HIGH (\
391 HRCWH_PCI1_ARBITER_ENABLE |\
392 HRCWH_PCI2_ARBITER_DISABLE |\
394 HRCWH_FROM_0X00000100 |\
395 HRCWH_BOOTSEQ_DISABLE |\
396 HRCWH_SW_WATCHDOG_DISABLE |\
397 HRCWH_ROM_LOC_LOCAL_16BIT |\
398 HRCWH_TSEC1M_IN_GMII |\
399 HRCWH_TSEC2M_IN_GMII )
401 #define CONFIG_SYS_HRCW_HIGH (\
404 HRCWH_PCI1_ARBITER_ENABLE |\
405 HRCWH_PCI2_ARBITER_DISABLE |\
407 HRCWH_FROM_0X00000100 |\
408 HRCWH_BOOTSEQ_DISABLE |\
409 HRCWH_SW_WATCHDOG_DISABLE |\
410 HRCWH_ROM_LOC_LOCAL_16BIT |\
411 HRCWH_TSEC1M_IN_GMII |\
412 HRCWH_TSEC2M_IN_GMII )
415 /* System IO Config */
416 #define CONFIG_SYS_SICRH SICRH_TSOBI1
417 #define CONFIG_SYS_SICRL SICRL_LDP_A
419 /* i-cache and d-cache disabled */
420 #define CONFIG_SYS_HID0_INIT 0x000000000
421 #define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
422 #define CONFIG_SYS_HID2 HID2_HBE
424 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
427 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
428 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
429 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
430 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
432 /* stack in DCACHE @ 512M (no backing mem) */
433 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
434 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
438 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
439 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
440 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
441 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
442 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
443 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
445 #define CONFIG_SYS_IBAT3L (0)
446 #define CONFIG_SYS_IBAT3U (0)
447 #define CONFIG_SYS_IBAT4L (0)
448 #define CONFIG_SYS_IBAT4U (0)
449 #define CONFIG_SYS_IBAT5L (0)
450 #define CONFIG_SYS_IBAT5U (0)
454 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
455 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
458 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
459 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
461 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
462 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
463 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
464 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
465 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
466 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
467 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
468 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
469 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
470 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
471 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
472 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
473 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
474 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
475 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
476 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
479 * Internal Definitions
483 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
484 #define BOOTFLAG_WARM 0x02 /* Software reboot */
486 #if defined(CONFIG_CMD_KGDB)
487 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
488 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
492 * Environment Configuration
495 #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
497 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
498 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
500 #define CONFIG_BAUDRATE 115200
502 #define CONFIG_PREBOOT "echo;" \
503 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
506 #undef CONFIG_BOOTARGS
508 #define CONFIG_EXTRA_ENV_SETTINGS \
510 "hostname=tqm834x\0" \
511 "nfsargs=setenv bootargs root=/dev/nfs rw " \
512 "nfsroot=${serverip}:${rootpath}\0" \
513 "ramargs=setenv bootargs root=/dev/ram rw\0" \
514 "addip=setenv bootargs ${bootargs} " \
515 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
516 ":${hostname}:${netdev}:off panic=1\0" \
517 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
518 "flash_nfs=run nfsargs addip addtty;" \
519 "bootm ${kernel_addr}\0" \
520 "flash_self=run ramargs addip addtty;" \
521 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
522 "net_nfs=tftp 400000 ${bootfile};run nfsargs addip addtty;" \
524 "rootpath=/opt/eldk/ppc_6xx\0" \
525 "bootfile=/tftpboot/tqm834x/uImage\0" \
526 "kernel_addr=80060000\0" \
527 "ramdisk_addr=80160000\0" \
528 "load=tftp 100000 /tftpboot/tqm834x/u-boot.bin\0" \
529 "update=protect off 80000000 8003ffff; " \
530 "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \
531 "upd=run load update\0" \
534 #define CONFIG_BOOTCOMMAND "run flash_self"
539 /* mtdparts command line support */
540 #define CONFIG_CMD_MTDPARTS
541 #define MTDIDS_DEFAULT "nor0=TQM834x-0"
543 /* default mtd partition table */
544 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
545 "1m(kernel),2m(initrd),"\
548 #endif /* __CONFIG_H */