1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * TQM8349 board configuration file
15 * High Level Configuration Options
17 #define CONFIG_E300 1 /* E300 Family */
21 * LCRR: DLL bypass, Clock divider is 8
23 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
25 * External Local Bus rate is
26 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
28 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
29 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
31 /* board pre init: do not call, nothing to do */
33 /* detect the number of flash banks */
38 /* DDR is system memory*/
39 #define CONFIG_SYS_DDR_BASE 0x00000000
40 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
41 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
42 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */
43 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
44 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
46 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
47 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
48 #define CONFIG_SYS_MEMTEST_END 0x00100000
51 * FLASH on the Local Bus
53 #undef CONFIG_SYS_FLASH_CHECKSUM
54 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
55 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
56 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
59 * FLASH bank number detection
63 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
64 * Flash banks has to be determined at runtime and stored in a gloabl variable
65 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
66 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
67 * flash_info, and should be made sufficiently large to accomodate the number
68 * of banks that might actually be detected. Since most (all?) Flash related
69 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
70 * the board, it is defined as tqm834x_num_flash_banks.
72 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
74 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
77 /* disable remaining mappings */
78 #define CONFIG_SYS_BR1_PRELIM 0x00000000
79 #define CONFIG_SYS_OR1_PRELIM 0x00000000
81 #define CONFIG_SYS_BR2_PRELIM 0x00000000
82 #define CONFIG_SYS_OR2_PRELIM 0x00000000
84 #define CONFIG_SYS_BR3_PRELIM 0x00000000
85 #define CONFIG_SYS_OR3_PRELIM 0x00000000
90 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
92 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
93 # define CONFIG_SYS_RAMBOOT
95 # undef CONFIG_SYS_RAMBOOT
98 #define CONFIG_SYS_INIT_RAM_LOCK 1
99 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
100 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
102 #define CONFIG_SYS_GBL_DATA_OFFSET \
103 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
104 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
106 /* Reserve 384 kB = 3 sect. for Mon */
107 #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
108 /* Reserve 512 kB for malloc */
109 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
114 #define CONFIG_SYS_NS16550_SERIAL
115 #define CONFIG_SYS_NS16550_REG_SIZE 1
116 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
118 #define CONFIG_SYS_BAUDRATE_TABLE \
119 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
121 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
122 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
127 #define CONFIG_SYS_I2C
128 #define CONFIG_SYS_I2C_FSL
129 #define CONFIG_SYS_FSL_I2C_SPEED 400000
130 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
131 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
133 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
134 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
135 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
136 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
137 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
140 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
141 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
147 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
148 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
149 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
150 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
152 #if defined(CONFIG_TSEC_ENET)
154 #define CONFIG_TSEC1 1
155 #define CONFIG_TSEC1_NAME "TSEC0"
156 #define CONFIG_TSEC2 1
157 #define CONFIG_TSEC2_NAME "TSEC1"
158 #define TSEC1_PHY_ADDR 2
159 #define TSEC2_PHY_ADDR 1
160 #define TSEC1_PHYIDX 0
161 #define TSEC2_PHYIDX 0
162 #define TSEC1_FLAGS TSEC_GIGABIT
163 #define TSEC2_FLAGS TSEC_GIGABIT
165 /* Options are: TSEC[0-1] */
166 #define CONFIG_ETHPRIME "TSEC0"
168 #endif /* CONFIG_TSEC_ENET */
170 #if defined(CONFIG_PCI)
172 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
174 /* PCI1 host bridge */
175 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
176 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
177 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
178 #define CONFIG_SYS_PCI1_MMIO_BASE \
179 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
180 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
181 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
182 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
183 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
184 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
186 #undef CONFIG_EEPRO100
187 #define CONFIG_EEPRO100
190 #if !defined(CONFIG_PCI_PNP)
191 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
192 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
193 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
196 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
198 #endif /* CONFIG_PCI */
203 #define CONFIG_ENV_ADDR \
204 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
205 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
206 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
207 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
208 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
210 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
211 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
216 #define CONFIG_BOOTP_BOOTFILESIZE
219 * Miscellaneous configurable options
221 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
223 #undef CONFIG_WATCHDOG /* watchdog disabled */
226 * For booting Linux, the board info and command line data
227 * have to be in the first 256 MB of memory, since this is
228 * the maximum mapped by the Linux kernel during initialization.
230 /* Initial Memory map for Linux */
231 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
233 /* System IO Config */
234 #define CONFIG_SYS_SICRH 0
235 #define CONFIG_SYS_SICRL SICRL_LDP_A
239 #define CONFIG_PCI_INDIRECT_BRIDGE
242 #if defined(CONFIG_CMD_KGDB)
243 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
247 * Environment Configuration
250 /* default location for tftp and bootm */
251 #define CONFIG_LOADADDR 400000
253 #define CONFIG_PREBOOT "echo;" \
254 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
257 #define CONFIG_EXTRA_ENV_SETTINGS \
259 "hostname=tqm834x\0" \
260 "nfsargs=setenv bootargs root=/dev/nfs rw " \
261 "nfsroot=${serverip}:${rootpath}\0" \
262 "ramargs=setenv bootargs root=/dev/ram rw\0" \
263 "addip=setenv bootargs ${bootargs} " \
264 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
265 ":${hostname}:${netdev}:off panic=1\0" \
266 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
267 "flash_nfs_old=run nfsargs addip addcons;" \
268 "bootm ${kernel_addr}\0" \
269 "flash_nfs=run nfsargs addip addcons;" \
270 "bootm ${kernel_addr} - ${fdt_addr}\0" \
271 "flash_self_old=run ramargs addip addcons;" \
272 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
273 "flash_self=run ramargs addip addcons;" \
274 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
275 "net_nfs_old=tftp 400000 ${bootfile};" \
276 "run nfsargs addip addcons;bootm\0" \
277 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
278 "tftp ${fdt_addr_r} ${fdt_file}; " \
279 "run nfsargs addip addcons; " \
280 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
281 "rootpath=/opt/eldk/ppc_6xx\0" \
282 "bootfile=tqm834x/uImage\0" \
283 "fdtfile=tqm834x/tqm834x.dtb\0" \
284 "kernel_addr_r=400000\0" \
285 "fdt_addr_r=600000\0" \
286 "ramdisk_addr_r=800000\0" \
287 "kernel_addr=800C0000\0" \
288 "fdt_addr=800A0000\0" \
289 "ramdisk_addr=80300000\0" \
290 "u-boot=tqm834x/u-boot.bin\0" \
291 "load=tftp 200000 ${u-boot}\0" \
292 "update=protect off 80000000 +${filesize};" \
293 "era 80000000 +${filesize};" \
294 "cp.b 200000 80000000 ${filesize}\0" \
295 "upd=run load update\0" \
298 #define CONFIG_BOOTCOMMAND "run flash_self"
303 /* mtdparts command line support */
305 /* default mtd partition table */
306 #endif /* __CONFIG_H */