c54de6507633d53a43ee3c1047b26fde87b4b823
[platform/kernel/u-boot.git] / include / configs / TQM834x.h
1 /*
2  * (C) Copyright 2005
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /*
9  * TQM8349 board configuration file
10  */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 /*
16  * High Level Configuration Options
17  */
18 #define CONFIG_E300             1       /* E300 Family */
19 #define CONFIG_MPC834x          1       /* MPC834x specific */
20 #define CONFIG_MPC8349          1       /* MPC8349 specific */
21 #define CONFIG_TQM834X          1       /* TQM834X board specific */
22
23 #define CONFIG_SYS_TEXT_BASE    0x80000000
24
25 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
26 #define CONFIG_SYS_IMMR         0xff400000
27
28 /* System clock. Primary input clock when in PCI host mode */
29 #define CONFIG_83XX_CLKIN       66666000        /* 66,666 MHz */
30
31 /*
32  * Local Bus LCRR
33  *    LCRR:  DLL bypass, Clock divider is 8
34  *
35  *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
36  *
37  * External Local Bus rate is
38  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
39  */
40 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
41 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
42
43 /* board pre init: do not call, nothing to do */
44
45 /* detect the number of flash banks */
46 #define CONFIG_BOARD_EARLY_INIT_R
47
48 /*
49  * DDR Setup
50  */
51                                 /* DDR is system memory*/
52 #define CONFIG_SYS_DDR_BASE     0x00000000
53 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
54 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
55 #define DDR_CASLAT_25           /* CASLAT set to 2.5 */
56 #undef CONFIG_DDR_ECC           /* only for ECC DDR module */
57 #undef CONFIG_SPD_EEPROM        /* do not use SPD EEPROM for DDR setup */
58
59 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
60 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
61 #define CONFIG_SYS_MEMTEST_END          0x00100000
62
63 /*
64  * FLASH on the Local Bus
65  */
66 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
67 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
68 #undef CONFIG_SYS_FLASH_CHECKSUM
69 #define CONFIG_SYS_FLASH_BASE           0x80000000      /* start of FLASH   */
70 #define CONFIG_SYS_FLASH_SIZE           8               /* FLASH size in MB */
71 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sectors */
72 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
73
74 /*
75  * FLASH bank number detection
76  */
77
78 /*
79  * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
80  * Flash banks has to be determined at runtime and stored in a gloabl variable
81  * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
82  * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
83  * flash_info, and should be made sufficiently large to accomodate the number
84  * of banks that might actually be detected.  Since most (all?) Flash related
85  * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
86  * the board, it is defined as tqm834x_num_flash_banks.
87  */
88 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       2
89
90 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
91
92 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
93 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BR_BA) \
94                                 | BR_MS_GPCM \
95                                 | BR_PS_32 \
96                                 | BR_V)
97
98 /* FLASH timing (0x0000_0c54) */
99 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_GPCM_CSNT \
100                                         | OR_GPCM_ACS_DIV4 \
101                                         | OR_GPCM_SCY_5 \
102                                         | OR_GPCM_TRLX)
103
104 #define CONFIG_SYS_PRELIM_OR_AM         OR_AM_1GB /* OR addr mask: 1 GiB */
105
106 #define CONFIG_SYS_OR0_PRELIM           (CONFIG_SYS_PRELIM_OR_AM  \
107                                         | CONFIG_SYS_OR_TIMING_FLASH)
108
109 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_1GB)
110
111                                         /* Window base at flash base */
112 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
113
114 /* disable remaining mappings */
115 #define CONFIG_SYS_BR1_PRELIM           0x00000000
116 #define CONFIG_SYS_OR1_PRELIM           0x00000000
117 #define CONFIG_SYS_LBLAWBAR1_PRELIM     0x00000000
118 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x00000000
119
120 #define CONFIG_SYS_BR2_PRELIM           0x00000000
121 #define CONFIG_SYS_OR2_PRELIM           0x00000000
122 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0x00000000
123 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x00000000
124
125 #define CONFIG_SYS_BR3_PRELIM           0x00000000
126 #define CONFIG_SYS_OR3_PRELIM           0x00000000
127 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0x00000000
128 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x00000000
129
130 /*
131  * Monitor config
132  */
133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
134
135 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
136 # define CONFIG_SYS_RAMBOOT
137 #else
138 # undef  CONFIG_SYS_RAMBOOT
139 #endif
140
141 #define CONFIG_SYS_INIT_RAM_LOCK        1
142 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000 /* Initial RAM address */
143 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM*/
144
145 #define CONFIG_SYS_GBL_DATA_OFFSET      \
146                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
147 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
148
149                                 /* Reserve 384 kB = 3 sect. for Mon */
150 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)
151                                 /* Reserve 512 kB for malloc */
152 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)
153
154 /*
155  * Serial Port
156  */
157 #define CONFIG_CONS_INDEX       1
158 #define CONFIG_SYS_NS16550_SERIAL
159 #define CONFIG_SYS_NS16550_REG_SIZE     1
160 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
161
162 #define CONFIG_SYS_BAUDRATE_TABLE  \
163                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
164
165 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
166 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
167
168 /*
169  * I2C
170  */
171 #define CONFIG_SYS_I2C
172 #define CONFIG_SYS_I2C_FSL
173 #define CONFIG_SYS_FSL_I2C_SPEED        400000
174 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
175 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
176
177 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
178 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16 bit */
180 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32 bytes/write */
181 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12      /* 10ms +/- 20% */
182
183 /* I2C RTC */
184 #define CONFIG_RTC_DS1337                       /* use ds1337 rtc via i2c */
185 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68 */
186
187 /*
188  * TSEC
189  */
190 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
191 #define CONFIG_MII
192
193 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
194 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
195 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
196 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
197
198 #if defined(CONFIG_TSEC_ENET)
199
200 #define CONFIG_TSEC1            1
201 #define CONFIG_TSEC1_NAME       "TSEC0"
202 #define CONFIG_TSEC2            1
203 #define CONFIG_TSEC2_NAME       "TSEC1"
204 #define TSEC1_PHY_ADDR          2
205 #define TSEC2_PHY_ADDR          1
206 #define TSEC1_PHYIDX            0
207 #define TSEC2_PHYIDX            0
208 #define TSEC1_FLAGS             TSEC_GIGABIT
209 #define TSEC2_FLAGS             TSEC_GIGABIT
210
211 /* Options are: TSEC[0-1] */
212 #define CONFIG_ETHPRIME         "TSEC0"
213
214 #endif  /* CONFIG_TSEC_ENET */
215
216 /*
217  * General PCI
218  * Addresses are mapped 1-1.
219  */
220
221 #if defined(CONFIG_PCI)
222
223 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
224
225 /* PCI1 host bridge */
226 #define CONFIG_SYS_PCI1_MEM_BASE        0x90000000
227 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
228 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
229 #define CONFIG_SYS_PCI1_MMIO_BASE       \
230                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
231 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
232 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
233 #define CONFIG_SYS_PCI1_IO_BASE         0xe2000000
234 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
235 #define CONFIG_SYS_PCI1_IO_SIZE         0x1000000       /* 16M */
236
237 #undef CONFIG_EEPRO100
238 #define CONFIG_EEPRO100
239 #undef CONFIG_TULIP
240
241 #if !defined(CONFIG_PCI_PNP)
242         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
243         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_MEM_BASE
244         #define PCI_IDSEL_NUMBER        0x1c    /* slot0 (IDSEL) = 28 */
245 #endif
246
247 #define CONFIG_SYS_PCI_SUBSYS_VENDORID          0x1957  /* Freescale */
248
249 #endif  /* CONFIG_PCI */
250
251 /*
252  * Environment
253  */
254 #define CONFIG_ENV_IS_IN_FLASH  1
255 #define CONFIG_ENV_ADDR         \
256                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
257 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) for env */
258 #define CONFIG_ENV_SIZE         0x8000  /*  32K max size */
259 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
260 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
261
262 #define CONFIG_LOADS_ECHO               1 /* echo on for serial download */
263 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1 /* allow baudrate change */
264
265 /*
266  * BOOTP options
267  */
268 #define CONFIG_BOOTP_BOOTFILESIZE
269 #define CONFIG_BOOTP_BOOTPATH
270 #define CONFIG_BOOTP_GATEWAY
271 #define CONFIG_BOOTP_HOSTNAME
272
273 /*
274  * Command line configuration.
275  */
276 #if defined(CONFIG_PCI)
277     #define CONFIG_CMD_PCI
278 #endif
279
280 /*
281  * Miscellaneous configurable options
282  */
283 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
284 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
285
286 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
287 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
288
289 #if defined(CONFIG_CMD_KGDB)
290         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
291 #else
292         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
293 #endif
294
295                                 /* Print Buffer Size */
296 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
297 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
298                                 /* Boot Argument Buffer Size */
299 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
300
301 #undef CONFIG_WATCHDOG          /* watchdog disabled */
302
303 /*
304  * For booting Linux, the board info and command line data
305  * have to be in the first 256 MB of memory, since this is
306  * the maximum mapped by the Linux kernel during initialization.
307  */
308                                 /* Initial Memory map for Linux */
309 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
310
311 #define CONFIG_SYS_HRCW_LOW (\
312         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
313         HRCWL_DDR_TO_SCB_CLK_1X1 |\
314         HRCWL_CSB_TO_CLKIN_4X1 |\
315         HRCWL_VCO_1X2 |\
316         HRCWL_CORE_TO_CSB_2X1)
317
318 #if defined(PCI_64BIT)
319 #define CONFIG_SYS_HRCW_HIGH (\
320         HRCWH_PCI_HOST |\
321         HRCWH_64_BIT_PCI |\
322         HRCWH_PCI1_ARBITER_ENABLE |\
323         HRCWH_PCI2_ARBITER_DISABLE |\
324         HRCWH_CORE_ENABLE |\
325         HRCWH_FROM_0X00000100 |\
326         HRCWH_BOOTSEQ_DISABLE |\
327         HRCWH_SW_WATCHDOG_DISABLE |\
328         HRCWH_ROM_LOC_LOCAL_16BIT |\
329         HRCWH_TSEC1M_IN_GMII |\
330         HRCWH_TSEC2M_IN_GMII)
331 #else
332 #define CONFIG_SYS_HRCW_HIGH (\
333         HRCWH_PCI_HOST |\
334         HRCWH_32_BIT_PCI |\
335         HRCWH_PCI1_ARBITER_ENABLE |\
336         HRCWH_PCI2_ARBITER_DISABLE |\
337         HRCWH_CORE_ENABLE |\
338         HRCWH_FROM_0X00000100 |\
339         HRCWH_BOOTSEQ_DISABLE |\
340         HRCWH_SW_WATCHDOG_DISABLE |\
341         HRCWH_ROM_LOC_LOCAL_16BIT |\
342         HRCWH_TSEC1M_IN_GMII |\
343         HRCWH_TSEC2M_IN_GMII)
344 #endif
345
346 /* System IO Config */
347 #define CONFIG_SYS_SICRH        0
348 #define CONFIG_SYS_SICRL        SICRL_LDP_A
349
350 /* i-cache and d-cache disabled */
351 #define CONFIG_SYS_HID0_INIT    0x000000000
352 #define CONFIG_SYS_HID0_FINAL   (CONFIG_SYS_HID0_INIT | \
353                                  HID0_ENABLE_INSTRUCTION_CACHE)
354 #define CONFIG_SYS_HID2 HID2_HBE
355
356 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
357
358 /* DDR 0 - 512M */
359 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
360                                 | BATL_PP_RW \
361                                 | BATL_MEMCOHERENCE)
362 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
363                                 | BATU_BL_256M \
364                                 | BATU_VS \
365                                 | BATU_VP)
366 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
367                                 | BATL_PP_RW \
368                                 | BATL_MEMCOHERENCE)
369 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
370                                 | BATU_BL_256M \
371                                 | BATU_VS \
372                                 | BATU_VP)
373
374 /* stack in DCACHE @ 512M (no backing mem) */
375 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_INIT_RAM_ADDR \
376                                 | BATL_PP_RW \
377                                 | BATL_MEMCOHERENCE)
378 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_INIT_RAM_ADDR \
379                                 | BATU_BL_128K \
380                                 | BATU_VS \
381                                 | BATU_VP)
382
383 /* PCI */
384 #ifdef CONFIG_PCI
385 #define CONFIG_PCI_INDIRECT_BRIDGE
386 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MEM_BASE \
387                                 | BATL_PP_RW \
388                                 | BATL_MEMCOHERENCE)
389 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MEM_BASE \
390                                 | BATU_BL_256M \
391                                 | BATU_VS \
392                                 | BATU_VP)
393 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI1_MMIO_BASE \
394                                 | BATL_PP_RW \
395                                 | BATL_MEMCOHERENCE \
396                                 | BATL_GUARDEDSTORAGE)
397 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI1_MMIO_BASE \
398                                 | BATU_BL_256M \
399                                 | BATU_VS \
400                                 | BATU_VP)
401 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_IO_BASE \
402                                 | BATL_PP_RW \
403                                 | BATL_CACHEINHIBIT \
404                                 | BATL_GUARDEDSTORAGE)
405 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_IO_BASE \
406                                 | BATU_BL_16M \
407                                 | BATU_VS \
408                                 | BATU_VP)
409 #else
410 #define CONFIG_SYS_IBAT3L       (0)
411 #define CONFIG_SYS_IBAT3U       (0)
412 #define CONFIG_SYS_IBAT4L       (0)
413 #define CONFIG_SYS_IBAT4U       (0)
414 #define CONFIG_SYS_IBAT5L       (0)
415 #define CONFIG_SYS_IBAT5U       (0)
416 #endif
417
418 /* IMMRBAR */
419 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_IMMR \
420                                 | BATL_PP_RW \
421                                 | BATL_CACHEINHIBIT \
422                                 | BATL_GUARDEDSTORAGE)
423 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_IMMR \
424                                 | BATU_BL_1M \
425                                 | BATU_VS \
426                                 | BATU_VP)
427
428 /* FLASH */
429 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_FLASH_BASE \
430                                 | BATL_PP_RW \
431                                 | BATL_CACHEINHIBIT \
432                                 | BATL_GUARDEDSTORAGE)
433 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_FLASH_BASE \
434                                 | BATU_BL_256M \
435                                 | BATU_VS \
436                                 | BATU_VP)
437
438 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
439 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
440 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
441 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
442 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
443 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
444 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
445 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
446 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
447 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
448 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
449 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
450 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
451 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
452 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
453 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
454
455 #if defined(CONFIG_CMD_KGDB)
456 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
457 #endif
458
459 /*
460  * Environment Configuration
461  */
462
463                                 /* default location for tftp and bootm */
464 #define CONFIG_LOADADDR         400000
465
466 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
467
468 #define CONFIG_PREBOOT  "echo;" \
469         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
470         "echo"
471
472 #undef  CONFIG_BOOTARGS
473
474 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
475         "netdev=eth0\0"                                                 \
476         "hostname=tqm834x\0"                                            \
477         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
478                 "nfsroot=${serverip}:${rootpath}\0"                     \
479         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
480         "addip=setenv bootargs ${bootargs} "                            \
481                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
482                 ":${hostname}:${netdev}:off panic=1\0"                  \
483         "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
484         "flash_nfs_old=run nfsargs addip addcons;"                      \
485                 "bootm ${kernel_addr}\0"                                \
486         "flash_nfs=run nfsargs addip addcons;"                          \
487                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
488         "flash_self_old=run ramargs addip addcons;"                     \
489                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
490         "flash_self=run ramargs addip addcons;"                         \
491                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
492         "net_nfs_old=tftp 400000 ${bootfile};"                          \
493                 "run nfsargs addip addcons;bootm\0"                     \
494         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
495                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
496                 "run nfsargs addip addcons; "                           \
497                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
498         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
499         "bootfile=tqm834x/uImage\0"                                     \
500         "fdtfile=tqm834x/tqm834x.dtb\0"                                 \
501         "kernel_addr_r=400000\0"                                        \
502         "fdt_addr_r=600000\0"                                           \
503         "ramdisk_addr_r=800000\0"                                       \
504         "kernel_addr=800C0000\0"                                        \
505         "fdt_addr=800A0000\0"                                           \
506         "ramdisk_addr=80300000\0"                                       \
507         "u-boot=tqm834x/u-boot.bin\0"                                   \
508         "load=tftp 200000 ${u-boot}\0"                                  \
509         "update=protect off 80000000 +${filesize};"                     \
510                 "era 80000000 +${filesize};"                            \
511                 "cp.b 200000 80000000 ${filesize}\0"                    \
512         "upd=run load update\0"                                         \
513         ""
514
515 #define CONFIG_BOOTCOMMAND      "run flash_self"
516
517 /*
518  * JFFS2 partitions
519  */
520 /* mtdparts command line support */
521 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
522 #define CONFIG_FLASH_CFI_MTD
523 #define MTDIDS_DEFAULT          "nor0=TQM834x-0"
524
525 /* default mtd partition table */
526 #define MTDPARTS_DEFAULT        "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
527                                                 "1m(kernel),2m(initrd)," \
528                                                 "-(user);" \
529
530 #endif  /* __CONFIG_H */