1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * TQM8349 board configuration file
15 * High Level Configuration Options
17 #define CONFIG_E300 1 /* E300 Family */
19 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
20 #define CONFIG_SYS_IMMR 0xff400000
24 * LCRR: DLL bypass, Clock divider is 8
26 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
28 * External Local Bus rate is
29 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
31 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
32 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
34 /* board pre init: do not call, nothing to do */
36 /* detect the number of flash banks */
41 /* DDR is system memory*/
42 #define CONFIG_SYS_DDR_BASE 0x00000000
43 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
44 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
45 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */
46 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
47 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
49 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
50 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
51 #define CONFIG_SYS_MEMTEST_END 0x00100000
54 * FLASH on the Local Bus
56 #undef CONFIG_SYS_FLASH_CHECKSUM
57 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
58 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
59 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
62 * FLASH bank number detection
66 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
67 * Flash banks has to be determined at runtime and stored in a gloabl variable
68 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
69 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
70 * flash_info, and should be made sufficiently large to accomodate the number
71 * of banks that might actually be detected. Since most (all?) Flash related
72 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
73 * the board, it is defined as tqm834x_num_flash_banks.
75 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
77 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
79 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
80 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
85 /* FLASH timing (0x0000_0c54) */
86 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
91 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
93 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
94 | CONFIG_SYS_OR_TIMING_FLASH)
96 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB)
98 /* Window base at flash base */
99 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
101 /* disable remaining mappings */
102 #define CONFIG_SYS_BR1_PRELIM 0x00000000
103 #define CONFIG_SYS_OR1_PRELIM 0x00000000
104 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
105 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
107 #define CONFIG_SYS_BR2_PRELIM 0x00000000
108 #define CONFIG_SYS_OR2_PRELIM 0x00000000
109 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
110 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
112 #define CONFIG_SYS_BR3_PRELIM 0x00000000
113 #define CONFIG_SYS_OR3_PRELIM 0x00000000
114 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
115 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
122 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
123 # define CONFIG_SYS_RAMBOOT
125 # undef CONFIG_SYS_RAMBOOT
128 #define CONFIG_SYS_INIT_RAM_LOCK 1
129 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
130 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
132 #define CONFIG_SYS_GBL_DATA_OFFSET \
133 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
134 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
136 /* Reserve 384 kB = 3 sect. for Mon */
137 #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
138 /* Reserve 512 kB for malloc */
139 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
144 #define CONFIG_SYS_NS16550_SERIAL
145 #define CONFIG_SYS_NS16550_REG_SIZE 1
146 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
148 #define CONFIG_SYS_BAUDRATE_TABLE \
149 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
157 #define CONFIG_SYS_I2C
158 #define CONFIG_SYS_I2C_FSL
159 #define CONFIG_SYS_FSL_I2C_SPEED 400000
160 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
161 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
163 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
164 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
165 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
166 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
167 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
170 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
171 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
177 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
178 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
179 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
180 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
182 #if defined(CONFIG_TSEC_ENET)
184 #define CONFIG_TSEC1 1
185 #define CONFIG_TSEC1_NAME "TSEC0"
186 #define CONFIG_TSEC2 1
187 #define CONFIG_TSEC2_NAME "TSEC1"
188 #define TSEC1_PHY_ADDR 2
189 #define TSEC2_PHY_ADDR 1
190 #define TSEC1_PHYIDX 0
191 #define TSEC2_PHYIDX 0
192 #define TSEC1_FLAGS TSEC_GIGABIT
193 #define TSEC2_FLAGS TSEC_GIGABIT
195 /* Options are: TSEC[0-1] */
196 #define CONFIG_ETHPRIME "TSEC0"
198 #endif /* CONFIG_TSEC_ENET */
200 #if defined(CONFIG_PCI)
202 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
204 /* PCI1 host bridge */
205 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
206 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
207 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
208 #define CONFIG_SYS_PCI1_MMIO_BASE \
209 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
210 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
211 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
212 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
213 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
214 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
216 #undef CONFIG_EEPRO100
217 #define CONFIG_EEPRO100
220 #if !defined(CONFIG_PCI_PNP)
221 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
222 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
223 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
226 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
228 #endif /* CONFIG_PCI */
233 #define CONFIG_ENV_ADDR \
234 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
235 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
236 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
237 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
238 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
240 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
241 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
246 #define CONFIG_BOOTP_BOOTFILESIZE
249 * Miscellaneous configurable options
251 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
253 #undef CONFIG_WATCHDOG /* watchdog disabled */
256 * For booting Linux, the board info and command line data
257 * have to be in the first 256 MB of memory, since this is
258 * the maximum mapped by the Linux kernel during initialization.
260 /* Initial Memory map for Linux */
261 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
263 /* System IO Config */
264 #define CONFIG_SYS_SICRH 0
265 #define CONFIG_SYS_SICRL SICRL_LDP_A
267 /* i-cache and d-cache disabled */
268 #define CONFIG_SYS_HID0_INIT 0x000000000
269 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
270 HID0_ENABLE_INSTRUCTION_CACHE)
271 #define CONFIG_SYS_HID2 HID2_HBE
273 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
276 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
279 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
283 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
286 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
291 /* stack in DCACHE @ 512M (no backing mem) */
292 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
295 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
302 #define CONFIG_PCI_INDIRECT_BRIDGE
303 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
306 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
310 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
312 | BATL_MEMCOHERENCE \
313 | BATL_GUARDEDSTORAGE)
314 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
318 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
320 | BATL_CACHEINHIBIT \
321 | BATL_GUARDEDSTORAGE)
322 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
327 #define CONFIG_SYS_IBAT3L (0)
328 #define CONFIG_SYS_IBAT3U (0)
329 #define CONFIG_SYS_IBAT4L (0)
330 #define CONFIG_SYS_IBAT4U (0)
331 #define CONFIG_SYS_IBAT5L (0)
332 #define CONFIG_SYS_IBAT5U (0)
336 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
338 | BATL_CACHEINHIBIT \
339 | BATL_GUARDEDSTORAGE)
340 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
346 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
348 | BATL_CACHEINHIBIT \
349 | BATL_GUARDEDSTORAGE)
350 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
355 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
356 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
357 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
358 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
359 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
360 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
361 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
362 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
363 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
364 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
365 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
366 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
367 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
368 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
369 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
370 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
372 #if defined(CONFIG_CMD_KGDB)
373 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
377 * Environment Configuration
380 /* default location for tftp and bootm */
381 #define CONFIG_LOADADDR 400000
383 #define CONFIG_PREBOOT "echo;" \
384 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
387 #define CONFIG_EXTRA_ENV_SETTINGS \
389 "hostname=tqm834x\0" \
390 "nfsargs=setenv bootargs root=/dev/nfs rw " \
391 "nfsroot=${serverip}:${rootpath}\0" \
392 "ramargs=setenv bootargs root=/dev/ram rw\0" \
393 "addip=setenv bootargs ${bootargs} " \
394 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
395 ":${hostname}:${netdev}:off panic=1\0" \
396 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
397 "flash_nfs_old=run nfsargs addip addcons;" \
398 "bootm ${kernel_addr}\0" \
399 "flash_nfs=run nfsargs addip addcons;" \
400 "bootm ${kernel_addr} - ${fdt_addr}\0" \
401 "flash_self_old=run ramargs addip addcons;" \
402 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
403 "flash_self=run ramargs addip addcons;" \
404 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
405 "net_nfs_old=tftp 400000 ${bootfile};" \
406 "run nfsargs addip addcons;bootm\0" \
407 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
408 "tftp ${fdt_addr_r} ${fdt_file}; " \
409 "run nfsargs addip addcons; " \
410 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
411 "rootpath=/opt/eldk/ppc_6xx\0" \
412 "bootfile=tqm834x/uImage\0" \
413 "fdtfile=tqm834x/tqm834x.dtb\0" \
414 "kernel_addr_r=400000\0" \
415 "fdt_addr_r=600000\0" \
416 "ramdisk_addr_r=800000\0" \
417 "kernel_addr=800C0000\0" \
418 "fdt_addr=800A0000\0" \
419 "ramdisk_addr=80300000\0" \
420 "u-boot=tqm834x/u-boot.bin\0" \
421 "load=tftp 200000 ${u-boot}\0" \
422 "update=protect off 80000000 +${filesize};" \
423 "era 80000000 +${filesize};" \
424 "cp.b 200000 80000000 ${filesize}\0" \
425 "upd=run load update\0" \
428 #define CONFIG_BOOTCOMMAND "run flash_self"
433 /* mtdparts command line support */
435 /* default mtd partition table */
436 #endif /* __CONFIG_H */