3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * TQM8349 board configuration file
15 #define CONFIG_DISPLAY_BOARDINFO
18 * High Level Configuration Options
20 #define CONFIG_E300 1 /* E300 Family */
21 #define CONFIG_MPC834x 1 /* MPC834x specific */
22 #define CONFIG_MPC8349 1 /* MPC8349 specific */
23 #define CONFIG_TQM834X 1 /* TQM834X board specific */
25 #define CONFIG_SYS_TEXT_BASE 0x80000000
27 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
28 #define CONFIG_SYS_IMMR 0xff400000
30 /* System clock. Primary input clock when in PCI host mode */
31 #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
35 * LCRR: DLL bypass, Clock divider is 8
37 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
39 * External Local Bus rate is
40 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
42 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
43 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
45 /* board pre init: do not call, nothing to do */
46 #undef CONFIG_BOARD_EARLY_INIT_F
48 /* detect the number of flash banks */
49 #define CONFIG_BOARD_EARLY_INIT_R
54 /* DDR is system memory*/
55 #define CONFIG_SYS_DDR_BASE 0x00000000
56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
57 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
58 #define DDR_CASLAT_25 /* CASLAT set to 2.5 */
59 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
60 #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
62 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
63 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
64 #define CONFIG_SYS_MEMTEST_END 0x00100000
67 * FLASH on the Local Bus
69 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
70 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
71 #undef CONFIG_SYS_FLASH_CHECKSUM
72 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
73 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
74 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
78 * FLASH bank number detection
82 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
83 * Flash banks has to be determined at runtime and stored in a gloabl variable
84 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
85 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
86 * flash_info, and should be made sufficiently large to accomodate the number
87 * of banks that might actually be detected. Since most (all?) Flash related
88 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
89 * the board, it is defined as tqm834x_num_flash_banks.
91 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
93 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
95 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
96 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
101 /* FLASH timing (0x0000_0c54) */
102 #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
107 #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
109 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
110 | CONFIG_SYS_OR_TIMING_FLASH)
112 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB)
114 /* Window base at flash base */
115 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
117 /* disable remaining mappings */
118 #define CONFIG_SYS_BR1_PRELIM 0x00000000
119 #define CONFIG_SYS_OR1_PRELIM 0x00000000
120 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
121 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
123 #define CONFIG_SYS_BR2_PRELIM 0x00000000
124 #define CONFIG_SYS_OR2_PRELIM 0x00000000
125 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
126 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
128 #define CONFIG_SYS_BR3_PRELIM 0x00000000
129 #define CONFIG_SYS_OR3_PRELIM 0x00000000
130 #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
131 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
136 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
138 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
139 # define CONFIG_SYS_RAMBOOT
141 # undef CONFIG_SYS_RAMBOOT
144 #define CONFIG_SYS_INIT_RAM_LOCK 1
145 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
146 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
148 #define CONFIG_SYS_GBL_DATA_OFFSET \
149 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
150 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
152 /* Reserve 384 kB = 3 sect. for Mon */
153 #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
154 /* Reserve 512 kB for malloc */
155 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
160 #define CONFIG_CONS_INDEX 1
161 #define CONFIG_SYS_NS16550_SERIAL
162 #define CONFIG_SYS_NS16550_REG_SIZE 1
163 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
165 #define CONFIG_SYS_BAUDRATE_TABLE \
166 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
168 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
169 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
174 #define CONFIG_SYS_I2C
175 #define CONFIG_SYS_I2C_FSL
176 #define CONFIG_SYS_FSL_I2C_SPEED 400000
177 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
178 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
180 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
181 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
183 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
184 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
187 #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
188 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
190 /* I2C SYSMON (LM75) */
191 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
192 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
193 #define CONFIG_SYS_DTT_MAX_TEMP 70
194 #define CONFIG_SYS_DTT_LOW_TEMP -30
195 #define CONFIG_SYS_DTT_HYSTERESIS 3
200 #define CONFIG_TSEC_ENET /* tsec ethernet support */
203 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
204 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
205 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
206 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
208 #if defined(CONFIG_TSEC_ENET)
210 #define CONFIG_TSEC1 1
211 #define CONFIG_TSEC1_NAME "TSEC0"
212 #define CONFIG_TSEC2 1
213 #define CONFIG_TSEC2_NAME "TSEC1"
214 #define TSEC1_PHY_ADDR 2
215 #define TSEC2_PHY_ADDR 1
216 #define TSEC1_PHYIDX 0
217 #define TSEC2_PHYIDX 0
218 #define TSEC1_FLAGS TSEC_GIGABIT
219 #define TSEC2_FLAGS TSEC_GIGABIT
221 /* Options are: TSEC[0-1] */
222 #define CONFIG_ETHPRIME "TSEC0"
224 #endif /* CONFIG_TSEC_ENET */
228 * Addresses are mapped 1-1.
232 #if defined(CONFIG_PCI)
234 #define CONFIG_PCI_PNP /* do pci plug-and-play */
235 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
237 /* PCI1 host bridge */
238 #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
239 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
240 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
241 #define CONFIG_SYS_PCI1_MMIO_BASE \
242 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
243 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
244 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
245 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
246 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
247 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
249 #undef CONFIG_EEPRO100
250 #define CONFIG_EEPRO100
253 #if !defined(CONFIG_PCI_PNP)
254 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
255 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
256 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
259 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
261 #endif /* CONFIG_PCI */
266 #define CONFIG_ENV_IS_IN_FLASH 1
267 #define CONFIG_ENV_ADDR \
268 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
269 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
270 #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
271 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
272 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
274 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
275 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
280 #define CONFIG_BOOTP_BOOTFILESIZE
281 #define CONFIG_BOOTP_BOOTPATH
282 #define CONFIG_BOOTP_GATEWAY
283 #define CONFIG_BOOTP_HOSTNAME
286 * Command line configuration.
288 #define CONFIG_CMD_DATE
289 #define CONFIG_CMD_DTT
290 #define CONFIG_CMD_EEPROM
291 #define CONFIG_CMD_JFFS2
292 #define CONFIG_CMD_REGINFO
294 #if defined(CONFIG_PCI)
295 #define CONFIG_CMD_PCI
299 * Miscellaneous configurable options
301 #define CONFIG_SYS_LONGHELP /* undef to save memory */
302 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
304 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
305 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
307 #if defined(CONFIG_CMD_KGDB)
308 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
310 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
313 /* Print Buffer Size */
314 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
315 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
316 /* Boot Argument Buffer Size */
317 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
319 #undef CONFIG_WATCHDOG /* watchdog disabled */
322 * For booting Linux, the board info and command line data
323 * have to be in the first 256 MB of memory, since this is
324 * the maximum mapped by the Linux kernel during initialization.
326 /* Initial Memory map for Linux */
327 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
329 #define CONFIG_SYS_HRCW_LOW (\
330 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
331 HRCWL_DDR_TO_SCB_CLK_1X1 |\
332 HRCWL_CSB_TO_CLKIN_4X1 |\
334 HRCWL_CORE_TO_CSB_2X1)
336 #if defined(PCI_64BIT)
337 #define CONFIG_SYS_HRCW_HIGH (\
340 HRCWH_PCI1_ARBITER_ENABLE |\
341 HRCWH_PCI2_ARBITER_DISABLE |\
343 HRCWH_FROM_0X00000100 |\
344 HRCWH_BOOTSEQ_DISABLE |\
345 HRCWH_SW_WATCHDOG_DISABLE |\
346 HRCWH_ROM_LOC_LOCAL_16BIT |\
347 HRCWH_TSEC1M_IN_GMII |\
348 HRCWH_TSEC2M_IN_GMII)
350 #define CONFIG_SYS_HRCW_HIGH (\
353 HRCWH_PCI1_ARBITER_ENABLE |\
354 HRCWH_PCI2_ARBITER_DISABLE |\
356 HRCWH_FROM_0X00000100 |\
357 HRCWH_BOOTSEQ_DISABLE |\
358 HRCWH_SW_WATCHDOG_DISABLE |\
359 HRCWH_ROM_LOC_LOCAL_16BIT |\
360 HRCWH_TSEC1M_IN_GMII |\
361 HRCWH_TSEC2M_IN_GMII)
364 /* System IO Config */
365 #define CONFIG_SYS_SICRH 0
366 #define CONFIG_SYS_SICRL SICRL_LDP_A
368 /* i-cache and d-cache disabled */
369 #define CONFIG_SYS_HID0_INIT 0x000000000
370 #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
371 HID0_ENABLE_INSTRUCTION_CACHE)
372 #define CONFIG_SYS_HID2 HID2_HBE
374 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
377 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
380 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
384 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
387 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
392 /* stack in DCACHE @ 512M (no backing mem) */
393 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
396 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
403 #define CONFIG_PCI_INDIRECT_BRIDGE
404 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
407 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
411 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
413 | BATL_MEMCOHERENCE \
414 | BATL_GUARDEDSTORAGE)
415 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
419 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
421 | BATL_CACHEINHIBIT \
422 | BATL_GUARDEDSTORAGE)
423 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
428 #define CONFIG_SYS_IBAT3L (0)
429 #define CONFIG_SYS_IBAT3U (0)
430 #define CONFIG_SYS_IBAT4L (0)
431 #define CONFIG_SYS_IBAT4U (0)
432 #define CONFIG_SYS_IBAT5L (0)
433 #define CONFIG_SYS_IBAT5U (0)
437 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
439 | BATL_CACHEINHIBIT \
440 | BATL_GUARDEDSTORAGE)
441 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
447 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
449 | BATL_CACHEINHIBIT \
450 | BATL_GUARDEDSTORAGE)
451 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
456 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
457 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
458 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
459 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
460 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
461 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
462 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
463 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
464 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
465 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
466 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
467 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
468 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
469 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
470 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
471 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
473 #if defined(CONFIG_CMD_KGDB)
474 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
478 * Environment Configuration
481 /* default location for tftp and bootm */
482 #define CONFIG_LOADADDR 400000
484 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
486 #define CONFIG_BAUDRATE 115200
488 #define CONFIG_PREBOOT "echo;" \
489 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
492 #undef CONFIG_BOOTARGS
494 #define CONFIG_EXTRA_ENV_SETTINGS \
496 "hostname=tqm834x\0" \
497 "nfsargs=setenv bootargs root=/dev/nfs rw " \
498 "nfsroot=${serverip}:${rootpath}\0" \
499 "ramargs=setenv bootargs root=/dev/ram rw\0" \
500 "addip=setenv bootargs ${bootargs} " \
501 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
502 ":${hostname}:${netdev}:off panic=1\0" \
503 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
504 "flash_nfs_old=run nfsargs addip addcons;" \
505 "bootm ${kernel_addr}\0" \
506 "flash_nfs=run nfsargs addip addcons;" \
507 "bootm ${kernel_addr} - ${fdt_addr}\0" \
508 "flash_self_old=run ramargs addip addcons;" \
509 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
510 "flash_self=run ramargs addip addcons;" \
511 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
512 "net_nfs_old=tftp 400000 ${bootfile};" \
513 "run nfsargs addip addcons;bootm\0" \
514 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
515 "tftp ${fdt_addr_r} ${fdt_file}; " \
516 "run nfsargs addip addcons; " \
517 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
518 "rootpath=/opt/eldk/ppc_6xx\0" \
519 "bootfile=tqm834x/uImage\0" \
520 "fdtfile=tqm834x/tqm834x.dtb\0" \
521 "kernel_addr_r=400000\0" \
522 "fdt_addr_r=600000\0" \
523 "ramdisk_addr_r=800000\0" \
524 "kernel_addr=800C0000\0" \
525 "fdt_addr=800A0000\0" \
526 "ramdisk_addr=80300000\0" \
527 "u-boot=tqm834x/u-boot.bin\0" \
528 "load=tftp 200000 ${u-boot}\0" \
529 "update=protect off 80000000 +${filesize};" \
530 "era 80000000 +${filesize};" \
531 "cp.b 200000 80000000 ${filesize}\0" \
532 "upd=run load update\0" \
535 #define CONFIG_BOOTCOMMAND "run flash_self"
540 /* mtdparts command line support */
541 #define CONFIG_CMD_MTDPARTS
542 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
543 #define CONFIG_FLASH_CFI_MTD
544 #define MTDIDS_DEFAULT "nor0=TQM834x-0"
546 /* default mtd partition table */
547 #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
548 "1m(kernel),2m(initrd)," \
551 #endif /* __CONFIG_H */