3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
37 #define CONFIG_MPC8272_FAMILY 1
38 #define CONFIG_TQM8272 1
40 #define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */
41 #define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */
43 #define STK82xx_150 1 /* on a STK82xx.150 */
45 #define CONFIG_CPM2 1 /* Has a CPM2 */
47 #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
49 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
51 #define CONFIG_BOARD_EARLY_INIT_R 1
53 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
54 #define CONFIG_BAUDRATE 230400
56 #define CONFIG_BAUDRATE 115200
59 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
61 #undef CONFIG_BOOTARGS
63 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "nfsargs=setenv bootargs root=/dev/nfs rw " \
67 "nfsroot=${serverip}:${rootpath}\0" \
68 "ramargs=setenv bootargs root=/dev/ram rw\0" \
69 "hostname=tqm8272\0" \
70 "addip=setenv bootargs ${bootargs} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
72 ":${hostname}:${netdev}:off panic=1\0" \
73 "addcons=setenv bootargs ${bootargs} " \
74 "console=$(consdev),$(baudrate)\0" \
75 "flash_nfs=run nfsargs addip addcons;" \
76 "bootm ${kernel_addr}\0" \
77 "flash_self=run ramargs addip addcons;" \
78 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
79 "net_nfs=tftp 300000 ${bootfile};" \
80 "run nfsargs addip addcons;bootm\0" \
81 "rootpath=/opt/eldk/ppc_82xx\0" \
82 "bootfile=/tftpboot/tqm8272/uImage\0" \
83 "kernel_addr=40080000\0" \
84 "ramdisk_addr=40100000\0" \
85 "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \
86 "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \
87 "cp.b 300000 40000000 40000;" \
88 "setenv filesize;saveenv\0" \
89 "cphwib=cp.b 4003fc00 33fc00 400\0" \
90 "upd=run load;run cphwib;run update\0" \
92 #define CONFIG_BOOTCOMMAND "run flash_self"
97 /* enable I2C and select the hardware/software driver */
98 #undef CONFIG_HARD_I2C /* I2C with hardware support */
99 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
100 #define ADD_CMD_I2C CFG_CMD_I2C | \
104 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
105 #define CFG_I2C_SLAVE 0x7F
108 * Software (bit-bang) I2C driver configuration
110 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
111 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
112 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
113 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
114 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
115 else iop->pdat &= ~0x00010000
116 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
117 else iop->pdat &= ~0x00020000
118 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
123 #define CFG_I2C_EEPROM_ADDR_LEN 2
124 #define CFG_EEPROM_PAGE_WRITE_BITS 4
125 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
126 #define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */
127 #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
130 #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
131 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
133 /* I2C SYSMON (LM75) */
134 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
135 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
136 #define CFG_DTT_MAX_TEMP 70
137 #define CFG_DTT_LOW_TEMP -30
138 #define CFG_DTT_HYSTERESIS 3
141 #undef CONFIG_HARD_I2C
142 #undef CONFIG_SOFT_I2C
143 #define ADD_CMD_I2C 0
147 * select serial console configuration
149 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
150 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
153 * if CONFIG_CONS_NONE is defined, then the serial console routines must
154 * defined elsewhere (for example, on the cogent platform, there are serial
155 * ports on the motherboard which are used for the serial console - see
156 * cogent/cma101/serial.[ch]).
158 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
159 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
160 #undef CONFIG_CONS_NONE /* define if console on something else*/
161 #ifdef CONFIG_82xx_CONS_SMC1
162 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
164 #ifdef CONFIG_82xx_CONS_SMC2
165 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */
168 #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
169 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
170 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
173 * select ethernet configuration
175 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
176 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
179 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
180 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
181 * from CONFIG_COMMANDS to remove support for networking.
183 * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
184 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
186 #define CFG_FCC_ETHERNET
188 #if defined(CFG_FCC_ETHERNET)
189 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
190 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
191 #undef CONFIG_ETHER_NONE /* define if ether on something else */
192 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
194 #define CONFIG_ETHER_ON_SCC /* define if ether on SCC */
195 #undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
196 #undef CONFIG_ETHER_NONE /* define if ether on something else */
197 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
200 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
206 # define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
208 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
213 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
214 * - Enable Full Duplex in FSMR
216 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
217 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
218 # define CFG_CPMFCR_RAMTYPE 0
219 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
221 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
223 #define CONFIG_MII /* MII PHY management */
224 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
226 * GPIO pins used for bit-banged MII communications
228 #define MDIO_PORT 2 /* Port C */
231 #define CFG_MDIO_PIN 0x00008000 /* PC16 */
232 #define CFG_MDC_PIN 0x00004000 /* PC17 */
236 #define CFG_MDIO_PIN 0x00000002 /* PC30 */
237 #define CFG_MDC_PIN 0x00000001 /* PC31 */
241 #define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
242 #define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
243 #define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
245 #define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
246 else iop->pdat &= ~CFG_MDIO_PIN
248 #define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
249 else iop->pdat &= ~CFG_MDC_PIN
251 #define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CFG_MDIO_PIN; iop->pdir = tmp;})
252 #define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CFG_MDIO_PIN; iop->pdir = tmp;})
253 #define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
255 #define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDIO_PIN; iop->pdat = tmp;}\
256 else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDIO_PIN; iop->pdat = tmp;}
258 #define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDC_PIN; iop->pdat = tmp;}\
259 else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDC_PIN; iop->pdat = tmp;}
262 #define MIIDELAY udelay(1)
265 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
266 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
268 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
269 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
271 #undef CONFIG_WATCHDOG /* watchdog disabled */
273 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
275 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
279 * Command line configuration.
281 #include <config_cmd_default.h>
283 #define CONFIG_CMD_I2C
284 #define CONFIG_CMD_DHCP
285 #define CONFIG_CMD_MII
286 #define CONFIG_CMD_NAND
287 #define CONFIG_CMD_NFS
288 #define CONFIG_CMD_PCI
289 #define CONFIG_CMD_PING
290 #define CONFIG_CMD_SNTP
294 * Miscellaneous configurable options
296 #define CFG_LONGHELP /* undef to save memory */
297 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
300 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
301 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
302 #ifdef CFG_HUSH_PARSER
303 #define CFG_PROMPT_HUSH_PS2 "> "
307 #if defined(CONFIG_CMD_KGDB)
308 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
310 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
312 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
313 #define CFG_MAXARGS 16 /* max number of command args */
314 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
316 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
317 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
319 #define CFG_LOAD_ADDR 0x300000 /* default load address */
321 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
323 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
325 #define CFG_RESET_ADDRESS 0x40000104 /* "bad" address */
328 * For booting Linux, the board info and command line data
329 * have to be in the first 8 MB of memory, since this is
330 * the maximum mapped by the Linux kernel during initialization.
332 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
334 /*-----------------------------------------------------------------------
336 *-----------------------------------------------------------------------
338 #define CFG_CAN_BASE 0x51000000
339 #define CFG_CAN_SIZE 1
340 #define CFG_CAN_BR ((CFG_CAN_BASE & BRx_BA_MSK) |\
345 #define CFG_CAN_OR (MEG_TO_AM(CFG_CAN_SIZE) |\
349 /* What should the base address of the main FLASH be and how big is
350 * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk
351 * The main FLASH is whichever is connected to *CS0.
353 #define CFG_FLASH0_BASE 0x40000000
354 #define CFG_FLASH0_SIZE 32 /* 32 MB */
356 /* Flash bank size (for preliminary settings)
358 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
360 /*-----------------------------------------------------------------------
363 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
364 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
366 #define CFG_FLASH_CFI /* flash is CFI compat. */
367 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
368 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
369 #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
371 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
372 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
374 #define CFG_UPDATE_FLASH_SIZE
376 #define CFG_ENV_IS_IN_FLASH 1
377 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000)
378 #define CFG_ENV_SIZE 0x20000
379 #define CFG_ENV_SECT_SIZE 0x20000
380 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SIZE)
381 #define CFG_ENV_SIZE_REDUND 0x20000
383 /* Where is the Hardwareinformation Block (from Monitor Sources) */
384 #define MON_RES_LENGTH (0x0003FC00)
385 #define HWIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH)
386 #define HWIB_INFO_LEN 512
387 #define CIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
388 #define CIB_INFO_LEN 512
390 #define CFG_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */
391 #define CFG_HWINFO_SIZE 0x00000060 /* size of HW Info block */
392 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
394 /*-----------------------------------------------------------------------
396 *-----------------------------------------------------------------------
398 #if defined(CONFIG_CMD_NAND)
400 #define CFG_NAND_CS_DIST 0x80
401 #define CFG_NAND_UPM_WRITE_CMD_OFS 0x20
402 #define CFG_NAND_UPM_WRITE_ADDR_OFS 0x40
404 #define CFG_NAND_BR ((CFG_NAND0_BASE & BRx_BA_MSK) |\
409 #define CFG_NAND_OR (MEG_TO_AM(CFG_NAND_SIZE) |\
413 #define CFG_NAND_SIZE 1
414 #define CFG_NAND0_BASE 0x50000000
415 #define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
416 #define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
417 #define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
419 #define CFG_MAX_NAND_DEVICE 4 /* Max number of NAND devices */
420 #define NAND_MAX_CHIPS 1
422 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
428 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
429 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
430 #define WRITE_NAND_UPM(d, adr, off) do \
432 volatile unsigned char *addr = (unsigned char *) (adr + off); \
433 WRITE_NAND(d, addr); \
436 #endif /* CFG_CMD_NAND */
440 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
441 #define CONFIG_PCI_PNP
442 #define CONFIG_EEPRO100
443 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
444 #define CONFIG_PCI_SCAN_SHOW
447 /*-----------------------------------------------------------------------
448 * Hard Reset Configuration Words
450 * if you change bits in the HRCW, you must also change the CFG_*
451 * defines for the various registers affected by the HRCW e.g. changing
452 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
455 #define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
457 # define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
459 #define CFG_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
462 /* no slaves so just fill with zeros */
463 #define CFG_HRCW_SLAVE1 0
464 #define CFG_HRCW_SLAVE2 0
465 #define CFG_HRCW_SLAVE3 0
466 #define CFG_HRCW_SLAVE4 0
467 #define CFG_HRCW_SLAVE5 0
468 #define CFG_HRCW_SLAVE6 0
469 #define CFG_HRCW_SLAVE7 0
471 /*-----------------------------------------------------------------------
472 * Internal Memory Mapped Register
474 #define CFG_IMMR 0xFFF00000
476 /*-----------------------------------------------------------------------
477 * Definitions for initial stack pointer and data area (in DPRAM)
479 #define CFG_INIT_RAM_ADDR CFG_IMMR
480 #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
481 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
482 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
483 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
485 /*-----------------------------------------------------------------------
486 * Start addresses for the final memory configuration
487 * (Set up by the startup code)
488 * Please note that CFG_SDRAM_BASE _must_ start at 0
490 #define CFG_SDRAM_BASE 0x00000000
491 #define CFG_FLASH_BASE CFG_FLASH0_BASE
492 #define CFG_MONITOR_BASE TEXT_BASE
493 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
494 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
497 * Internal Definitions
501 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
502 #define BOOTFLAG_WARM 0x02 /* Software reboot */
504 /*-----------------------------------------------------------------------
505 * Cache Configuration
507 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
508 #if defined(CONFIG_CMD_KGDB)
509 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
512 /*-----------------------------------------------------------------------
513 * HIDx - Hardware Implementation-dependent Registers 2-11
514 *-----------------------------------------------------------------------
515 * HID0 also contains cache control - initially enable both caches and
516 * invalidate contents, then the final state leaves only the instruction
517 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
518 * but Soft reset does not.
520 * HID1 has only read-only information - nothing to set.
522 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
524 #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
527 /*-----------------------------------------------------------------------
528 * RMR - Reset Mode Register 5-5
529 *-----------------------------------------------------------------------
530 * turn on Checkstop Reset Enable
532 #define CFG_RMR RMR_CSRE
534 /*-----------------------------------------------------------------------
535 * BCR - Bus Configuration 4-25
536 *-----------------------------------------------------------------------
538 #define CFG_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */
539 #define BCR_APD01 0x10000000
540 #define CFG_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */
542 /*-----------------------------------------------------------------------
543 * SIUMCR - SIU Module Configuration 4-31
544 *-----------------------------------------------------------------------
546 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
547 #define CFG_SIUMCR_LOW (SIUMCR_DPPC00)
548 #define CFG_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE)
550 #define CFG_SIUMCR (SIUMCR_DPPC00)
553 /*-----------------------------------------------------------------------
554 * SYPCR - System Protection Control 4-35
555 * SYPCR can only be written once after reset!
556 *-----------------------------------------------------------------------
557 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
559 #if defined(CONFIG_WATCHDOG)
560 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
561 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
563 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
564 SYPCR_SWRI|SYPCR_SWP)
565 #endif /* CONFIG_WATCHDOG */
567 /*-----------------------------------------------------------------------
568 * TMCNTSC - Time Counter Status and Control 4-40
569 *-----------------------------------------------------------------------
570 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
571 * and enable Time Counter
573 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
575 /*-----------------------------------------------------------------------
576 * PISCR - Periodic Interrupt Status and Control 4-42
577 *-----------------------------------------------------------------------
578 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
581 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
583 /*-----------------------------------------------------------------------
584 * SCCR - System Clock Control 9-8
585 *-----------------------------------------------------------------------
586 * Ensure DFBRG is Divide by 16
588 #define CFG_SCCR SCCR_DFBRG01
590 /*-----------------------------------------------------------------------
591 * RCCR - RISC Controller Configuration 13-7
592 *-----------------------------------------------------------------------
597 * Init Memory Controller:
599 * Bank Bus Machine PortSz Device
600 * ---- --- ------- ------ ------
601 * 0 60x GPCM 32 bit FLASH
602 * 1 60x SDRAM 64 bit SDRAM
603 * 2 60x UPMB 8 bit NAND
604 * 3 60x UPMC 8 bit CAN
610 #undef CFG_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */
612 #define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */
614 /* Minimum mask to separate preliminary
615 * address ranges for CS[0:2]
617 #define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
619 #define CFG_MPTPR 0x4000
621 /*-----------------------------------------------------------------------------
622 * Address for Mode Register Set (MRS) command
623 *-----------------------------------------------------------------------------
624 * In fact, the address is rather configuration data presented to the SDRAM on
625 * its address lines. Because the address lines may be mux'ed externally either
626 * for 8 column or 9 column devices, some bits appear twice in the 8260's
629 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
630 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
631 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
632 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
633 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
634 *-----------------------------------------------------------------------------
636 #define CFG_MRS_OFFS 0x00000110
640 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
645 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
651 /* SDRAM on TQM8272 can have either 8 or 9 columns.
652 * The number affects configuration values.
655 /* Bank 1 - 60x bus SDRAM
657 #define CFG_PSRT 0x20 /* Low Value */
658 /* #define CFG_PSRT 0x10 Fast Value */
659 #define CFG_LSRT 0x20 /* Local Bus */
661 #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
666 #define CFG_OR1_PRELIM CFG_OR1_8COL
668 /* SDRAM initialization values for 8-column chips
670 #define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
672 ORxS_ROWST_PBI1_A7 |\
675 #define CFG_PSDMR_8COL (PSDMR_PBI |\
676 PSDMR_SDAM_A15_IS_A5 |\
677 PSDMR_BSMA_A12_A14 |\
678 PSDMR_SDA10_PBI1_A8 |\
689 /* SDRAM initialization values for 9-column chips
691 #define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
693 ORxS_ROWST_PBI1_A5 |\
696 #define CFG_PSDMR_9COL (PSDMR_PBI |\
697 PSDMR_SDAM_A16_IS_A5 |\
698 PSDMR_BSMA_A12_A14 |\
699 PSDMR_SDA10_PBI1_A7 |\
709 #define CFG_OR1_10COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
711 ORxS_ROWST_PBI1_A4 |\
714 #define CFG_PSDMR_10COL (PSDMR_PBI |\
715 PSDMR_SDAM_A17_IS_A5 |\
716 PSDMR_BSMA_A12_A14 |\
717 PSDMR_SDA10_PBI1_A4 |\
727 #define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */
728 #define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */
729 #define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */
730 #define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */
731 #define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */
732 #define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */
734 #define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */
735 #define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */
736 #define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */
737 #define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */
738 #define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */
739 #define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */
741 #define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */
742 #define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */
743 #define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */
744 #define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */
745 #define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */
746 #define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */
748 #define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */
749 #define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */
750 #define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */
751 #define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */
752 #define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */
753 #define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */
755 #endif /* CFG_RAMBOOT */
757 #endif /* __CONFIG_H */