2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2004-2006
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * High Level Configuration Options
35 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37 #define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38 #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
40 /* On a Cameron or on a FO300 board or ... */
41 #if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300)
42 #define CONFIG_STK52XX 1 /* ... on a STK52XX board */
45 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
47 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
48 #define BOOTFLAG_WARM 0x02 /* Software reboot */
50 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
51 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
52 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
56 * Serial console configuration
58 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
59 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
60 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
63 #define CFG_DEVICE_NULLDEV 1 /* enable null device */
64 #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
65 #define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */
68 #define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
69 /* switch is closed */
72 #undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
74 #endif /* CONFIG_FO300 */
77 #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
78 #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
79 #define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
80 #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
81 #define CONFIG_BOARD_EARLY_INIT_R
82 #endif /* CONFIG_STK52XX */
86 * 0x40000000 - 0x4fffffff - PCI Memory
87 * 0x50000000 - 0x50ffffff - PCI IO Space
91 #define CONFIG_PCI_PNP 1
92 /* #define CONFIG_PCI_SCAN_SHOW 1 */
94 #define CONFIG_PCI_MEM_BUS 0x40000000
95 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
96 #define CONFIG_PCI_MEM_SIZE 0x10000000
98 #define CONFIG_PCI_IO_BUS 0x50000000
99 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
100 #define CONFIG_PCI_IO_SIZE 0x01000000
102 #define CONFIG_NET_MULTI 1
103 #define CONFIG_EEPRO100 1
104 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
105 #define CONFIG_NS8382X 1
106 #endif /* CONFIG_STK52XX */
109 #define ADD_PCI_CMD CFG_CMD_PCI
111 #define ADD_PCI_CMD 0
117 #ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
119 #define CONFIG_VIDEO_SM501
120 #define CONFIG_VIDEO_SM501_32BPP
121 #define CONFIG_CFB_CONSOLE
122 #define CONFIG_VIDEO_LOGO
125 #define CONFIG_CONSOLE_EXTRA_INFO
127 #define CONFIG_VIDEO_BMP_LOGO
130 #define CONFIG_VGA_AS_SINGLE_DEVICE
131 #define CONFIG_VIDEO_SW_CURSOR
132 #define CONFIG_SPLASH_SCREEN
133 #define CFG_CONSOLE_IS_IN_ENV
134 #endif /* #ifndef CONFIG_TQM5200S */
137 #define ADD_BMP_CMD CFG_CMD_BMP
139 #define ADD_BMP_CMD 0
143 #define CONFIG_MAC_PARTITION
144 #define CONFIG_DOS_PARTITION
145 #define CONFIG_ISO_PARTITION
148 #if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
149 #define CONFIG_USB_OHCI
150 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
151 #define CONFIG_USB_STORAGE
153 #define ADD_USB_CMD 0
156 #ifndef CONFIG_CAM5200
158 #define CONFIG_POST (CFG_POST_MEMORY | \
164 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
165 /* preserve space for the post_word at end of on-chip SRAM */
166 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
168 #define CFG_CMD_POST_DIAG 0
172 #if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) || defined(CONFIG_FO300)
173 #define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
175 #define ADD_IDE_CMD 0
181 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
195 CFG_CMD_POST_DIAG | \
200 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
201 #include <cmd_confdefs.h>
203 #define CONFIG_TIMESTAMP /* display image timestamps */
205 #if (TEXT_BASE != 0xFFF00000)
206 # define CFG_LOWBOOT 1 /* Boot low */
212 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
214 #define CONFIG_PREBOOT "echo;" \
215 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
218 #undef CONFIG_BOOTARGS
220 #ifdef CONFIG_STK52XX
221 # if defined(CONFIG_TQM5200_B)
222 # if defined(CFG_LOWBOOT)
224 "update=protect off FC000000 FC07FFFF;" \
225 "erase FC000000 FC07FFFF;" \
226 "cp.b 200000 FC000000 ${filesize};" \
227 "protect on FC000000 FC07FFFF\0"
228 # else /* highboot */
230 "update=protect off FFF00000 FFF7FFFF;" \
231 "erase FFF00000 FFF7FFFF;" \
232 "cp.b 200000 FFF00000 ${filesize};" \
233 "protect on FFF00000 FFF7FFFF\0"
234 # endif /* CFG_LOWBOOT */
235 # else /* !CONFIG_TQM5200_B */
237 "update=protect off FC000000 FC05FFFF;" \
238 "erase FC000000 FC05FFFF;" \
239 "cp.b 200000 FC000000 ${filesize};" \
240 "protect on FC000000 FC05FFFF\0"
241 # endif /* CONFIG_TQM5200_B */
242 #elif defined (CONFIG_CAM5200)
244 "update=protect off FC000000 FC03FFFF;" \
245 "erase FC000000 FC03FFFF;" \
246 "cp.b 200000 FC000000 ${filesize};" \
247 "protect on FC000000 FC03FFFF\0"
248 #elif defined (CONFIG_FO300)
250 "update=protect off FC000000 FC05FFFF;" \
251 "erase FC000000 FC05FFFF;" \
252 "cp.b 200000 FC000000 ${filesize};" \
253 "protect on FC000000 FC05FFFF\0"
255 # error "Unknown Carrier Board"
256 #endif /* CONFIG_STK52XX */
258 #define CONFIG_EXTRA_ENV_SETTINGS \
260 "rootpath=/opt/eldk/ppc_6xx\0" \
261 "ramargs=setenv bootargs root=/dev/ram rw\0" \
262 "nfsargs=setenv bootargs root=/dev/nfs rw " \
263 "nfsroot=${serverip}:${rootpath}\0" \
264 "addip=setenv bootargs ${bootargs} " \
265 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
266 ":${hostname}:${netdev}:off panic=1\0" \
267 "addcons=setenv bootargs ${bootargs} " \
268 "console=ttyS0,${baudrate}\0" \
269 "flash_self=run ramargs addip addcons;" \
270 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
271 "flash_nfs=run nfsargs addip addcons;" \
272 "bootm ${kernel_addr}\0" \
273 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
275 "bootfile=/tftpboot/tqm5200/uImage\0" \
276 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
277 "load=tftp 200000 ${u-boot}\0" \
281 #define CONFIG_BOOTCOMMAND "run net_nfs"
284 * IPB Bus clocking configuration.
286 #define CFG_IPBSPEED_133 /* define for 133MHz speed */
288 #if defined(CFG_IPBSPEED_133)
290 * PCI Bus clocking configuration
292 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
293 * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
294 * been tested with a IPB Bus Clock of 66 MHz.
296 #define CFG_PCISPEED_66 /* define for 66MHz speed */
302 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
303 #ifdef CONFIG_TQM5200_REV100
304 #define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
306 #define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
310 * I2C clock frequency
312 * Please notice, that the resulting clock frequency could differ from the
313 * configured value. This is because the I2C clock is derived from system
314 * clock over a frequency divider with only a few divider values. U-boot
315 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
316 * approximation allways lies below the configured value, never above.
318 #define CFG_I2C_SPEED 100000 /* 100 kHz */
319 #define CFG_I2C_SLAVE 0x7F
322 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
323 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
324 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
325 * same configuration could be used.
327 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
328 #define CFG_I2C_EEPROM_ADDR_LEN 2
329 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
330 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
333 * HW-Monitor configuration on Mini-FAP
335 #if defined (CONFIG_MINIFAP)
336 #define CFG_I2C_HWMON_ADDR 0x2C
339 /* List of I2C addresses to be verified by POST */
340 #if defined (CONFIG_MINIFAP)
342 #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
343 CFG_I2C_HWMON_ADDR, \
348 * Flash configuration
350 #define CFG_FLASH_BASE 0xFC000000
352 /* use CFI flash driver */
353 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
354 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
355 #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
356 #define CFG_FLASH_EMPTY_INFO
357 #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
358 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
359 #define CFG_FLASH_USE_BUFFER_WRITE 1
361 #if defined (CONFIG_CAM5200)
362 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
363 #elif defined(CONFIG_TQM5200_B)
364 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000)
366 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
369 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
372 /* Dynamic MTD partition support */
373 #define CONFIG_JFFS2_CMDLINE
374 #define MTDIDS_DEFAULT "nor0=TQM5200-0"
376 #ifdef CONFIG_STK52XX
377 # if defined(CONFIG_TQM5200_B)
378 # if defined(CFG_LOWBOOT)
379 # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:1m(firmware)," \
385 # else /* highboot */
386 # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:2560k(kernel)," \
392 # endif /* CFG_LOWBOOT */
393 # else /* !CONFIG_TQM5200_B */
394 # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
400 # endif /* CONFIG_TQM5200_B */
401 #elif defined (CONFIG_CAM5200)
402 # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
408 #elif defined (CONFIG_FO300)
409 # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
416 # error "Unknown Carrier Board"
417 #endif /* CONFIG_STK52XX */
420 * Environment settings
422 #define CFG_ENV_IS_IN_FLASH 1
423 #define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
424 #if defined(CONFIG_TQM5200_B)
425 #define CFG_ENV_SECT_SIZE 0x40000
427 #define CFG_ENV_SECT_SIZE 0x20000
428 #endif /* CONFIG_TQM5200_B */
429 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
430 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
435 #define CFG_MBAR 0xF0000000
436 #define CFG_SDRAM_BASE 0x00000000
437 #define CFG_DEFAULT_MBAR 0x80000000
439 /* Use ON-Chip SRAM until RAM will be available */
440 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
442 /* preserve space for the post_word at end of on-chip SRAM */
443 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
445 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
449 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
450 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
451 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
453 #define CFG_MONITOR_BASE TEXT_BASE
454 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
455 # define CFG_RAMBOOT 1
458 #if defined (CONFIG_CAM5200)
459 # define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
460 #elif defined(CONFIG_TQM5200_B)
461 # define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
463 # define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
466 #define CFG_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
467 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
470 * Ethernet configuration
472 #define CONFIG_MPC5xxx_FEC 1
474 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
476 /* #define CONFIG_FEC_10MBIT 1 */
477 #define CONFIG_PHY_ADDR 0x00
482 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
483 * Bit 0 (mask: 0x80000000): 1
484 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
485 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
486 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
487 * Use for REV200 STK52XX boards and FO300 boards. Do not use
488 * with REV100 modules (because, there I2C1 is used as I2C bus)
489 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
490 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
491 * 000 -> All PSC2 pins are GIOPs
492 * 001 -> CAN1/2 on PSC2 pins
493 * Use for REV100 STK52xx boards
495 * use PSC3: Bits 20-23 (mask: 0x00000f00)
496 * 1100 -> UART/SPI (on FO300 board)
498 * on STK52xx and FO300:
499 * use as UART. Pins PSC6_0 to PSC6_3 are used.
500 * Bits 9:11 (mask: 0x00700000):
501 * 101 -> PSC6 : Extended POST test is not available
502 * on MINI-FAP and TQM5200_IB:
503 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
504 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
505 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
508 #if defined (CONFIG_MINIFAP)
509 # define CFG_GPS_PORT_CONFIG 0x91000004
510 #elif defined (CONFIG_STK52XX)
511 # if defined (CONFIG_STK52XX_REV100)
512 # define CFG_GPS_PORT_CONFIG 0x81500014
513 # else /* STK52xx REV200 and above */
514 # if defined (CONFIG_TQM5200_REV100)
515 # error TQM5200 REV100 not supported on STK52XX REV200 or above
516 # else/* TQM5200 REV200 and above */
517 # define CFG_GPS_PORT_CONFIG 0x91500004
520 #elif defined (CONFIG_FO300)
521 # define CFG_GPS_PORT_CONFIG 0x91502c24
522 #else /* TMQ5200 Inbetriebnahme-Board */
523 # define CFG_GPS_PORT_CONFIG 0x81000004
529 #if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
530 # define CONFIG_RTC_M41T11 1
531 # define CFG_I2C_RTC_ADDR 0x68
532 # define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
535 # define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
539 * Miscellaneous configurable options
541 #define CFG_LONGHELP /* undef to save memory */
542 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
544 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
545 #define CFG_PROMPT_HUSH_PS2 "> "
547 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
548 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
550 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
552 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
553 #define CFG_MAXARGS 16 /* max number of command args */
554 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
556 /* Enable an alternate, more extensive memory test */
557 #define CFG_ALT_MEMTEST
559 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
560 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
562 #define CFG_LOAD_ADDR 0x100000 /* default load address */
564 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
567 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
568 * which is normally part of the default commands (CFV_CMD_DFL)
573 * Various low-level settings
575 #if defined(CONFIG_MPC5200)
576 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
577 #define CFG_HID0_FINAL HID0_ICE
579 #define CFG_HID0_INIT 0
580 #define CFG_HID0_FINAL 0
583 #define CFG_BOOTCS_START CFG_FLASH_BASE
584 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
585 #ifdef CFG_PCISPEED_66
586 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
588 #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
590 #define CFG_CS0_START CFG_FLASH_BASE
591 #define CFG_CS0_SIZE CFG_FLASH_SIZE
593 #define CONFIG_LAST_STAGE_INIT
596 * SRAM - Do not map below 2 GB in address space, because this area is used
597 * for SDRAM autosizing.
599 #define CFG_CS2_START 0xE5000000
600 #define CFG_CS2_SIZE 0x100000 /* 1 MByte */
601 #define CFG_CS2_CFG 0x0004D930
604 * Grafic controller - Do not map below 2 GB in address space, because this
605 * area is used for SDRAM autosizing.
607 #define SM501_FB_BASE 0xE0000000
608 #define CFG_CS1_START (SM501_FB_BASE)
609 #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
610 #define CFG_CS1_CFG 0x8F48FF70
611 #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
613 #define CFG_CS_BURST 0x00000000
614 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
616 #define CFG_RESET_ADDRESS 0xff000000
618 /*-----------------------------------------------------------------------
620 *-----------------------------------------------------------------------
622 #define CONFIG_USB_CLOCK 0x0001BBBB
623 #define CONFIG_USB_CONFIG 0x00001000
625 /*-----------------------------------------------------------------------
626 * IDE/ATA stuff Supports IDE harddisk
627 *-----------------------------------------------------------------------
630 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
632 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
633 #undef CONFIG_IDE_LED /* LED for ide not supported */
635 #define CONFIG_IDE_RESET /* reset for ide supported */
636 #define CONFIG_IDE_PREINIT
638 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
639 #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
641 #define CFG_ATA_IDE0_OFFSET 0x0000
643 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
645 /* Offset for data I/O */
646 #define CFG_ATA_DATA_OFFSET (0x0060)
648 /* Offset for normal register accesses */
649 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
651 /* Offset for alternate registers */
652 #define CFG_ATA_ALT_OFFSET (0x005C)
654 /* Interval between registers */
655 #define CFG_ATA_STRIDE 4
657 #endif /* __CONFIG_H */