3 * EMK Elektronik GmbH <www.emk-elektronik.de>
4 * Reinhard Meyer <r.meyer@emk-elektronik.de>
6 * Configuation settings for the TOP860 board.
8 * -----------------------------------------------------------------
9 * SPDX-License-Identifier: GPL-2.0+
12 * TOP860 is a simple module:
13 * 16-bit wide FLASH on CS0 (2MB or more)
14 * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
15 * FEC with Am79C874 100-Base-T and Fiber Optic
16 * Ports available, but we choose SMC1 for Console
17 * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
18 * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
20 * This config has been copied from MBX.h / MBX860T.h
23 * board/config.h - configuration options, board specific
30 * High Level Configuration Options
34 /*-----------------------------------------------------------------------
37 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
38 #define CONFIG_MPC860T 1 /* even better... an FEC! */
39 #define CONFIG_TOP860 1 /* ...on a TOP860 module */
41 #define CONFIG_SYS_TEXT_BASE 0x80000000
43 #undef CONFIG_WATCHDOG /* watchdog disabled */
44 #define CONFIG_IDENT_STRING " EMK TOP860"
46 /*-----------------------------------------------------------------------
49 #define CONFIG_SYSCLK 49152000
50 #define CONFIG_SYS_XTAL 32768
53 #define CONFIG_RTC_MPC8xx
55 /*-----------------------------------------------------------------------
56 * Physical memory map as defined by EMK
58 #define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register */
59 #define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH in final mapping */
60 #define CONFIG_SYS_DRAM_BASE 0x00000000 /* DRAM in final mapping */
61 #define CONFIG_SYS_FLASH_MAX 0x00400000 /* max FLASH to expect */
62 #define CONFIG_SYS_DRAM_MAX 0x01000000 /* max DRAM to expect */
64 /*-----------------------------------------------------------------------
67 #define CONFIG_SYS_MF (CONFIG_SYSCLK/CONFIG_SYS_XTAL)
68 #define CONFIG_SYS_CPUCLOCK CONFIG_SYSCLK
69 #define CONFIG_SYS_BRGCLOCK CONFIG_SYSCLK
70 #define CONFIG_SYS_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF)
71 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
72 #define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK
74 /*-----------------------------------------------------------------------
77 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
78 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
80 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
81 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
83 #define CONFIG_SYS_FLASH_CFI
85 /*-----------------------------------------------------------------------
88 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
89 #undef CONFIG_8xx_CONS_SMC2
90 #define CONFIG_BAUDRATE 9600
93 * Allow partial commands to be matched to uniqueness.
95 #define CONFIG_SYS_MATCH_PARTIAL_CMD
99 * Command line configuration.
101 #include <config_cmd_default.h>
103 #define CONFIG_CMD_ASKENV
104 #define CONFIG_CMD_DHCP
105 #define CONFIG_CMD_I2C
106 #define CONFIG_CMD_EEPROM
107 #define CONFIG_CMD_REGINFO
108 #define CONFIG_CMD_IMMAP
109 #define CONFIG_CMD_ELF
110 #define CONFIG_CMD_DATE
111 #define CONFIG_CMD_MII
112 #define CONFIG_CMD_BEDBUG
115 #define CONFIG_SOURCE 1
116 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1
117 #undef CONFIG_LOADS_ECHO /* NO echo on for serial download */
120 #define CONFIG_SYS_LONGHELP /* undef to save memory */
122 #undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */
125 #if defined(CONFIG_CMD_KGDB)
126 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
128 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
131 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
132 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
133 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
135 /*-----------------------------------------------------------------------
136 * Memory Test Command
138 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
139 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
141 /*-----------------------------------------------------------------------
142 * Environment handler
143 * only the first 6k in EEPROM are available for user. Of that we use 256b
145 #define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
146 #define CONFIG_ENV_OFFSET 0x1000
147 #define CONFIG_ENV_SIZE 0x0700
148 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
149 #define CONFIG_SYS_FACT_OFFSET 0x1800
150 #define CONFIG_SYS_FACT_SIZE 0x0800
151 #define CONFIG_SYS_I2C_FACT_ADDR 0x57
152 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
154 #define CONFIG_SYS_EEPROM_SIZE 0x2000
155 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
156 #define CONFIG_ENV_OVERWRITE
157 #define CONFIG_MISC_INIT_R
159 #define CONFIG_SYS_I2C
160 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
161 #define CONFIG_SYS_I2C_SOFT_SPEED 100000
162 #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
166 #define __I2C_DIR immr->im_cpm.cp_pbdir
167 #define __I2C_DAT immr->im_cpm.cp_pbdat
168 #define __I2C_PAR immr->im_cpm.cp_pbpar
169 #define __I2C_ODR immr->im_cpm.cp_pbodr
170 #define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
171 __I2C_ODR &= ~(SDA|SCL); \
172 __I2C_DAT |= (SDA|SCL); \
173 __I2C_DIR|=(SDA|SCL); }
174 #define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
175 #define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
176 #define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
177 #define I2C_DELAY { udelay(5); }
178 #define I2C_ACTIVE { __I2C_DIR |= SDA; }
179 #define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
181 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
183 /*-----------------------------------------------------------------------
184 * defines we need to get FEC running
186 #define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */
187 #define FEC_ENET 1 /* eth.c needs it that way... */
188 #define CONFIG_SYS_DISCOVER_PHY 1
190 #define CONFIG_MII_INIT 1
191 #define CONFIG_PHY_ADDR 31
193 /*-----------------------------------------------------------------------
196 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
197 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
198 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
200 /*-----------------------------------------------------------------------
201 * Start addresses for the final memory configuration
202 * (Set up by the startup code)
203 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
205 #define CONFIG_SYS_SDRAM_BASE 0x00000000
206 #define CONFIG_SYS_FLASH_BASE 0x80000000
208 /*-----------------------------------------------------------------------
209 * Definitions for initial stack pointer and data area (in DPRAM)
211 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
212 #define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
213 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
214 #define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
215 #define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
216 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
218 /*-----------------------------------------------------------------------
219 * Cache Configuration
221 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
222 #if defined(CONFIG_CMD_KGDB)
223 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
226 /* Interrupt level assignments.
228 #define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
230 /*-----------------------------------------------------------------------
231 * Debug Enable Register
232 *-----------------------------------------------------------------------
235 #define CONFIG_SYS_DER 0 /* used in start.S */
237 /*-----------------------------------------------------------------------
238 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
239 *-----------------------------------------------------------------------
240 * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
241 * 12 MF calculated Multiplication factor
243 * 1 SPLSS 0 System PLL lock status sticky
244 * 1 TEXPS 1 Timer expired status
246 * 1 TMIST 0 Timers interrupt status
248 * 1 CSRC 0 Clock source (0=DFNH, 1=DFNL)
249 * 2 LPM 00 Low-power modes
250 * 1 CSR 0 Checkstop reset enable
251 * 1 LOLRE 0 Loss-of-lock reset enable
252 * 1 FIOPD 0 Force I/O pull down
255 #define CONFIG_SYS_PLPRCR (PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20))
257 /*-----------------------------------------------------------------------
258 * SYPCR - System Protection Control 11-9
259 * SYPCR can only be written once after reset!
260 *-----------------------------------------------------------------------
262 * 16 SWTC 0xffff Software watchdog timer count
263 * 8 BMT 0xff Bus monitor timing
264 * 1 BME 1 Bus monitor enable
266 * 1 SWF 1 Software watchdog freeze
267 * 1 SWE 0/1 Software watchdog enable
268 * 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET)
269 * 1 SWP 0/1 Software watchdog prescale (1=/2048)
271 #if defined (CONFIG_WATCHDOG)
272 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
273 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
275 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
278 /*-----------------------------------------------------------------------
279 * SIUMCR - SIU Module Configuration 11-6
280 *-----------------------------------------------------------------------
282 * 1 EARB 0 External arbitration
283 * 3 EARP 000 External arbitration request priority
285 * 1 DSHW 0 Data show cycles
286 * 2 DBGC 00 Debug pin configuration
287 * 2 DBPC 00 Debug port pins configuration
289 * 1 FRC 0 FRZ pin configuration
290 * 1 DLK 0 Debug register lock
291 * 1 OPAR 0 Odd parity
292 * 1 PNCS 0 Parity enable for non memory controller regions
293 * 1 DPC 0 Data parity pins configuration
294 * 1 MPRE 0 Multiprocessor reservation enable
295 * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
296 * 1 AEME 0 Async external master enable
297 * 1 SEME 0 Sync external master enable
298 * 1 BSC 0 Byte strobe configuration
299 * 1 GB5E 0 GPL_B5 enable
300 * 1 B2DD 0 Bank 2 double drive
301 * 1 B3DD 0 Bank 3 double drive
304 #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC11)
306 /*-----------------------------------------------------------------------
307 * TBSCR - Time Base Status and Control 11-26
308 *-----------------------------------------------------------------------
309 * Clear Reference Interrupt Status, Timebase freezing enabled
311 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
313 /*-----------------------------------------------------------------------
314 * PISCR - Periodic Interrupt Status and Control 11-31
315 *-----------------------------------------------------------------------
316 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
318 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
320 /*-----------------------------------------------------------------------
321 * SCCR - System Clock and reset Control Register 15-27
322 *-----------------------------------------------------------------------
323 * set up SCCR (System Clock and Reset Control Register)
325 * 2 COM 11 Clock output module (00=full, 01=half, 11=off)
327 * 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2)
328 * 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512)
329 * 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK)
330 * 1 CRQEN 0 CPM request enable
331 * 1 PRQEN 0 Power management request enable
333 * 2 EBDF xx External bus division factor
335 * 2 DFSYNC 00 Division factor for SYNCLK
336 * 2 DFBRG 00 Division factor for BRGCLK
337 * 3 DFNL 000 Division factor low frequency
338 * 3 DFNH 000 Division factor high frequency
343 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
345 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
348 /*-----------------------------------------------------------------------
349 * Chip Select 0 - FLASH
350 *-----------------------------------------------------------------------
353 /* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */
354 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
355 #define CONFIG_SYS_OR0_PRELIM (-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH)
356 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V )
358 /*-----------------------------------------------------------------------
360 *-----------------------------------------------------------------------
364 * Set the autoboot delay in seconds. A delay of -1 disables autoboot
366 #define CONFIG_BOOTDELAY 5
369 * Pass the clock frequency to the Linux kernel in units of MHz
371 #define CONFIG_CLOCKS_IN_MHZ
373 #define CONFIG_PREBOOT \
376 #undef CONFIG_BOOTARGS
377 #define CONFIG_BOOTCOMMAND \
379 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
380 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
386 #define CONFIG_BOOTP_SUBNETMASK
387 #define CONFIG_BOOTP_GATEWAY
388 #define CONFIG_BOOTP_HOSTNAME
389 #define CONFIG_BOOTP_BOOTPATH
390 #define CONFIG_BOOTP_BOOTFILESIZE
394 * Set default IP stuff just to get bootstrap entries into the
395 * environment so that we can source the full default environment.
397 #define CONFIG_ETHADDR 9a:52:63:15:85:25
398 #define CONFIG_SERVERIP 10.0.4.200
399 #define CONFIG_IPADDR 10.0.4.111
401 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
404 * For booting Linux, the board info and command line data
405 * have to be in the first 8 MB of memory, since this is
406 * the maximum mapped by the Linux kernel during initialization.
408 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
410 #endif /* __CONFIG_H */