2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2004-2006
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * High Level Configuration Options
35 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37 #define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38 #define CONFIG_TB5200 1 /* ... on a TB5200 base board */
41 * Valid values for CONFIG_SYS_TEXT_BASE are:
42 * 0xFC000000 boot low (standard configuration with room for
43 * max 64 MByte Flash ROM)
44 * 0xFFF00000 boot high (for a backup copy of U-Boot)
45 * 0x00100000 boot from RAM (for testing only)
47 #ifndef CONFIG_SYS_TEXT_BASE
48 #define CONFIG_SYS_TEXT_BASE 0xFC000000
51 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
53 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
54 #define BOOTFLAG_WARM 0x02 /* Software reboot */
56 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
59 * Serial console configuration
61 #define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */
62 #define CONFIG_SERIAL_MULTI 1 /* support multiple consoles */
63 #define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */
64 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
65 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
72 #define CONFIG_VIDEO_SM501
73 #define CONFIG_VIDEO_SM501_32BPP
74 #define CONFIG_CFB_CONSOLE
75 #define CONFIG_VIDEO_LOGO
76 #define CONFIG_VGA_AS_SINGLE_DEVICE
77 #define CONFIG_CONSOLE_EXTRA_INFO
78 #define CONFIG_VIDEO_SW_CURSOR
79 #define CONFIG_SPLASH_SCREEN
80 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
84 #define CONFIG_MAC_PARTITION
85 #define CONFIG_DOS_PARTITION
86 #define CONFIG_ISO_PARTITION
89 #define CONFIG_USB_OHCI
90 #define CONFIG_USB_STORAGE
93 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
94 CONFIG_SYS_POST_CPU | \
98 /* preserve space for the post_word at end of on-chip SRAM */
99 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
106 #define CONFIG_BOOTP_BOOTFILESIZE
107 #define CONFIG_BOOTP_BOOTPATH
108 #define CONFIG_BOOTP_GATEWAY
109 #define CONFIG_BOOTP_HOSTNAME
113 * Command line configuration.
115 #include <config_cmd_default.h>
117 #define CONFIG_CMD_ASKENV
118 #define CONFIG_CMD_DATE
119 #define CONFIG_CMD_DHCP
120 #define CONFIG_CMD_ECHO
121 #define CONFIG_CMD_EEPROM
122 #define CONFIG_CMD_EXT2
123 #define CONFIG_CMD_FAT
124 #define CONFIG_CMD_I2C
125 #define CONFIG_CMD_IDE
126 #define CONFIG_CMD_JFFS2
127 #define CONFIG_CMD_MII
128 #define CONFIG_CMD_NFS
129 #define CONFIG_CMD_PING
130 #define CONFIG_CMD_REGINFO
131 #define CONFIG_CMD_SNTP
132 #define CONFIG_CMD_BSP
133 #define CONFIG_CMD_USB
136 #define CONFIG_CMD_BMP
140 #define CONFIG_CMD_DIAG
144 #define CONFIG_TIMESTAMP /* display image timestamps */
146 #if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
147 # define CONFIG_SYS_LOWBOOT 1
153 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
155 #define CONFIG_PREBOOT "echo;" \
156 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
159 #undef CONFIG_BOOTARGS
161 #if defined(CONFIG_TQM5200_B)
162 #define CONFIG_EXTRA_ENV_SETTINGS \
164 "rootpath=/opt/eldk/ppc_6xx\0" \
165 "ramargs=setenv bootargs root=/dev/ram rw\0" \
166 "nfsargs=setenv bootargs root=/dev/nfs rw " \
167 "nfsroot=${serverip}:${rootpath}\0" \
168 "addip=setenv bootargs ${bootargs} " \
169 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
170 ":${hostname}:${netdev}:off panic=1\0" \
171 "flash_self=run ramargs addip;" \
172 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
173 "flash_nfs=run nfsargs addip;" \
174 "bootm ${kernel_addr}\0" \
175 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
176 "bootfile=/tftpboot/tqm5200/uImage\0" \
177 "load=tftp 200000 ${u-boot}\0" \
178 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
179 "update=protect off FC000000 FC07FFFF;" \
180 "erase FC000000 FC07FFFF;" \
181 "cp.b 200000 FC000000 ${filesize};" \
182 "protect on FC000000 FC07FFFF\0" \
185 #define CONFIG_EXTRA_ENV_SETTINGS \
187 "rootpath=/opt/eldk/ppc_6xx\0" \
188 "ramargs=setenv bootargs root=/dev/ram rw\0" \
189 "nfsargs=setenv bootargs root=/dev/nfs rw " \
190 "nfsroot=${serverip}:${rootpath}\0" \
191 "addip=setenv bootargs ${bootargs} " \
192 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
193 ":${hostname}:${netdev}:off panic=1\0" \
194 "flash_self=run ramargs addip;" \
195 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
196 "flash_nfs=run nfsargs addip;" \
197 "bootm ${kernel_addr}\0" \
198 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
199 "bootfile=/tftpboot/tqm5200/uImage\0" \
200 "load=tftp 200000 $(u-boot)\0" \
201 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
202 "update=protect off FC000000 FC05FFFF;" \
203 "erase FC000000 FC05FFFF;" \
204 "cp.b 200000 FC000000 ${filesize};" \
205 "protect on FC000000 FC05FFFF\0" \
207 #endif /* CONFIG_TQM5200_B */
209 #define CONFIG_BOOTCOMMAND "run net_nfs"
212 * IPB Bus clocking configuration.
214 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
216 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
218 * PCI Bus clocking configuration
220 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
221 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
222 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
224 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
230 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
231 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
234 * I2C clock frequency
236 * Please notice, that the resulting clock frequency could differ from the
237 * configured value. This is because the I2C clock is derived from system
238 * clock over a frequency divider with only a few divider values. U-boot
239 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
240 * approximation allways lies below the configured value, never above.
242 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
243 #define CONFIG_SYS_I2C_SLAVE 0x7F
246 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
247 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
248 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
249 * same configuration could be used.
251 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
252 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
254 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
256 /* List of I2C addresses to be verified by POST */
258 #define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \
259 CONFIG_SYS_I2C_RTC_ADDR, \
260 CONFIG_SYS_I2C_SLAVE }
263 * Flash configuration
265 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
267 /* use CFI flash driver */
268 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
269 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
270 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
271 #define CONFIG_SYS_FLASH_EMPTY_INFO
272 #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
273 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
274 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
276 #if !defined(CONFIG_SYS_LOWBOOT)
277 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
278 #else /* CONFIG_SYS_LOWBOOT */
279 #if defined(CONFIG_TQM5200_B)
280 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
282 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
283 #endif /* CONFIG_TQM5200_B */
284 #endif /* CONFIG_SYS_LOWBOOT */
285 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
288 /* Dynamic MTD partition support */
289 #define CONFIG_CMD_MTDPARTS
290 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
291 #define CONFIG_FLASH_CFI_MTD
292 #define MTDIDS_DEFAULT "nor0=TQM5200-0"
293 #if defined(CONFIG_TQM5200_B)
294 #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
301 #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
307 #endif /* CONFIG_TQM5200_B */
310 * Environment settings
312 #define CONFIG_ENV_IS_IN_FLASH 1
313 #define CONFIG_ENV_SIZE 0x10000
314 #if defined(CONFIG_TQM5200_B)
315 #define CONFIG_ENV_SECT_SIZE 0x40000
317 #define CONFIG_ENV_SECT_SIZE 0x20000
318 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
319 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
320 #endif /* CONFIG_TQM5200_B */
325 #define CONFIG_SYS_MBAR 0xF0000000
326 #define CONFIG_SYS_SDRAM_BASE 0x00000000
327 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
329 /* Use ON-Chip SRAM until RAM will be available */
330 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
332 /* preserve space for the post_word at end of on-chip SRAM */
333 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
335 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
339 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
340 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
341 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
343 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
344 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
345 # define CONFIG_SYS_RAMBOOT 1
348 #if defined(CONFIG_TQM5200_B)
349 #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
351 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
352 #endif /* CONFIG_TQM5200_B */
353 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
354 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
357 * Ethernet configuration
359 #define CONFIG_MPC5xxx_FEC 1
360 #define CONFIG_MPC5xxx_FEC_MII100
362 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
364 /* #define CONFIG_MPC5xxx_FEC_MII10 */
365 #define CONFIG_PHY_ADDR 0x00
370 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
371 * Bit 0 (mask: 0x80000000): 1
372 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
373 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
374 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
375 * Use for REV200 STK52XX boards. Do not use with REV100 modules
376 * (because, there I2C1 is used as I2C bus)
377 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
378 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
379 * 000 -> All PSC2 pins are GIOPs
380 * 001 -> CAN1/2 on PSC2 pins
381 * Use for REV100 STK52xx boards
382 * use PSC3: Bits 20:23 (mask: 0x00000300):
387 * use as UART. Pins PSC6_0 to PSC6_3 are used.
388 * Bits 9:11 (mask: 0x00700000):
389 * 101 -> PSC6 : Extended POST test is not available
390 * on MINI-FAP and TQM5200_IB:
391 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
392 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
393 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
396 #define CONFIG_SYS_GPS_PORT_CONFIG 0x81500114
401 #define CONFIG_RTC_M41T11 1
402 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
403 #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
407 * Miscellaneous configurable options
409 #define CONFIG_SYS_LONGHELP /* undef to save memory */
410 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
411 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
412 #if defined(CONFIG_CMD_KGDB)
413 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
415 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
417 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
418 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
419 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
421 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
422 #if defined(CONFIG_CMD_KGDB)
423 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
426 /* Enable an alternate, more extensive memory test */
427 #define CONFIG_SYS_ALT_MEMTEST
429 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
430 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
432 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
434 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
437 * Enable loopw command.
442 * Various low-level settings
444 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
445 #define CONFIG_SYS_HID0_FINAL HID0_ICE
447 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
448 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
449 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
450 #define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
452 #define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
454 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
455 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
457 #define CONFIG_LAST_STAGE_INIT
460 * SRAM - Do not map below 2 GB in address space, because this area is used
461 * for SDRAM autosizing.
463 #define CONFIG_SYS_CS2_START 0xE5000000
464 #define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
465 #define CONFIG_SYS_CS2_CFG 0x0004D930
468 * Grafic controller - Do not map below 2 GB in address space, because this
469 * area is used for SDRAM autosizing.
471 #define SM501_FB_BASE 0xE0000000
472 #define CONFIG_SYS_CS1_START (SM501_FB_BASE)
473 #define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
474 #define CONFIG_SYS_CS1_CFG 0x8F48FF70
475 #define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
477 #define CONFIG_SYS_CS_BURST 0x00000000
478 #define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
480 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
482 /*-----------------------------------------------------------------------
484 *-----------------------------------------------------------------------
486 #define CONFIG_USB_CLOCK 0x0001BBBB
487 #define CONFIG_USB_CONFIG 0x00001000
489 /*-----------------------------------------------------------------------
490 * IDE/ATA stuff Supports IDE harddisk
491 *-----------------------------------------------------------------------
494 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
496 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
497 #undef CONFIG_IDE_LED /* LED for ide not supported */
499 #define CONFIG_IDE_RESET /* reset for ide supported */
500 #define CONFIG_IDE_PREINIT
502 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
503 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
505 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
507 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
509 /* Offset for data I/O */
510 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
512 /* Offset for normal register accesses */
513 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
515 /* Offset for alternate registers */
516 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
518 /* Interval between registers */
519 #define CONFIG_SYS_ATA_STRIDE 4
521 #endif /* __CONFIG_H */