include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #ifndef CONFIG_SDCARD
  19 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  20 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  21 #else
  22 #define RESET_VECTOR_OFFSET             0x27FFC
  23 #define BOOT_PAGE_OFFSET                0x27000
  24
  25 #ifdef  CONFIG_SDCARD
  26 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  27 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  28 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  29 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  30 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  31 #endif
  32
  33 #endif
  34 #endif /* CONFIG_RAMBOOT_PBL */
  35
  36 /* High Level Configuration Options */
  37
  38 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  39 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  40 #endif
  41
  42 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  43
  44 /*
  45  * These can be toggled for performance analysis, otherwise use default.
  46  */
  47 #define CONFIG_SYS_CACHE_STASHING
  48 #ifdef CONFIG_DDR_ECC
  49 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  50 #endif
  51
  52 /*
  53  *  Config the L3 Cache as L3 SRAM
  54  */
  55 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  56 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  57 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  58
  59 #define CONFIG_SYS_DCSRBAR              0xf0000000
  60 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  61
  62 /*
  63  * DDR Setup
  64  */
  65 #define CONFIG_VERY_BIG_RAM
  66 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  67 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  68
  69 /*
  70  * IFC Definitions
  71  */
  72 #define CONFIG_SYS_FLASH_BASE   0xe0000000
  73 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  74
  75 #define CONFIG_HWCONFIG
  76
  77 /* define to use L1 as initial stack */
  78 #define CONFIG_L1_INIT_RAM
  79 #define CONFIG_SYS_INIT_RAM_LOCK
  80 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
  81 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
  82 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
  83 /* The assembler doesn't like typecast */
  84 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  85         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  86           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  87 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
  88
  89 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  90
  91 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  92
  93 /* Serial Port - controlled on board with jumper J8
  94  * open - index 2
  95  * shorted - index 1
  96  */
  97 #define CONFIG_SYS_NS16550_SERIAL
  98 #define CONFIG_SYS_NS16550_REG_SIZE     1
  99 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 100
 101 #define CONFIG_SYS_BAUDRATE_TABLE       \
 102         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 103
 104 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 105 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 106 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 107 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 108
 109 /* I2C */
 110
 111 /*
 112  * General PCI
 113  * Memory space is mapped 1-1, but I/O space must start from 0.
 114  */
 115
 116 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 117 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 118 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 119 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 120 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 121
 122 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 123 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 124 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 125 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 126 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 127
 128 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 129 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 130 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 131 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 132 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 133
 134 /* controller 4, Base address 203000 */
 135 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 136 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 137 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 138
 139 /*
 140  * Environment
 141  */
 142 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 143 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 144
 145 /*
 146  * Miscellaneous configurable options
 147  */
 148
 149 /*
 150  * For booting Linux, the board info and command line data
 151  * have to be in the first 64 MB of memory, since this is
 152  * the maximum mapped by the Linux kernel during initialization.
 153  */
 154 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 155 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 156
 157 /*
 158  * Environment Configuration
 159  */
 160 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 161 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 162
 163 #define HVBOOT                                  \
 164         "setenv bootargs config-addr=0x60000000; "      \
 165         "bootm 0x01000000 - 0x00f00000"
 166
 167 /*
 168  * DDR Setup
 169  */
 170 #define SPD_EEPROM_ADDRESS1     0x52
 171 #define SPD_EEPROM_ADDRESS2     0x54
 172 #define SPD_EEPROM_ADDRESS3     0x56
 173 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 174 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 175
 176 /*
 177  * IFC Definitions
 178  */
 179 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 180 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 181                                 + 0x8000000) | \
 182                                 CSPR_PORT_SIZE_16 | \
 183                                 CSPR_MSEL_NOR | \
 184                                 CSPR_V)
 185 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 186 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 187                                 CSPR_PORT_SIZE_16 | \
 188                                 CSPR_MSEL_NOR | \
 189                                 CSPR_V)
 190 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 191 /* NOR Flash Timing Params */
 192 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 193
 194 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 195                                 FTIM0_NOR_TEADC(0x5) | \
 196                                 FTIM0_NOR_TEAHC(0x5))
 197 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 198                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 199                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 200 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 201                                 FTIM2_NOR_TCH(0x4) | \
 202                                 FTIM2_NOR_TWPH(0x0E) | \
 203                                 FTIM2_NOR_TWP(0x1c))
 204 #define CONFIG_SYS_NOR_FTIM3    0x0
 205
 206 #define CONFIG_SYS_FLASH_QUIET_TEST
 207 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 208
 209 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 210 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 211 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 212
 213 #define CONFIG_SYS_FLASH_EMPTY_INFO
 214 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 215                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 216
 217 /* NAND Flash on IFC */
 218 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 219 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 220 #define CONFIG_SYS_NAND_BASE            0xff800000
 221 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 222
 223 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 224 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 225                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 226                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 227                                 | CSPR_V)
 228 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 229
 230 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 231                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 232                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 233                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 234                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 235                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 236                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 237
 238 /* ONFI NAND Flash mode0 Timing Params */
 239 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 240                                         FTIM0_NAND_TWP(0x18)   | \
 241                                         FTIM0_NAND_TWCHT(0x07) | \
 242                                         FTIM0_NAND_TWH(0x0a))
 243 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 244                                         FTIM1_NAND_TWBE(0x39)  | \
 245                                         FTIM1_NAND_TRR(0x0e)   | \
 246                                         FTIM1_NAND_TRP(0x18))
 247 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 248                                         FTIM2_NAND_TREH(0x0a) | \
 249                                         FTIM2_NAND_TWHRE(0x1e))
 250 #define CONFIG_SYS_NAND_FTIM3           0x0
 251
 252 #define CONFIG_SYS_NAND_DDR_LAW         11
 253 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 254 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 255
 256 #if defined(CONFIG_MTD_RAW_NAND)
 257 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 258 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 259 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 260 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 261 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 262 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 263 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 264 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 265 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 266 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 267 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 268 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 269 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 270 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 271 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 272 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 273 #else
 274 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 275 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 276 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 277 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 278 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 279 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 280 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 281 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 282 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 283 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 284 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 285 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 286 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 287 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 288 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 289 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 290 #endif
 291 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 292 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 293 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 294 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 295 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 296 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 297 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 298 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 299
 300 /* CPLD on IFC */
 301 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 302 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 303 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 304 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 305                                 | CSPR_PORT_SIZE_8 \
 306                                 | CSPR_MSEL_GPCM \
 307                                 | CSPR_V)
 308
 309 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 310 #define CONFIG_SYS_CSOR3        0x0
 311
 312 /* CPLD Timing parameters for IFC CS3 */
 313 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 314                                         FTIM0_GPCM_TEADC(0x0e) | \
 315                                         FTIM0_GPCM_TEAHC(0x0e))
 316 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 317                                         FTIM1_GPCM_TRAD(0x1f))
 318 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 319                                         FTIM2_GPCM_TCH(0x8) | \
 320                                         FTIM2_GPCM_TWP(0x1f))
 321 #define CONFIG_SYS_CS3_FTIM3            0x0
 322
 323 /* I2C */
 324 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 325 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 326
 327 #define I2C_MUX_CH_DEFAULT      0x8
 328 #define I2C_MUX_CH_VOL_MONITOR  0xa
 329 #define I2C_MUX_CH_VSC3316_FS   0xc
 330 #define I2C_MUX_CH_VSC3316_BS   0xd
 331
 332 /* Voltage monitor on channel 2*/
 333 #define I2C_VOL_MONITOR_ADDR            0x40
 334 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 335 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 336 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 337
 338 /* The lowest and highest voltage allowed for T4240RDB */
 339 #define VDD_MV_MIN                      819
 340 #define VDD_MV_MAX                      1212
 341
 342 /*
 343  * eSPI - Enhanced SPI
 344  */
 345
 346 /* Qman/Bman */
 347 #ifndef CONFIG_NOBQFMAN
 348 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 349 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 350 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 351 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 352 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 353 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 354 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 355 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 356 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 357                                         CONFIG_SYS_BMAN_CENA_SIZE)
 358 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 359 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 360 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 361 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 362 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 363 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 364 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 365 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 366 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 367 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 368 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 369                                         CONFIG_SYS_QMAN_CENA_SIZE)
 370 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 371 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 372
 373 #define CONFIG_SYS_DPAA_FMAN
 374 #define CONFIG_SYS_DPAA_PME
 375 #define CONFIG_SYS_PMAN
 376 #define CONFIG_SYS_DPAA_DCE
 377 #define CONFIG_SYS_DPAA_RMAN
 378 #define CONFIG_SYS_INTERLAKEN
 379
 380 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 381 #endif /* CONFIG_NOBQFMAN */
 382
 383 #ifdef CONFIG_SYS_DPAA_FMAN
 384 #define SGMII_PHY_ADDR1 0x0
 385 #define SGMII_PHY_ADDR2 0x1
 386 #define SGMII_PHY_ADDR3 0x2
 387 #define SGMII_PHY_ADDR4 0x3
 388 #define SGMII_PHY_ADDR5 0x4
 389 #define SGMII_PHY_ADDR6 0x5
 390 #define SGMII_PHY_ADDR7 0x6
 391 #define SGMII_PHY_ADDR8 0x7
 392 #define FM1_10GEC1_PHY_ADDR     0x10
 393 #define FM1_10GEC2_PHY_ADDR     0x11
 394 #define FM2_10GEC1_PHY_ADDR     0x12
 395 #define FM2_10GEC2_PHY_ADDR     0x13
 396 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 397 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 398 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 399 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 400 #endif
 401
 402 /*
 403 * USB
 404 */
 405
 406 #ifdef CONFIG_MMC
 407 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 408 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 409 #endif
 410
 411
 412 #define __USB_PHY_TYPE  utmi
 413
 414 /*
 415  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 416  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 417  * interleaving. It can be cacheline, page, bank, superbank.
 418  * See doc/README.fsl-ddr for details.
 419  */
 420 #ifdef CONFIG_ARCH_T4240
 421 #define CTRL_INTLV_PREFERED 3way_4KB
 422 #else
 423 #define CTRL_INTLV_PREFERED cacheline
 424 #endif
 425
 426 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 427         "hwconfig=fsl_ddr:"                                     \
 428         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 429         "bank_intlv=auto;"                                      \
 430         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 431         "netdev=eth0\0"                                         \
 432         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 433         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 434         "tftpflash=tftpboot $loadaddr $uboot && "               \
 435         "protect off $ubootaddr +$filesize && "                 \
 436         "erase $ubootaddr +$filesize && "                       \
 437         "cp.b $loadaddr $ubootaddr $filesize && "               \
 438         "protect on $ubootaddr +$filesize && "                  \
 439         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 440         "consoledev=ttyS0\0"                                    \
 441         "ramdiskaddr=2000000\0"                                 \
 442         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 443         "fdtaddr=1e00000\0"                                     \
 444         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 445         "bdev=sda3\0"
 446
 447 #define HVBOOT                                  \
 448         "setenv bootargs config-addr=0x60000000; "      \
 449         "bootm 0x01000000 - 0x00f00000"
 450
 451 #include <asm/fsl_secure_boot.h>
 452
 453 #endif  /* __CONFIG_H */