include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #define CONFIG_FSL_SATA_V2
  16 #define CONFIG_PCIE4
  17
  18 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  19
  20 #ifdef CONFIG_RAMBOOT_PBL
  21 #ifndef CONFIG_SDCARD
  22 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  23 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  24 #else
  25 #define RESET_VECTOR_OFFSET             0x27FFC
  26 #define BOOT_PAGE_OFFSET                0x27000
  27
  28 #ifdef  CONFIG_SDCARD
  29 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  30 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  31 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  32 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  33 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  34 #ifndef CONFIG_SPL_BUILD
  35 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  36 #endif
  37 #endif
  38
  39 #endif
  40 #endif /* CONFIG_RAMBOOT_PBL */
  41
  42 /* High Level Configuration Options */
  43 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  44
  45 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  46 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  47 #endif
  48
  49 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  50 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  51 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  52 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  53 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  54
  55 /*
  56  * These can be toggled for performance analysis, otherwise use default.
  57  */
  58 #define CONFIG_SYS_CACHE_STASHING
  59 #ifdef CONFIG_DDR_ECC
  60 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  61 #endif
  62
  63 #define CONFIG_ENABLE_36BIT_PHYS
  64
  65 /*
  66  *  Config the L3 Cache as L3 SRAM
  67  */
  68 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  69 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  70 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  71 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  72 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
  73 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
  74 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
  75
  76 #define CONFIG_SYS_DCSRBAR              0xf0000000
  77 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  78
  79 /*
  80  * DDR Setup
  81  */
  82 #define CONFIG_VERY_BIG_RAM
  83 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  84 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  85
  86 /*
  87  * IFC Definitions
  88  */
  89 #define CONFIG_SYS_FLASH_BASE   0xe0000000
  90 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  91
  92 #define CONFIG_HWCONFIG
  93
  94 /* define to use L1 as initial stack */
  95 #define CONFIG_L1_INIT_RAM
  96 #define CONFIG_SYS_INIT_RAM_LOCK
  97 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
  98 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
  99 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 100 /* The assembler doesn't like typecast */
 101 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 102         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 103           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 104 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 105
 106 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 107
 108 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 109
 110 /* Serial Port - controlled on board with jumper J8
 111  * open - index 2
 112  * shorted - index 1
 113  */
 114 #define CONFIG_SYS_NS16550_SERIAL
 115 #define CONFIG_SYS_NS16550_REG_SIZE     1
 116 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 117
 118 #define CONFIG_SYS_BAUDRATE_TABLE       \
 119         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 120
 121 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 122 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 123 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 124 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 125
 126 /* I2C */
 127
 128 /*
 129  * General PCI
 130  * Memory space is mapped 1-1, but I/O space must start from 0.
 131  */
 132
 133 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 134 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 135 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 136 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 137 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 138
 139 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 140 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 141 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 142 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 143 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 144
 145 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 146 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 147 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 148 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 149 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 150
 151 /* controller 4, Base address 203000 */
 152 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 153 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 154 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 155
 156 #ifdef CONFIG_PCI
 157 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 158 #endif  /* CONFIG_PCI */
 159
 160 /* SATA */
 161 #ifdef CONFIG_FSL_SATA_V2
 162 #define CONFIG_SATA1
 163 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 164 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 165 #define CONFIG_SATA2
 166 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 167 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 168
 169 #define CONFIG_LBA48
 170 #endif
 171
 172 /*
 173  * Environment
 174  */
 175 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 176 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 177
 178 /*
 179  * Miscellaneous configurable options
 180  */
 181
 182 /*
 183  * For booting Linux, the board info and command line data
 184  * have to be in the first 64 MB of memory, since this is
 185  * the maximum mapped by the Linux kernel during initialization.
 186  */
 187 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 188 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 189
 190 /*
 191  * Environment Configuration
 192  */
 193 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 194 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 195
 196 #define HVBOOT                                  \
 197         "setenv bootargs config-addr=0x60000000; "      \
 198         "bootm 0x01000000 - 0x00f00000"
 199
 200 /*
 201  * DDR Setup
 202  */
 203 #define CONFIG_SYS_SPD_BUS_NUM  0
 204 #define SPD_EEPROM_ADDRESS1     0x52
 205 #define SPD_EEPROM_ADDRESS2     0x54
 206 #define SPD_EEPROM_ADDRESS3     0x56
 207 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 208 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 209
 210 /*
 211  * IFC Definitions
 212  */
 213 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 214 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 215                                 + 0x8000000) | \
 216                                 CSPR_PORT_SIZE_16 | \
 217                                 CSPR_MSEL_NOR | \
 218                                 CSPR_V)
 219 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 220 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 221                                 CSPR_PORT_SIZE_16 | \
 222                                 CSPR_MSEL_NOR | \
 223                                 CSPR_V)
 224 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 225 /* NOR Flash Timing Params */
 226 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 227
 228 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 229                                 FTIM0_NOR_TEADC(0x5) | \
 230                                 FTIM0_NOR_TEAHC(0x5))
 231 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 232                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 233                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 234 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 235                                 FTIM2_NOR_TCH(0x4) | \
 236                                 FTIM2_NOR_TWPH(0x0E) | \
 237                                 FTIM2_NOR_TWP(0x1c))
 238 #define CONFIG_SYS_NOR_FTIM3    0x0
 239
 240 #define CONFIG_SYS_FLASH_QUIET_TEST
 241 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 242
 243 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 244 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 245 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 246
 247 #define CONFIG_SYS_FLASH_EMPTY_INFO
 248 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 249                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 250
 251 /* NAND Flash on IFC */
 252 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 253 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 254 #define CONFIG_SYS_NAND_BASE            0xff800000
 255 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 256
 257 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 258 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 259                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 260                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 261                                 | CSPR_V)
 262 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 263
 264 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 265                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 266                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 267                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 268                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 269                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 270                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 271
 272 /* ONFI NAND Flash mode0 Timing Params */
 273 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 274                                         FTIM0_NAND_TWP(0x18)   | \
 275                                         FTIM0_NAND_TWCHT(0x07) | \
 276                                         FTIM0_NAND_TWH(0x0a))
 277 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 278                                         FTIM1_NAND_TWBE(0x39)  | \
 279                                         FTIM1_NAND_TRR(0x0e)   | \
 280                                         FTIM1_NAND_TRP(0x18))
 281 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 282                                         FTIM2_NAND_TREH(0x0a) | \
 283                                         FTIM2_NAND_TWHRE(0x1e))
 284 #define CONFIG_SYS_NAND_FTIM3           0x0
 285
 286 #define CONFIG_SYS_NAND_DDR_LAW         11
 287 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 288 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 289
 290 #if defined(CONFIG_MTD_RAW_NAND)
 291 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 292 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 293 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 294 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 295 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 296 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 297 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 298 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 299 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 300 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 301 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 302 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 303 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 304 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 305 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 306 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 307 #else
 308 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 309 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 310 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 311 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 312 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 313 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 314 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 315 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 316 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 317 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 318 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 319 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 320 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 321 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 322 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 323 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 324 #endif
 325 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 326 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 327 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 328 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 329 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 330 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 331 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 332 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 333
 334 /* CPLD on IFC */
 335 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 336 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 337 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 338 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 339                                 | CSPR_PORT_SIZE_8 \
 340                                 | CSPR_MSEL_GPCM \
 341                                 | CSPR_V)
 342
 343 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 344 #define CONFIG_SYS_CSOR3        0x0
 345
 346 /* CPLD Timing parameters for IFC CS3 */
 347 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 348                                         FTIM0_GPCM_TEADC(0x0e) | \
 349                                         FTIM0_GPCM_TEAHC(0x0e))
 350 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 351                                         FTIM1_GPCM_TRAD(0x1f))
 352 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 353                                         FTIM2_GPCM_TCH(0x8) | \
 354                                         FTIM2_GPCM_TWP(0x1f))
 355 #define CONFIG_SYS_CS3_FTIM3            0x0
 356
 357 #if defined(CONFIG_RAMBOOT_PBL)
 358 #define CONFIG_SYS_RAMBOOT
 359 #endif
 360
 361 /* I2C */
 362 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 363 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 364
 365 #define I2C_MUX_CH_DEFAULT      0x8
 366 #define I2C_MUX_CH_VOL_MONITOR  0xa
 367 #define I2C_MUX_CH_VSC3316_FS   0xc
 368 #define I2C_MUX_CH_VSC3316_BS   0xd
 369
 370 /* Voltage monitor on channel 2*/
 371 #define I2C_VOL_MONITOR_ADDR            0x40
 372 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 373 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 374 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 375
 376 /* The lowest and highest voltage allowed for T4240RDB */
 377 #define VDD_MV_MIN                      819
 378 #define VDD_MV_MAX                      1212
 379
 380 /*
 381  * eSPI - Enhanced SPI
 382  */
 383
 384 /* Qman/Bman */
 385 #ifndef CONFIG_NOBQFMAN
 386 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 387 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 388 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 389 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 390 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 391 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 392 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 393 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 394 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 395                                         CONFIG_SYS_BMAN_CENA_SIZE)
 396 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 397 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 398 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 399 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 400 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 401 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 402 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 403 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 404 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 405 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 406 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 407                                         CONFIG_SYS_QMAN_CENA_SIZE)
 408 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 409 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 410
 411 #define CONFIG_SYS_DPAA_FMAN
 412 #define CONFIG_SYS_DPAA_PME
 413 #define CONFIG_SYS_PMAN
 414 #define CONFIG_SYS_DPAA_DCE
 415 #define CONFIG_SYS_DPAA_RMAN
 416 #define CONFIG_SYS_INTERLAKEN
 417
 418 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 419 #endif /* CONFIG_NOBQFMAN */
 420
 421 #ifdef CONFIG_SYS_DPAA_FMAN
 422 #define SGMII_PHY_ADDR1 0x0
 423 #define SGMII_PHY_ADDR2 0x1
 424 #define SGMII_PHY_ADDR3 0x2
 425 #define SGMII_PHY_ADDR4 0x3
 426 #define SGMII_PHY_ADDR5 0x4
 427 #define SGMII_PHY_ADDR6 0x5
 428 #define SGMII_PHY_ADDR7 0x6
 429 #define SGMII_PHY_ADDR8 0x7
 430 #define FM1_10GEC1_PHY_ADDR     0x10
 431 #define FM1_10GEC2_PHY_ADDR     0x11
 432 #define FM2_10GEC1_PHY_ADDR     0x12
 433 #define FM2_10GEC2_PHY_ADDR     0x13
 434 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 435 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 436 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 437 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 438 #endif
 439
 440 /* SATA */
 441 #ifdef CONFIG_FSL_SATA_V2
 442 #define CONFIG_SATA1
 443 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 444 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 445 #define CONFIG_SATA2
 446 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 447 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 448
 449 #define CONFIG_LBA48
 450 #endif
 451
 452 /*
 453 * USB
 454 */
 455 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 456 #define CONFIG_HAS_FSL_DR_USB
 457
 458 #ifdef CONFIG_MMC
 459 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 460 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 461 #endif
 462
 463
 464 #define __USB_PHY_TYPE  utmi
 465
 466 /*
 467  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 468  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 469  * interleaving. It can be cacheline, page, bank, superbank.
 470  * See doc/README.fsl-ddr for details.
 471  */
 472 #ifdef CONFIG_ARCH_T4240
 473 #define CTRL_INTLV_PREFERED 3way_4KB
 474 #else
 475 #define CTRL_INTLV_PREFERED cacheline
 476 #endif
 477
 478 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 479         "hwconfig=fsl_ddr:"                                     \
 480         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 481         "bank_intlv=auto;"                                      \
 482         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 483         "netdev=eth0\0"                                         \
 484         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 485         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 486         "tftpflash=tftpboot $loadaddr $uboot && "               \
 487         "protect off $ubootaddr +$filesize && "                 \
 488         "erase $ubootaddr +$filesize && "                       \
 489         "cp.b $loadaddr $ubootaddr $filesize && "               \
 490         "protect on $ubootaddr +$filesize && "                  \
 491         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 492         "consoledev=ttyS0\0"                                    \
 493         "ramdiskaddr=2000000\0"                                 \
 494         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 495         "fdtaddr=1e00000\0"                                     \
 496         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 497         "bdev=sda3\0"
 498
 499 #define HVBOOT                                  \
 500         "setenv bootargs config-addr=0x60000000; "      \
 501         "bootm 0x01000000 - 0x00f00000"
 502
 503 #include <asm/fsl_secure_boot.h>
 504
 505 #endif  /* __CONFIG_H */