include/configs/T4240RDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_FSL_SATA_V2
  14 #define CONFIG_PCIE4
  15
  16 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  17
  18 #ifdef CONFIG_RAMBOOT_PBL
  19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  20 #ifndef CONFIG_SDCARD
  21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23 #else
  24 #define CONFIG_SPL_FLUSH_IMAGE
  25 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  26 #define CONFIG_SYS_TEXT_BASE            0x00201000
  27 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  28 #define CONFIG_SPL_PAD_TO               0x40000
  29 #define CONFIG_SPL_MAX_SIZE             0x28000
  30 #define RESET_VECTOR_OFFSET             0x27FFC
  31 #define BOOT_PAGE_OFFSET                0x27000
  32
  33 #ifdef  CONFIG_SDCARD
  34 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  35 #define CONFIG_SPL_MMC_MINIMAL
  36 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  37 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  38 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  39 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  40 #ifndef CONFIG_SPL_BUILD
  41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  42 #endif
  43 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  45 #define CONFIG_SPL_MMC_BOOT
  46 #endif
  47
  48 #ifdef CONFIG_SPL_BUILD
  49 #define CONFIG_SPL_SKIP_RELOCATE
  50 #define CONFIG_SPL_COMMON_INIT_DDR
  51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  52 #define CONFIG_SYS_NO_FLASH
  53 #endif
  54
  55 #endif
  56 #endif /* CONFIG_RAMBOOT_PBL */
  57
  58 #define CONFIG_DDR_ECC
  59
  60 #define CONFIG_CMD_REGINFO
  61
  62 /* High Level Configuration Options */
  63 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  64 #define CONFIG_MP                       /* support multiple processors */
  65
  66 #ifndef CONFIG_SYS_TEXT_BASE
  67 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  68 #endif
  69
  70 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  71 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  72 #endif
  73
  74 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  75 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  76 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  77 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  78 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  79 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  80 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  81 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  82
  83 #define CONFIG_ENV_OVERWRITE
  84
  85 /*
  86  * These can be toggled for performance analysis, otherwise use default.
  87  */
  88 #define CONFIG_SYS_CACHE_STASHING
  89 #define CONFIG_BTB                      /* toggle branch predition */
  90 #ifdef CONFIG_DDR_ECC
  91 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  92 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  93 #endif
  94
  95 #define CONFIG_ENABLE_36BIT_PHYS
  96
  97 #define CONFIG_ADDR_MAP
  98 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  99
 100 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 101 #define CONFIG_SYS_MEMTEST_END          0x00400000
 102 #define CONFIG_SYS_ALT_MEMTEST
 103 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 104
 105 /*
 106  *  Config the L3 Cache as L3 SRAM
 107  */
 108 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 109 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 110 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 111 #ifdef CONFIG_RAMBOOT_PBL
 112 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 113 #endif
 114 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 115 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 116 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 117 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 118
 119 #define CONFIG_SYS_DCSRBAR              0xf0000000
 120 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 121
 122 /*
 123  * DDR Setup
 124  */
 125 #define CONFIG_VERY_BIG_RAM
 126 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 127 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 128
 129 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 130 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 131 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 132
 133 #define CONFIG_DDR_SPD
 134
 135 /*
 136  * IFC Definitions
 137  */
 138 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 139 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 140
 141 #ifdef CONFIG_SPL_BUILD
 142 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 143 #else
 144 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 145 #endif
 146
 147 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 148 #define CONFIG_MISC_INIT_R
 149
 150 #define CONFIG_HWCONFIG
 151
 152 /* define to use L1 as initial stack */
 153 #define CONFIG_L1_INIT_RAM
 154 #define CONFIG_SYS_INIT_RAM_LOCK
 155 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 156 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 157 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 158 /* The assembler doesn't like typecast */
 159 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 160         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 161           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 162 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 163
 164 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 165                                         GENERATED_GBL_DATA_SIZE)
 166 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 167
 168 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 169 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 170
 171 /* Serial Port - controlled on board with jumper J8
 172  * open - index 2
 173  * shorted - index 1
 174  */
 175 #define CONFIG_CONS_INDEX       1
 176 #define CONFIG_SYS_NS16550_SERIAL
 177 #define CONFIG_SYS_NS16550_REG_SIZE     1
 178 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 179
 180 #define CONFIG_SYS_BAUDRATE_TABLE       \
 181         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 182
 183 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 184 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 185 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 186 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 187
 188 /* I2C */
 189 #define CONFIG_SYS_I2C
 190 #define CONFIG_SYS_I2C_FSL
 191 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 192 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 193 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 194 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 195
 196 /*
 197  * General PCI
 198  * Memory space is mapped 1-1, but I/O space must start from 0.
 199  */
 200
 201 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 202 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 203 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 204 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 205 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 206 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 207 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 208 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 209 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 210
 211 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 212 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 213 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 214 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 215 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 216 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 217 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 218 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 219 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 220
 221 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 222 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 223 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 224 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 225 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 226 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 227 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 228 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 229 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 230
 231 /* controller 4, Base address 203000 */
 232 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 233 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 234 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 235 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 236 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 237 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 238
 239 #ifdef CONFIG_PCI
 240 #define CONFIG_PCI_INDIRECT_BRIDGE
 241
 242 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 243 #define CONFIG_DOS_PARTITION
 244 #endif  /* CONFIG_PCI */
 245
 246 /* SATA */
 247 #ifdef CONFIG_FSL_SATA_V2
 248 #define CONFIG_LIBATA
 249 #define CONFIG_FSL_SATA
 250
 251 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 252 #define CONFIG_SATA1
 253 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 254 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 255 #define CONFIG_SATA2
 256 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 257 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 258
 259 #define CONFIG_LBA48
 260 #define CONFIG_CMD_SATA
 261 #define CONFIG_DOS_PARTITION
 262 #endif
 263
 264 #ifdef CONFIG_FMAN_ENET
 265 #define CONFIG_MII              /* MII PHY management */
 266 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 267 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 268 #endif
 269
 270 /*
 271  * Environment
 272  */
 273 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 274 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 275
 276 /*
 277  * Command line configuration.
 278  */
 279 #define CONFIG_CMD_ERRATA
 280 #define CONFIG_CMD_IRQ
 281
 282 #ifdef CONFIG_PCI
 283 #define CONFIG_CMD_PCI
 284 #endif
 285
 286 /*
 287  * Miscellaneous configurable options
 288  */
 289 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 290 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 291 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 292 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 293 #ifdef CONFIG_CMD_KGDB
 294 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 295 #else
 296 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 297 #endif
 298 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 299 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 300 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 301
 302 /*
 303  * For booting Linux, the board info and command line data
 304  * have to be in the first 64 MB of memory, since this is
 305  * the maximum mapped by the Linux kernel during initialization.
 306  */
 307 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 308 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 309
 310 #ifdef CONFIG_CMD_KGDB
 311 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 312 #endif
 313
 314 /*
 315  * Environment Configuration
 316  */
 317 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 318 #define CONFIG_BOOTFILE         "uImage"
 319 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 320
 321 /* default location for tftp and bootm */
 322 #define CONFIG_LOADADDR         1000000
 323
 324 #define CONFIG_BAUDRATE 115200
 325
 326 #define CONFIG_HVBOOT                                   \
 327         "setenv bootargs config-addr=0x60000000; "      \
 328         "bootm 0x01000000 - 0x00f00000"
 329
 330 #ifdef CONFIG_SYS_NO_FLASH
 331 #ifndef CONFIG_RAMBOOT_PBL
 332 #define CONFIG_ENV_IS_NOWHERE
 333 #endif
 334 #else
 335 #define CONFIG_FLASH_CFI_DRIVER
 336 #define CONFIG_SYS_FLASH_CFI
 337 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 338 #endif
 339
 340 #if defined(CONFIG_SPIFLASH)
 341 #define CONFIG_SYS_EXTRA_ENV_RELOC
 342 #define CONFIG_ENV_IS_IN_SPI_FLASH
 343 #define CONFIG_ENV_SPI_BUS              0
 344 #define CONFIG_ENV_SPI_CS               0
 345 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 346 #define CONFIG_ENV_SPI_MODE             0
 347 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 348 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 349 #define CONFIG_ENV_SECT_SIZE            0x10000
 350 #elif defined(CONFIG_SDCARD)
 351 #define CONFIG_SYS_EXTRA_ENV_RELOC
 352 #define CONFIG_ENV_IS_IN_MMC
 353 #define CONFIG_SYS_MMC_ENV_DEV          0
 354 #define CONFIG_ENV_SIZE                 0x2000
 355 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 356 #elif defined(CONFIG_NAND)
 357 #define CONFIG_SYS_EXTRA_ENV_RELOC
 358 #define CONFIG_ENV_IS_IN_NAND
 359 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 360 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 361 #elif defined(CONFIG_ENV_IS_NOWHERE)
 362 #define CONFIG_ENV_SIZE         0x2000
 363 #else
 364 #define CONFIG_ENV_IS_IN_FLASH
 365 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 366 #define CONFIG_ENV_SIZE         0x2000
 367 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 368 #endif
 369
 370 #define CONFIG_SYS_CLK_FREQ     66666666
 371 #define CONFIG_DDR_CLK_FREQ     133333333
 372
 373 #ifndef __ASSEMBLY__
 374 unsigned long get_board_sys_clk(void);
 375 unsigned long get_board_ddr_clk(void);
 376 #endif
 377
 378 /*
 379  * DDR Setup
 380  */
 381 #define CONFIG_SYS_SPD_BUS_NUM  0
 382 #define SPD_EEPROM_ADDRESS1     0x52
 383 #define SPD_EEPROM_ADDRESS2     0x54
 384 #define SPD_EEPROM_ADDRESS3     0x56
 385 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 386 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 387
 388 /*
 389  * IFC Definitions
 390  */
 391 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 392 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 393                                 + 0x8000000) | \
 394                                 CSPR_PORT_SIZE_16 | \
 395                                 CSPR_MSEL_NOR | \
 396                                 CSPR_V)
 397 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 398 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 399                                 CSPR_PORT_SIZE_16 | \
 400                                 CSPR_MSEL_NOR | \
 401                                 CSPR_V)
 402 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 403 /* NOR Flash Timing Params */
 404 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 405
 406 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 407                                 FTIM0_NOR_TEADC(0x5) | \
 408                                 FTIM0_NOR_TEAHC(0x5))
 409 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 410                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 411                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 412 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 413                                 FTIM2_NOR_TCH(0x4) | \
 414                                 FTIM2_NOR_TWPH(0x0E) | \
 415                                 FTIM2_NOR_TWP(0x1c))
 416 #define CONFIG_SYS_NOR_FTIM3    0x0
 417
 418 #define CONFIG_SYS_FLASH_QUIET_TEST
 419 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 420
 421 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 422 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 423 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 424 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 425
 426 #define CONFIG_SYS_FLASH_EMPTY_INFO
 427 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 428                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 429
 430 /* NAND Flash on IFC */
 431 #define CONFIG_NAND_FSL_IFC
 432 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 433 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 434 #define CONFIG_SYS_NAND_BASE            0xff800000
 435 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 436
 437 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 438 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 439                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 440                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 441                                 | CSPR_V)
 442 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 443
 444 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 445                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 446                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 447                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 448                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 449                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 450                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 451
 452 #define CONFIG_SYS_NAND_ONFI_DETECTION
 453
 454 /* ONFI NAND Flash mode0 Timing Params */
 455 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 456                                         FTIM0_NAND_TWP(0x18)   | \
 457                                         FTIM0_NAND_TWCHT(0x07) | \
 458                                         FTIM0_NAND_TWH(0x0a))
 459 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 460                                         FTIM1_NAND_TWBE(0x39)  | \
 461                                         FTIM1_NAND_TRR(0x0e)   | \
 462                                         FTIM1_NAND_TRP(0x18))
 463 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 464                                         FTIM2_NAND_TREH(0x0a) | \
 465                                         FTIM2_NAND_TWHRE(0x1e))
 466 #define CONFIG_SYS_NAND_FTIM3           0x0
 467
 468 #define CONFIG_SYS_NAND_DDR_LAW         11
 469 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 470 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 471 #define CONFIG_CMD_NAND
 472
 473 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 474
 475 #if defined(CONFIG_NAND)
 476 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 477 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 478 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 479 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 480 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 481 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 482 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 483 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 484 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 485 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 486 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 487 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 488 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 489 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 490 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 491 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 492 #else
 493 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 494 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 495 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 496 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 497 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 498 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 499 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 500 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 501 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 502 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 503 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 504 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 505 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 506 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 507 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 508 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 509 #endif
 510 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 511 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 512 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 513 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 514 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 515 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 516 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 517 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 518
 519 /* CPLD on IFC */
 520 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 521 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 522 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 523 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 524                                 | CSPR_PORT_SIZE_8 \
 525                                 | CSPR_MSEL_GPCM \
 526                                 | CSPR_V)
 527
 528 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 529 #define CONFIG_SYS_CSOR3        0x0
 530
 531 /* CPLD Timing parameters for IFC CS3 */
 532 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 533                                         FTIM0_GPCM_TEADC(0x0e) | \
 534                                         FTIM0_GPCM_TEAHC(0x0e))
 535 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 536                                         FTIM1_GPCM_TRAD(0x1f))
 537 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 538                                         FTIM2_GPCM_TCH(0x8) | \
 539                                         FTIM2_GPCM_TWP(0x1f))
 540 #define CONFIG_SYS_CS3_FTIM3            0x0
 541
 542 #if defined(CONFIG_RAMBOOT_PBL)
 543 #define CONFIG_SYS_RAMBOOT
 544 #endif
 545
 546 /* I2C */
 547 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 548 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 549 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 550 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 551
 552 #define I2C_MUX_CH_DEFAULT      0x8
 553 #define I2C_MUX_CH_VOL_MONITOR  0xa
 554 #define I2C_MUX_CH_VSC3316_FS   0xc
 555 #define I2C_MUX_CH_VSC3316_BS   0xd
 556
 557 /* Voltage monitor on channel 2*/
 558 #define I2C_VOL_MONITOR_ADDR            0x40
 559 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 560 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 561 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 562
 563 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
 564 #ifndef CONFIG_SPL_BUILD
 565 #define CONFIG_VID
 566 #endif
 567 #define CONFIG_VOL_MONITOR_IR36021_SET
 568 #define CONFIG_VOL_MONITOR_IR36021_READ
 569 /* The lowest and highest voltage allowed for T4240RDB */
 570 #define VDD_MV_MIN                      819
 571 #define VDD_MV_MAX                      1212
 572
 573 /*
 574  * eSPI - Enhanced SPI
 575  */
 576 #define CONFIG_SF_DEFAULT_SPEED         10000000
 577 #define CONFIG_SF_DEFAULT_MODE          0
 578
 579 /* Qman/Bman */
 580 #ifndef CONFIG_NOBQFMAN
 581 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 582 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 583 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 584 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 585 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 586 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 587 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 588 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 589 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 590 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 591                                         CONFIG_SYS_BMAN_CENA_SIZE)
 592 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 593 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 594 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 595 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 596 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 597 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 598 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 599 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 600 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 601 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 602 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 603                                         CONFIG_SYS_QMAN_CENA_SIZE)
 604 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 605 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 606
 607 #define CONFIG_SYS_DPAA_FMAN
 608 #define CONFIG_SYS_DPAA_PME
 609 #define CONFIG_SYS_PMAN
 610 #define CONFIG_SYS_DPAA_DCE
 611 #define CONFIG_SYS_DPAA_RMAN
 612 #define CONFIG_SYS_INTERLAKEN
 613
 614 /* Default address of microcode for the Linux Fman driver */
 615 #if defined(CONFIG_SPIFLASH)
 616 /*
 617  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 618  * env, so we got 0x110000.
 619  */
 620 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 621 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 622 #elif defined(CONFIG_SDCARD)
 623 /*
 624  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 625  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 626  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 627  */
 628 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 629 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 630 #elif defined(CONFIG_NAND)
 631 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 632 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 633 #else
 634 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 635 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 636 #endif
 637 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 638 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 639 #endif /* CONFIG_NOBQFMAN */
 640
 641 #ifdef CONFIG_SYS_DPAA_FMAN
 642 #define CONFIG_FMAN_ENET
 643 #define CONFIG_PHYLIB_10G
 644 #define CONFIG_PHY_VITESSE
 645 #define CONFIG_PHY_CORTINA
 646 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 647 #define CONFIG_CORTINA_FW_ADDR          0xefe00000
 648 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 649 #define CONFIG_PHY_TERANETICS
 650 #define SGMII_PHY_ADDR1 0x0
 651 #define SGMII_PHY_ADDR2 0x1
 652 #define SGMII_PHY_ADDR3 0x2
 653 #define SGMII_PHY_ADDR4 0x3
 654 #define SGMII_PHY_ADDR5 0x4
 655 #define SGMII_PHY_ADDR6 0x5
 656 #define SGMII_PHY_ADDR7 0x6
 657 #define SGMII_PHY_ADDR8 0x7
 658 #define FM1_10GEC1_PHY_ADDR     0x10
 659 #define FM1_10GEC2_PHY_ADDR     0x11
 660 #define FM2_10GEC1_PHY_ADDR     0x12
 661 #define FM2_10GEC2_PHY_ADDR     0x13
 662 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 663 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 664 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 665 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 666 #endif
 667
 668 /* SATA */
 669 #ifdef CONFIG_FSL_SATA_V2
 670 #define CONFIG_LIBATA
 671 #define CONFIG_FSL_SATA
 672
 673 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 674 #define CONFIG_SATA1
 675 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 676 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 677 #define CONFIG_SATA2
 678 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 679 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 680
 681 #define CONFIG_LBA48
 682 #define CONFIG_CMD_SATA
 683 #define CONFIG_DOS_PARTITION
 684 #endif
 685
 686 #ifdef CONFIG_FMAN_ENET
 687 #define CONFIG_MII              /* MII PHY management */
 688 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 689 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 690 #endif
 691
 692 /*
 693 * USB
 694 */
 695 #define CONFIG_USB_EHCI
 696 #define CONFIG_USB_EHCI_FSL
 697 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 698 #define CONFIG_HAS_FSL_DR_USB
 699
 700 #ifdef CONFIG_MMC
 701 #define CONFIG_FSL_ESDHC
 702 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 703 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 704 #define CONFIG_GENERIC_MMC
 705 #define CONFIG_DOS_PARTITION
 706 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 707 #endif
 708
 709 /* Hash command with SHA acceleration supported in hardware */
 710 #ifdef CONFIG_FSL_CAAM
 711 #define CONFIG_CMD_HASH
 712 #define CONFIG_SHA_HW_ACCEL
 713 #endif
 714
 715
 716 #define __USB_PHY_TYPE  utmi
 717
 718 /*
 719  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 720  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 721  * interleaving. It can be cacheline, page, bank, superbank.
 722  * See doc/README.fsl-ddr for details.
 723  */
 724 #ifdef CONFIG_ARCH_T4240
 725 #define CTRL_INTLV_PREFERED 3way_4KB
 726 #else
 727 #define CTRL_INTLV_PREFERED cacheline
 728 #endif
 729
 730 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 731         "hwconfig=fsl_ddr:"                                     \
 732         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 733         "bank_intlv=auto;"                                      \
 734         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 735         "netdev=eth0\0"                                         \
 736         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 737         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 738         "tftpflash=tftpboot $loadaddr $uboot && "               \
 739         "protect off $ubootaddr +$filesize && "                 \
 740         "erase $ubootaddr +$filesize && "                       \
 741         "cp.b $loadaddr $ubootaddr $filesize && "               \
 742         "protect on $ubootaddr +$filesize && "                  \
 743         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 744         "consoledev=ttyS0\0"                                    \
 745         "ramdiskaddr=2000000\0"                                 \
 746         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 747         "fdtaddr=1e00000\0"                                     \
 748         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 749         "bdev=sda3\0"
 750
 751 #define CONFIG_HVBOOT                                   \
 752         "setenv bootargs config-addr=0x60000000; "      \
 753         "bootm 0x01000000 - 0x00f00000"
 754
 755 #define CONFIG_LINUX                                    \
 756         "setenv bootargs root=/dev/ram rw "             \
 757         "console=$consoledev,$baudrate $othbootargs;"   \
 758         "setenv ramdiskaddr 0x02000000;"                \
 759         "setenv fdtaddr 0x00c00000;"                    \
 760         "setenv loadaddr 0x1000000;"                    \
 761         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 762
 763 #define CONFIG_HDBOOT                                   \
 764         "setenv bootargs root=/dev/$bdev rw "           \
 765         "console=$consoledev,$baudrate $othbootargs;"   \
 766         "tftp $loadaddr $bootfile;"                     \
 767         "tftp $fdtaddr $fdtfile;"                       \
 768         "bootm $loadaddr - $fdtaddr"
 769
 770 #define CONFIG_NFSBOOTCOMMAND                   \
 771         "setenv bootargs root=/dev/nfs rw "     \
 772         "nfsroot=$serverip:$rootpath "          \
 773         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 774         "console=$consoledev,$baudrate $othbootargs;"   \
 775         "tftp $loadaddr $bootfile;"             \
 776         "tftp $fdtaddr $fdtfile;"               \
 777         "bootm $loadaddr - $fdtaddr"
 778
 779 #define CONFIG_RAMBOOTCOMMAND                           \
 780         "setenv bootargs root=/dev/ram rw "             \
 781         "console=$consoledev,$baudrate $othbootargs;"   \
 782         "tftp $ramdiskaddr $ramdiskfile;"               \
 783         "tftp $loadaddr $bootfile;"                     \
 784         "tftp $fdtaddr $fdtfile;"                       \
 785         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 786
 787 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 788
 789 #include <asm/fsl_secure_boot.h>
 790
 791 #endif  /* __CONFIG_H */