1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T4240 RDB board configuration file
13 #include <linux/stringify.h>
15 #define CONFIG_FSL_SATA_V2
18 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
20 #ifdef CONFIG_RAMBOOT_PBL
22 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
23 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
25 #define RESET_VECTOR_OFFSET 0x27FFC
26 #define BOOT_PAGE_OFFSET 0x27000
29 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
30 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
31 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
32 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
33 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
34 #ifndef CONFIG_SPL_BUILD
35 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
39 #ifdef CONFIG_SPL_BUILD
40 #define CONFIG_SPL_COMMON_INIT_DDR
41 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
45 #endif /* CONFIG_RAMBOOT_PBL */
47 /* High Level Configuration Options */
48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
50 #ifndef CONFIG_RESET_VECTOR_ADDRESS
51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
55 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
56 #define CONFIG_PCIE1 /* PCIE controller 1 */
57 #define CONFIG_PCIE2 /* PCIE controller 2 */
58 #define CONFIG_PCIE3 /* PCIE controller 3 */
61 * These can be toggled for performance analysis, otherwise use default.
63 #define CONFIG_SYS_CACHE_STASHING
65 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
68 #define CONFIG_ENABLE_36BIT_PHYS
71 * Config the L3 Cache as L3 SRAM
73 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
74 #define CONFIG_SYS_L3_SIZE (512 << 10)
75 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
76 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
77 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
78 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
79 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
81 #define CONFIG_SYS_DCSRBAR 0xf0000000
82 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
87 #define CONFIG_VERY_BIG_RAM
88 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
89 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
94 #define CONFIG_SYS_FLASH_BASE 0xe0000000
95 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
97 #define CONFIG_HWCONFIG
99 /* define to use L1 as initial stack */
100 #define CONFIG_L1_INIT_RAM
101 #define CONFIG_SYS_INIT_RAM_LOCK
102 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
103 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
104 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
105 /* The assembler doesn't like typecast */
106 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
107 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
108 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
109 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
111 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
112 GENERATED_GBL_DATA_SIZE)
113 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
115 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
117 /* Serial Port - controlled on board with jumper J8
121 #define CONFIG_SYS_NS16550_SERIAL
122 #define CONFIG_SYS_NS16550_REG_SIZE 1
123 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
125 #define CONFIG_SYS_BAUDRATE_TABLE \
126 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
128 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
129 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
130 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
131 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
137 * Memory space is mapped 1-1, but I/O space must start from 0.
140 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
141 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
142 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
143 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
144 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
146 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
147 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
148 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
149 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
150 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
152 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
153 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
154 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
155 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
156 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
158 /* controller 4, Base address 203000 */
159 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
160 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
161 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
164 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
165 #endif /* CONFIG_PCI */
168 #ifdef CONFIG_FSL_SATA_V2
170 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
171 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
173 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
174 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
182 #define CONFIG_LOADS_ECHO /* echo on for serial download */
183 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
186 * Miscellaneous configurable options
190 * For booting Linux, the board info and command line data
191 * have to be in the first 64 MB of memory, since this is
192 * the maximum mapped by the Linux kernel during initialization.
194 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
195 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
198 * Environment Configuration
200 #define CONFIG_ROOTPATH "/opt/nfsroot"
201 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
204 "setenv bootargs config-addr=0x60000000; " \
205 "bootm 0x01000000 - 0x00f00000"
210 #define CONFIG_SYS_SPD_BUS_NUM 0
211 #define SPD_EEPROM_ADDRESS1 0x52
212 #define SPD_EEPROM_ADDRESS2 0x54
213 #define SPD_EEPROM_ADDRESS3 0x56
214 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
215 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
220 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
221 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
223 CSPR_PORT_SIZE_16 | \
226 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
227 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
228 CSPR_PORT_SIZE_16 | \
231 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
232 /* NOR Flash Timing Params */
233 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
235 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
236 FTIM0_NOR_TEADC(0x5) | \
237 FTIM0_NOR_TEAHC(0x5))
238 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
239 FTIM1_NOR_TRAD_NOR(0x1A) |\
240 FTIM1_NOR_TSEQRAD_NOR(0x13))
241 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
242 FTIM2_NOR_TCH(0x4) | \
243 FTIM2_NOR_TWPH(0x0E) | \
245 #define CONFIG_SYS_NOR_FTIM3 0x0
247 #define CONFIG_SYS_FLASH_QUIET_TEST
248 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
250 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
251 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
252 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
254 #define CONFIG_SYS_FLASH_EMPTY_INFO
255 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
256 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
258 /* NAND Flash on IFC */
259 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
260 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
261 #define CONFIG_SYS_NAND_BASE 0xff800000
262 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
264 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
265 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
266 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
267 | CSPR_MSEL_NAND /* MSEL = NAND */ \
269 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
271 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
272 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
273 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
274 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
275 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
276 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
277 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
279 /* ONFI NAND Flash mode0 Timing Params */
280 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
281 FTIM0_NAND_TWP(0x18) | \
282 FTIM0_NAND_TWCHT(0x07) | \
283 FTIM0_NAND_TWH(0x0a))
284 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
285 FTIM1_NAND_TWBE(0x39) | \
286 FTIM1_NAND_TRR(0x0e) | \
287 FTIM1_NAND_TRP(0x18))
288 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
289 FTIM2_NAND_TREH(0x0a) | \
290 FTIM2_NAND_TWHRE(0x1e))
291 #define CONFIG_SYS_NAND_FTIM3 0x0
293 #define CONFIG_SYS_NAND_DDR_LAW 11
294 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
295 #define CONFIG_SYS_MAX_NAND_DEVICE 1
297 #if defined(CONFIG_MTD_RAW_NAND)
298 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
299 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
300 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
301 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
302 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
303 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
304 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
305 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
306 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
307 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
308 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
309 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
310 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
311 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
312 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
313 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
315 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
316 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
317 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
318 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
319 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
320 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
321 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
322 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
323 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
324 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
325 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
326 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
327 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
328 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
329 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
330 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
332 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
333 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
334 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
335 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
336 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
337 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
338 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
339 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
342 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
343 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
344 #define CONFIG_SYS_CSPR3_EXT (0xf)
345 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
350 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
351 #define CONFIG_SYS_CSOR3 0x0
353 /* CPLD Timing parameters for IFC CS3 */
354 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
355 FTIM0_GPCM_TEADC(0x0e) | \
356 FTIM0_GPCM_TEAHC(0x0e))
357 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
358 FTIM1_GPCM_TRAD(0x1f))
359 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
360 FTIM2_GPCM_TCH(0x8) | \
361 FTIM2_GPCM_TWP(0x1f))
362 #define CONFIG_SYS_CS3_FTIM3 0x0
364 #if defined(CONFIG_RAMBOOT_PBL)
365 #define CONFIG_SYS_RAMBOOT
369 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
370 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
372 #define I2C_MUX_CH_DEFAULT 0x8
373 #define I2C_MUX_CH_VOL_MONITOR 0xa
374 #define I2C_MUX_CH_VSC3316_FS 0xc
375 #define I2C_MUX_CH_VSC3316_BS 0xd
377 /* Voltage monitor on channel 2*/
378 #define I2C_VOL_MONITOR_ADDR 0x40
379 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
380 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
381 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
383 /* The lowest and highest voltage allowed for T4240RDB */
384 #define VDD_MV_MIN 819
385 #define VDD_MV_MAX 1212
388 * eSPI - Enhanced SPI
392 #ifndef CONFIG_NOBQFMAN
393 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
394 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
395 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
396 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
397 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
398 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
399 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
400 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
401 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
402 CONFIG_SYS_BMAN_CENA_SIZE)
403 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
404 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
405 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
406 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
407 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
408 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
409 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
410 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
411 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
412 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
413 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
414 CONFIG_SYS_QMAN_CENA_SIZE)
415 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
416 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
418 #define CONFIG_SYS_DPAA_FMAN
419 #define CONFIG_SYS_DPAA_PME
420 #define CONFIG_SYS_PMAN
421 #define CONFIG_SYS_DPAA_DCE
422 #define CONFIG_SYS_DPAA_RMAN
423 #define CONFIG_SYS_INTERLAKEN
425 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
426 #endif /* CONFIG_NOBQFMAN */
428 #ifdef CONFIG_SYS_DPAA_FMAN
429 #define SGMII_PHY_ADDR1 0x0
430 #define SGMII_PHY_ADDR2 0x1
431 #define SGMII_PHY_ADDR3 0x2
432 #define SGMII_PHY_ADDR4 0x3
433 #define SGMII_PHY_ADDR5 0x4
434 #define SGMII_PHY_ADDR6 0x5
435 #define SGMII_PHY_ADDR7 0x6
436 #define SGMII_PHY_ADDR8 0x7
437 #define FM1_10GEC1_PHY_ADDR 0x10
438 #define FM1_10GEC2_PHY_ADDR 0x11
439 #define FM2_10GEC1_PHY_ADDR 0x12
440 #define FM2_10GEC2_PHY_ADDR 0x13
441 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
442 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
443 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
444 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
448 #ifdef CONFIG_FSL_SATA_V2
450 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
451 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
453 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
454 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
462 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
463 #define CONFIG_HAS_FSL_DR_USB
466 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
467 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
471 #define __USB_PHY_TYPE utmi
474 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
475 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
476 * interleaving. It can be cacheline, page, bank, superbank.
477 * See doc/README.fsl-ddr for details.
479 #ifdef CONFIG_ARCH_T4240
480 #define CTRL_INTLV_PREFERED 3way_4KB
482 #define CTRL_INTLV_PREFERED cacheline
485 #define CONFIG_EXTRA_ENV_SETTINGS \
486 "hwconfig=fsl_ddr:" \
487 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
489 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
491 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
492 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
493 "tftpflash=tftpboot $loadaddr $uboot && " \
494 "protect off $ubootaddr +$filesize && " \
495 "erase $ubootaddr +$filesize && " \
496 "cp.b $loadaddr $ubootaddr $filesize && " \
497 "protect on $ubootaddr +$filesize && " \
498 "cmp.b $loadaddr $ubootaddr $filesize\0" \
499 "consoledev=ttyS0\0" \
500 "ramdiskaddr=2000000\0" \
501 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
502 "fdtaddr=1e00000\0" \
503 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
507 "setenv bootargs config-addr=0x60000000; " \
508 "bootm 0x01000000 - 0x00f00000"
510 #include <asm/fsl_secure_boot.h>
512 #endif /* __CONFIG_H */