include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T4240 RDB board configuration file
   8  */
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_FSL_SATA_V2
  13 #define CONFIG_PCIE4
  14
  15 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  19 #ifndef CONFIG_SDCARD
  20 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  21 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  22 #else
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_PAD_TO               0x40000
  25 #define CONFIG_SPL_MAX_SIZE             0x28000
  26 #define RESET_VECTOR_OFFSET             0x27FFC
  27 #define BOOT_PAGE_OFFSET                0x27000
  28
  29 #ifdef  CONFIG_SDCARD
  30 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  31 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  32 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  33 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  34 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  35 #ifndef CONFIG_SPL_BUILD
  36 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  37 #endif
  38 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  39 #endif
  40
  41 #ifdef CONFIG_SPL_BUILD
  42 #define CONFIG_SPL_SKIP_RELOCATE
  43 #define CONFIG_SPL_COMMON_INIT_DDR
  44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  45 #endif
  46
  47 #endif
  48 #endif /* CONFIG_RAMBOOT_PBL */
  49
  50 #define CONFIG_DDR_ECC
  51
  52 /* High Level Configuration Options */
  53 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  54
  55 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  56 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  57 #endif
  58
  59 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  60 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  61 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  62 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  63 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  64 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  65 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  66
  67 #define CONFIG_ENV_OVERWRITE
  68
  69 /*
  70  * These can be toggled for performance analysis, otherwise use default.
  71  */
  72 #define CONFIG_SYS_CACHE_STASHING
  73 #define CONFIG_BTB                      /* toggle branch predition */
  74 #ifdef CONFIG_DDR_ECC
  75 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  76 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  77 #endif
  78
  79 #define CONFIG_ENABLE_36BIT_PHYS
  80
  81 #define CONFIG_ADDR_MAP
  82 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  83
  84 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  85 #define CONFIG_SYS_MEMTEST_END          0x00400000
  86
  87 /*
  88  *  Config the L3 Cache as L3 SRAM
  89  */
  90 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  91 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  92 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  93 #ifdef CONFIG_RAMBOOT_PBL
  94 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
  95 #endif
  96 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
  97 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
  98 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
  99
 100 #define CONFIG_SYS_DCSRBAR              0xf0000000
 101 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 102
 103 /*
 104  * DDR Setup
 105  */
 106 #define CONFIG_VERY_BIG_RAM
 107 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 108 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 109
 110 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 111 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 112
 113 #define CONFIG_DDR_SPD
 114
 115 /*
 116  * IFC Definitions
 117  */
 118 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 119 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 120
 121 #ifdef CONFIG_SPL_BUILD
 122 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 123 #else
 124 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 125 #endif
 126
 127 #define CONFIG_HWCONFIG
 128
 129 /* define to use L1 as initial stack */
 130 #define CONFIG_L1_INIT_RAM
 131 #define CONFIG_SYS_INIT_RAM_LOCK
 132 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 133 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 134 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 135 /* The assembler doesn't like typecast */
 136 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 137         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 138           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 139 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 140
 141 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 142                                         GENERATED_GBL_DATA_SIZE)
 143 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 144
 145 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 146 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 147
 148 /* Serial Port - controlled on board with jumper J8
 149  * open - index 2
 150  * shorted - index 1
 151  */
 152 #define CONFIG_SYS_NS16550_SERIAL
 153 #define CONFIG_SYS_NS16550_REG_SIZE     1
 154 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 155
 156 #define CONFIG_SYS_BAUDRATE_TABLE       \
 157         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 158
 159 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 160 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 161 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 162 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 163
 164 /* I2C */
 165 #define CONFIG_SYS_I2C
 166 #define CONFIG_SYS_I2C_FSL
 167 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 168 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 169 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 170 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 171
 172 /*
 173  * General PCI
 174  * Memory space is mapped 1-1, but I/O space must start from 0.
 175  */
 176
 177 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 178 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 179 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 180 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 181 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 182 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 183 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 184 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 185 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 186
 187 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 188 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 189 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 190 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 191 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 192 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 193 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 194 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 195 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 196
 197 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 198 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 199 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 200 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 201 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 202 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 203 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 204 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 205 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 206
 207 /* controller 4, Base address 203000 */
 208 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 209 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 210 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 211 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 212 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 213 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 214
 215 #ifdef CONFIG_PCI
 216 #define CONFIG_PCI_INDIRECT_BRIDGE
 217
 218 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 219 #endif  /* CONFIG_PCI */
 220
 221 /* SATA */
 222 #ifdef CONFIG_FSL_SATA_V2
 223 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 224 #define CONFIG_SATA1
 225 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 226 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 227 #define CONFIG_SATA2
 228 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 229 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 230
 231 #define CONFIG_LBA48
 232 #endif
 233
 234 #ifdef CONFIG_FMAN_ENET
 235 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 236 #endif
 237
 238 /*
 239  * Environment
 240  */
 241 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 242 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 243
 244 /*
 245  * Command line configuration.
 246  */
 247
 248 /*
 249  * Miscellaneous configurable options
 250  */
 251 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 252
 253 /*
 254  * For booting Linux, the board info and command line data
 255  * have to be in the first 64 MB of memory, since this is
 256  * the maximum mapped by the Linux kernel during initialization.
 257  */
 258 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 259 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 260
 261 #ifdef CONFIG_CMD_KGDB
 262 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 263 #endif
 264
 265 /*
 266  * Environment Configuration
 267  */
 268 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 269 #define CONFIG_BOOTFILE         "uImage"
 270 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 271
 272 /* default location for tftp and bootm */
 273 #define CONFIG_LOADADDR         1000000
 274
 275 #define CONFIG_HVBOOT                                   \
 276         "setenv bootargs config-addr=0x60000000; "      \
 277         "bootm 0x01000000 - 0x00f00000"
 278
 279 #if defined(CONFIG_SPIFLASH)
 280 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 281 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 282 #define CONFIG_ENV_SECT_SIZE            0x10000
 283 #elif defined(CONFIG_SDCARD)
 284 #define CONFIG_SYS_MMC_ENV_DEV          0
 285 #define CONFIG_ENV_SIZE                 0x2000
 286 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 287 #elif defined(CONFIG_NAND)
 288 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 289 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 290 #elif defined(CONFIG_ENV_IS_NOWHERE)
 291 #define CONFIG_ENV_SIZE         0x2000
 292 #else
 293 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 294 #define CONFIG_ENV_SIZE         0x2000
 295 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 296 #endif
 297
 298 #define CONFIG_SYS_CLK_FREQ     66666666
 299 #define CONFIG_DDR_CLK_FREQ     133333333
 300
 301 #ifndef __ASSEMBLY__
 302 unsigned long get_board_sys_clk(void);
 303 unsigned long get_board_ddr_clk(void);
 304 #endif
 305
 306 /*
 307  * DDR Setup
 308  */
 309 #define CONFIG_SYS_SPD_BUS_NUM  0
 310 #define SPD_EEPROM_ADDRESS1     0x52
 311 #define SPD_EEPROM_ADDRESS2     0x54
 312 #define SPD_EEPROM_ADDRESS3     0x56
 313 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 314 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 315
 316 /*
 317  * IFC Definitions
 318  */
 319 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 320 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 321                                 + 0x8000000) | \
 322                                 CSPR_PORT_SIZE_16 | \
 323                                 CSPR_MSEL_NOR | \
 324                                 CSPR_V)
 325 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 326 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 327                                 CSPR_PORT_SIZE_16 | \
 328                                 CSPR_MSEL_NOR | \
 329                                 CSPR_V)
 330 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 331 /* NOR Flash Timing Params */
 332 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 333
 334 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 335                                 FTIM0_NOR_TEADC(0x5) | \
 336                                 FTIM0_NOR_TEAHC(0x5))
 337 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 338                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 339                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 340 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 341                                 FTIM2_NOR_TCH(0x4) | \
 342                                 FTIM2_NOR_TWPH(0x0E) | \
 343                                 FTIM2_NOR_TWP(0x1c))
 344 #define CONFIG_SYS_NOR_FTIM3    0x0
 345
 346 #define CONFIG_SYS_FLASH_QUIET_TEST
 347 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 348
 349 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 350 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 351 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 352 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 353
 354 #define CONFIG_SYS_FLASH_EMPTY_INFO
 355 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 356                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 357
 358 /* NAND Flash on IFC */
 359 #define CONFIG_NAND_FSL_IFC
 360 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 361 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 362 #define CONFIG_SYS_NAND_BASE            0xff800000
 363 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 364
 365 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 366 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 367                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 368                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 369                                 | CSPR_V)
 370 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 371
 372 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 373                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 374                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 375                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 376                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 377                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 378                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 379
 380 #define CONFIG_SYS_NAND_ONFI_DETECTION
 381
 382 /* ONFI NAND Flash mode0 Timing Params */
 383 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 384                                         FTIM0_NAND_TWP(0x18)   | \
 385                                         FTIM0_NAND_TWCHT(0x07) | \
 386                                         FTIM0_NAND_TWH(0x0a))
 387 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 388                                         FTIM1_NAND_TWBE(0x39)  | \
 389                                         FTIM1_NAND_TRR(0x0e)   | \
 390                                         FTIM1_NAND_TRP(0x18))
 391 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 392                                         FTIM2_NAND_TREH(0x0a) | \
 393                                         FTIM2_NAND_TWHRE(0x1e))
 394 #define CONFIG_SYS_NAND_FTIM3           0x0
 395
 396 #define CONFIG_SYS_NAND_DDR_LAW         11
 397 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 398 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 399
 400 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 401
 402 #if defined(CONFIG_NAND)
 403 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 404 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 405 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 406 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 407 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 408 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 409 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 410 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 411 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 412 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 413 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 414 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 415 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 416 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 417 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 418 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 419 #else
 420 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 421 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 422 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 423 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 424 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 425 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 426 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 427 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 428 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 429 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 430 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 431 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 432 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 433 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 434 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 435 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 436 #endif
 437 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 438 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 439 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 440 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 441 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 442 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 443 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 444 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 445
 446 /* CPLD on IFC */
 447 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 448 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 449 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 450 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 451                                 | CSPR_PORT_SIZE_8 \
 452                                 | CSPR_MSEL_GPCM \
 453                                 | CSPR_V)
 454
 455 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 456 #define CONFIG_SYS_CSOR3        0x0
 457
 458 /* CPLD Timing parameters for IFC CS3 */
 459 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 460                                         FTIM0_GPCM_TEADC(0x0e) | \
 461                                         FTIM0_GPCM_TEAHC(0x0e))
 462 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 463                                         FTIM1_GPCM_TRAD(0x1f))
 464 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 465                                         FTIM2_GPCM_TCH(0x8) | \
 466                                         FTIM2_GPCM_TWP(0x1f))
 467 #define CONFIG_SYS_CS3_FTIM3            0x0
 468
 469 #if defined(CONFIG_RAMBOOT_PBL)
 470 #define CONFIG_SYS_RAMBOOT
 471 #endif
 472
 473 /* I2C */
 474 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 475 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 476 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 477 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 478
 479 #define I2C_MUX_CH_DEFAULT      0x8
 480 #define I2C_MUX_CH_VOL_MONITOR  0xa
 481 #define I2C_MUX_CH_VSC3316_FS   0xc
 482 #define I2C_MUX_CH_VSC3316_BS   0xd
 483
 484 /* Voltage monitor on channel 2*/
 485 #define I2C_VOL_MONITOR_ADDR            0x40
 486 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 487 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 488 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 489
 490 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
 491 #ifndef CONFIG_SPL_BUILD
 492 #define CONFIG_VID
 493 #endif
 494 #define CONFIG_VOL_MONITOR_IR36021_SET
 495 #define CONFIG_VOL_MONITOR_IR36021_READ
 496 /* The lowest and highest voltage allowed for T4240RDB */
 497 #define VDD_MV_MIN                      819
 498 #define VDD_MV_MAX                      1212
 499
 500 /*
 501  * eSPI - Enhanced SPI
 502  */
 503
 504 /* Qman/Bman */
 505 #ifndef CONFIG_NOBQFMAN
 506 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 507 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 508 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 509 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 510 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 511 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 512 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 513 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 514 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 515                                         CONFIG_SYS_BMAN_CENA_SIZE)
 516 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 517 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 518 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 519 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 520 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 521 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 522 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 523 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 524 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 525 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 526 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 527                                         CONFIG_SYS_QMAN_CENA_SIZE)
 528 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 529 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 530
 531 #define CONFIG_SYS_DPAA_FMAN
 532 #define CONFIG_SYS_DPAA_PME
 533 #define CONFIG_SYS_PMAN
 534 #define CONFIG_SYS_DPAA_DCE
 535 #define CONFIG_SYS_DPAA_RMAN
 536 #define CONFIG_SYS_INTERLAKEN
 537
 538 /* Default address of microcode for the Linux Fman driver */
 539 #if defined(CONFIG_SPIFLASH)
 540 /*
 541  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 542  * env, so we got 0x110000.
 543  */
 544 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 545 #elif defined(CONFIG_SDCARD)
 546 /*
 547  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 548  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 549  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 550  */
 551 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 552 #elif defined(CONFIG_NAND)
 553 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 554 #else
 555 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 556 #endif
 557 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 558 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 559 #endif /* CONFIG_NOBQFMAN */
 560
 561 #ifdef CONFIG_SYS_DPAA_FMAN
 562 #define CONFIG_PHYLIB_10G
 563 #define CONFIG_PHY_VITESSE
 564 #define CONFIG_PHY_CORTINA
 565 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 566 #define CONFIG_CORTINA_FW_ADDR          0xefe00000
 567 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 568 #define CONFIG_PHY_TERANETICS
 569 #define SGMII_PHY_ADDR1 0x0
 570 #define SGMII_PHY_ADDR2 0x1
 571 #define SGMII_PHY_ADDR3 0x2
 572 #define SGMII_PHY_ADDR4 0x3
 573 #define SGMII_PHY_ADDR5 0x4
 574 #define SGMII_PHY_ADDR6 0x5
 575 #define SGMII_PHY_ADDR7 0x6
 576 #define SGMII_PHY_ADDR8 0x7
 577 #define FM1_10GEC1_PHY_ADDR     0x10
 578 #define FM1_10GEC2_PHY_ADDR     0x11
 579 #define FM2_10GEC1_PHY_ADDR     0x12
 580 #define FM2_10GEC2_PHY_ADDR     0x13
 581 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 582 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 583 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 584 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 585 #endif
 586
 587 /* SATA */
 588 #ifdef CONFIG_FSL_SATA_V2
 589 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 590 #define CONFIG_SATA1
 591 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 592 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 593 #define CONFIG_SATA2
 594 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 595 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 596
 597 #define CONFIG_LBA48
 598 #endif
 599
 600 #ifdef CONFIG_FMAN_ENET
 601 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 602 #endif
 603
 604 /*
 605 * USB
 606 */
 607 #define CONFIG_USB_EHCI_FSL
 608 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 609 #define CONFIG_HAS_FSL_DR_USB
 610
 611 #ifdef CONFIG_MMC
 612 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 613 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 614 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 615 #endif
 616
 617
 618 #define __USB_PHY_TYPE  utmi
 619
 620 /*
 621  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 622  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 623  * interleaving. It can be cacheline, page, bank, superbank.
 624  * See doc/README.fsl-ddr for details.
 625  */
 626 #ifdef CONFIG_ARCH_T4240
 627 #define CTRL_INTLV_PREFERED 3way_4KB
 628 #else
 629 #define CTRL_INTLV_PREFERED cacheline
 630 #endif
 631
 632 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 633         "hwconfig=fsl_ddr:"                                     \
 634         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 635         "bank_intlv=auto;"                                      \
 636         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 637         "netdev=eth0\0"                                         \
 638         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 639         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 640         "tftpflash=tftpboot $loadaddr $uboot && "               \
 641         "protect off $ubootaddr +$filesize && "                 \
 642         "erase $ubootaddr +$filesize && "                       \
 643         "cp.b $loadaddr $ubootaddr $filesize && "               \
 644         "protect on $ubootaddr +$filesize && "                  \
 645         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 646         "consoledev=ttyS0\0"                                    \
 647         "ramdiskaddr=2000000\0"                                 \
 648         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 649         "fdtaddr=1e00000\0"                                     \
 650         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 651         "bdev=sda3\0"
 652
 653 #define CONFIG_HVBOOT                                   \
 654         "setenv bootargs config-addr=0x60000000; "      \
 655         "bootm 0x01000000 - 0x00f00000"
 656
 657 #define CONFIG_LINUX                                    \
 658         "setenv bootargs root=/dev/ram rw "             \
 659         "console=$consoledev,$baudrate $othbootargs;"   \
 660         "setenv ramdiskaddr 0x02000000;"                \
 661         "setenv fdtaddr 0x00c00000;"                    \
 662         "setenv loadaddr 0x1000000;"                    \
 663         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 664
 665 #define CONFIG_HDBOOT                                   \
 666         "setenv bootargs root=/dev/$bdev rw "           \
 667         "console=$consoledev,$baudrate $othbootargs;"   \
 668         "tftp $loadaddr $bootfile;"                     \
 669         "tftp $fdtaddr $fdtfile;"                       \
 670         "bootm $loadaddr - $fdtaddr"
 671
 672 #define CONFIG_NFSBOOTCOMMAND                   \
 673         "setenv bootargs root=/dev/nfs rw "     \
 674         "nfsroot=$serverip:$rootpath "          \
 675         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 676         "console=$consoledev,$baudrate $othbootargs;"   \
 677         "tftp $loadaddr $bootfile;"             \
 678         "tftp $fdtaddr $fdtfile;"               \
 679         "bootm $loadaddr - $fdtaddr"
 680
 681 #define CONFIG_RAMBOOTCOMMAND                           \
 682         "setenv bootargs root=/dev/ram rw "             \
 683         "console=$consoledev,$baudrate $othbootargs;"   \
 684         "tftp $ramdiskaddr $ramdiskfile;"               \
 685         "tftp $loadaddr $bootfile;"                     \
 686         "tftp $fdtaddr $fdtfile;"                       \
 687         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 688
 689 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 690
 691 #include <asm/fsl_secure_boot.h>
 692
 693 #endif  /* __CONFIG_H */