include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #define CONFIG_FSL_SATA_V2
  16 #define CONFIG_PCIE4
  17
  18 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  19
  20 #ifdef CONFIG_RAMBOOT_PBL
  21 #ifndef CONFIG_SDCARD
  22 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  23 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  24 #else
  25 #define CONFIG_SPL_PAD_TO               0x40000
  26 #define CONFIG_SPL_MAX_SIZE             0x28000
  27 #define RESET_VECTOR_OFFSET             0x27FFC
  28 #define BOOT_PAGE_OFFSET                0x27000
  29
  30 #ifdef  CONFIG_SDCARD
  31 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  32 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  33 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  34 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  35 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  36 #ifndef CONFIG_SPL_BUILD
  37 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  38 #endif
  39 #endif
  40
  41 #ifdef CONFIG_SPL_BUILD
  42 #define CONFIG_SPL_COMMON_INIT_DDR
  43 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  44 #endif
  45
  46 #endif
  47 #endif /* CONFIG_RAMBOOT_PBL */
  48
  49 /* High Level Configuration Options */
  50 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  51
  52 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  53 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  54 #endif
  55
  56 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  57 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  58 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  59 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  60 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  61
  62 /*
  63  * These can be toggled for performance analysis, otherwise use default.
  64  */
  65 #define CONFIG_SYS_CACHE_STASHING
  66 #ifdef CONFIG_DDR_ECC
  67 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  68 #endif
  69
  70 #define CONFIG_ENABLE_36BIT_PHYS
  71
  72 /*
  73  *  Config the L3 Cache as L3 SRAM
  74  */
  75 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  76 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  77 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  78 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  79 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
  80 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
  81 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
  82
  83 #define CONFIG_SYS_DCSRBAR              0xf0000000
  84 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  85
  86 /*
  87  * DDR Setup
  88  */
  89 #define CONFIG_VERY_BIG_RAM
  90 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  91 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  92
  93 /*
  94  * IFC Definitions
  95  */
  96 #define CONFIG_SYS_FLASH_BASE   0xe0000000
  97 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  98
  99 #define CONFIG_HWCONFIG
 100
 101 /* define to use L1 as initial stack */
 102 #define CONFIG_L1_INIT_RAM
 103 #define CONFIG_SYS_INIT_RAM_LOCK
 104 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 105 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 106 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 107 /* The assembler doesn't like typecast */
 108 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 109         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 110           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 111 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 112
 113 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 114                                         GENERATED_GBL_DATA_SIZE)
 115 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 116
 117 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 118
 119 /* Serial Port - controlled on board with jumper J8
 120  * open - index 2
 121  * shorted - index 1
 122  */
 123 #define CONFIG_SYS_NS16550_SERIAL
 124 #define CONFIG_SYS_NS16550_REG_SIZE     1
 125 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 126
 127 #define CONFIG_SYS_BAUDRATE_TABLE       \
 128         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 129
 130 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 131 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 132 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 133 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 134
 135 /* I2C */
 136
 137 /*
 138  * General PCI
 139  * Memory space is mapped 1-1, but I/O space must start from 0.
 140  */
 141
 142 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 143 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 144 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 145 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 146 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 147
 148 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 149 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 150 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 151 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 152 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 153
 154 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 155 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 156 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 157 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 158 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 159
 160 /* controller 4, Base address 203000 */
 161 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 162 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 163 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 164
 165 #ifdef CONFIG_PCI
 166 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 167 #endif  /* CONFIG_PCI */
 168
 169 /* SATA */
 170 #ifdef CONFIG_FSL_SATA_V2
 171 #define CONFIG_SATA1
 172 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 173 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 174 #define CONFIG_SATA2
 175 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 176 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 177
 178 #define CONFIG_LBA48
 179 #endif
 180
 181 /*
 182  * Environment
 183  */
 184 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 185 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 186
 187 /*
 188  * Miscellaneous configurable options
 189  */
 190
 191 /*
 192  * For booting Linux, the board info and command line data
 193  * have to be in the first 64 MB of memory, since this is
 194  * the maximum mapped by the Linux kernel during initialization.
 195  */
 196 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 197 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 198
 199 /*
 200  * Environment Configuration
 201  */
 202 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 203 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 204
 205 #define HVBOOT                                  \
 206         "setenv bootargs config-addr=0x60000000; "      \
 207         "bootm 0x01000000 - 0x00f00000"
 208
 209 /*
 210  * DDR Setup
 211  */
 212 #define CONFIG_SYS_SPD_BUS_NUM  0
 213 #define SPD_EEPROM_ADDRESS1     0x52
 214 #define SPD_EEPROM_ADDRESS2     0x54
 215 #define SPD_EEPROM_ADDRESS3     0x56
 216 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 217 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 218
 219 /*
 220  * IFC Definitions
 221  */
 222 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 223 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 224                                 + 0x8000000) | \
 225                                 CSPR_PORT_SIZE_16 | \
 226                                 CSPR_MSEL_NOR | \
 227                                 CSPR_V)
 228 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 229 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 230                                 CSPR_PORT_SIZE_16 | \
 231                                 CSPR_MSEL_NOR | \
 232                                 CSPR_V)
 233 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 234 /* NOR Flash Timing Params */
 235 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 236
 237 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 238                                 FTIM0_NOR_TEADC(0x5) | \
 239                                 FTIM0_NOR_TEAHC(0x5))
 240 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 241                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 242                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 243 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 244                                 FTIM2_NOR_TCH(0x4) | \
 245                                 FTIM2_NOR_TWPH(0x0E) | \
 246                                 FTIM2_NOR_TWP(0x1c))
 247 #define CONFIG_SYS_NOR_FTIM3    0x0
 248
 249 #define CONFIG_SYS_FLASH_QUIET_TEST
 250 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 251
 252 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 253 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 254 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 255
 256 #define CONFIG_SYS_FLASH_EMPTY_INFO
 257 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 258                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 259
 260 /* NAND Flash on IFC */
 261 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 262 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 263 #define CONFIG_SYS_NAND_BASE            0xff800000
 264 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 265
 266 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 267 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 268                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 269                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 270                                 | CSPR_V)
 271 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 272
 273 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 274                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 275                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 276                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 277                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 278                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 279                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 280
 281 /* ONFI NAND Flash mode0 Timing Params */
 282 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 283                                         FTIM0_NAND_TWP(0x18)   | \
 284                                         FTIM0_NAND_TWCHT(0x07) | \
 285                                         FTIM0_NAND_TWH(0x0a))
 286 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 287                                         FTIM1_NAND_TWBE(0x39)  | \
 288                                         FTIM1_NAND_TRR(0x0e)   | \
 289                                         FTIM1_NAND_TRP(0x18))
 290 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 291                                         FTIM2_NAND_TREH(0x0a) | \
 292                                         FTIM2_NAND_TWHRE(0x1e))
 293 #define CONFIG_SYS_NAND_FTIM3           0x0
 294
 295 #define CONFIG_SYS_NAND_DDR_LAW         11
 296 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 297 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 298
 299 #if defined(CONFIG_MTD_RAW_NAND)
 300 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 301 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 302 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 303 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 304 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 305 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 306 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 307 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 308 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 309 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 310 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 311 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 312 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 313 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 314 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 315 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 316 #else
 317 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 318 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 319 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 320 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 321 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 322 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 323 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 324 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 325 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 326 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 327 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 328 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 329 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 330 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 331 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 332 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 333 #endif
 334 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 335 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 336 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 337 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 338 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 339 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 340 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 341 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 342
 343 /* CPLD on IFC */
 344 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 345 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 346 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 347 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 348                                 | CSPR_PORT_SIZE_8 \
 349                                 | CSPR_MSEL_GPCM \
 350                                 | CSPR_V)
 351
 352 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 353 #define CONFIG_SYS_CSOR3        0x0
 354
 355 /* CPLD Timing parameters for IFC CS3 */
 356 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 357                                         FTIM0_GPCM_TEADC(0x0e) | \
 358                                         FTIM0_GPCM_TEAHC(0x0e))
 359 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 360                                         FTIM1_GPCM_TRAD(0x1f))
 361 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 362                                         FTIM2_GPCM_TCH(0x8) | \
 363                                         FTIM2_GPCM_TWP(0x1f))
 364 #define CONFIG_SYS_CS3_FTIM3            0x0
 365
 366 #if defined(CONFIG_RAMBOOT_PBL)
 367 #define CONFIG_SYS_RAMBOOT
 368 #endif
 369
 370 /* I2C */
 371 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 372 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 373
 374 #define I2C_MUX_CH_DEFAULT      0x8
 375 #define I2C_MUX_CH_VOL_MONITOR  0xa
 376 #define I2C_MUX_CH_VSC3316_FS   0xc
 377 #define I2C_MUX_CH_VSC3316_BS   0xd
 378
 379 /* Voltage monitor on channel 2*/
 380 #define I2C_VOL_MONITOR_ADDR            0x40
 381 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 382 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 383 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 384
 385 /* The lowest and highest voltage allowed for T4240RDB */
 386 #define VDD_MV_MIN                      819
 387 #define VDD_MV_MAX                      1212
 388
 389 /*
 390  * eSPI - Enhanced SPI
 391  */
 392
 393 /* Qman/Bman */
 394 #ifndef CONFIG_NOBQFMAN
 395 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 396 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 397 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 398 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 399 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 400 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 401 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 402 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 403 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 404                                         CONFIG_SYS_BMAN_CENA_SIZE)
 405 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 406 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 407 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 408 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 409 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 410 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 411 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 412 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 413 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 414 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 415 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 416                                         CONFIG_SYS_QMAN_CENA_SIZE)
 417 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 418 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 419
 420 #define CONFIG_SYS_DPAA_FMAN
 421 #define CONFIG_SYS_DPAA_PME
 422 #define CONFIG_SYS_PMAN
 423 #define CONFIG_SYS_DPAA_DCE
 424 #define CONFIG_SYS_DPAA_RMAN
 425 #define CONFIG_SYS_INTERLAKEN
 426
 427 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 428 #endif /* CONFIG_NOBQFMAN */
 429
 430 #ifdef CONFIG_SYS_DPAA_FMAN
 431 #define SGMII_PHY_ADDR1 0x0
 432 #define SGMII_PHY_ADDR2 0x1
 433 #define SGMII_PHY_ADDR3 0x2
 434 #define SGMII_PHY_ADDR4 0x3
 435 #define SGMII_PHY_ADDR5 0x4
 436 #define SGMII_PHY_ADDR6 0x5
 437 #define SGMII_PHY_ADDR7 0x6
 438 #define SGMII_PHY_ADDR8 0x7
 439 #define FM1_10GEC1_PHY_ADDR     0x10
 440 #define FM1_10GEC2_PHY_ADDR     0x11
 441 #define FM2_10GEC1_PHY_ADDR     0x12
 442 #define FM2_10GEC2_PHY_ADDR     0x13
 443 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 444 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 445 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 446 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 447 #endif
 448
 449 /* SATA */
 450 #ifdef CONFIG_FSL_SATA_V2
 451 #define CONFIG_SATA1
 452 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 453 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 454 #define CONFIG_SATA2
 455 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 456 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 457
 458 #define CONFIG_LBA48
 459 #endif
 460
 461 /*
 462 * USB
 463 */
 464 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 465 #define CONFIG_HAS_FSL_DR_USB
 466
 467 #ifdef CONFIG_MMC
 468 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 469 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 470 #endif
 471
 472
 473 #define __USB_PHY_TYPE  utmi
 474
 475 /*
 476  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 477  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 478  * interleaving. It can be cacheline, page, bank, superbank.
 479  * See doc/README.fsl-ddr for details.
 480  */
 481 #ifdef CONFIG_ARCH_T4240
 482 #define CTRL_INTLV_PREFERED 3way_4KB
 483 #else
 484 #define CTRL_INTLV_PREFERED cacheline
 485 #endif
 486
 487 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 488         "hwconfig=fsl_ddr:"                                     \
 489         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 490         "bank_intlv=auto;"                                      \
 491         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 492         "netdev=eth0\0"                                         \
 493         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 494         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 495         "tftpflash=tftpboot $loadaddr $uboot && "               \
 496         "protect off $ubootaddr +$filesize && "                 \
 497         "erase $ubootaddr +$filesize && "                       \
 498         "cp.b $loadaddr $ubootaddr $filesize && "               \
 499         "protect on $ubootaddr +$filesize && "                  \
 500         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 501         "consoledev=ttyS0\0"                                    \
 502         "ramdiskaddr=2000000\0"                                 \
 503         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 504         "fdtaddr=1e00000\0"                                     \
 505         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 506         "bdev=sda3\0"
 507
 508 #define HVBOOT                                  \
 509         "setenv bootargs config-addr=0x60000000; "      \
 510         "bootm 0x01000000 - 0x00f00000"
 511
 512 #include <asm/fsl_secure_boot.h>
 513
 514 #endif  /* __CONFIG_H */