2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T4240 RDB board configuration file
13 #define CONFIG_T4240RDB
14 #define CONFIG_DISPLAY_BOARDINFO
16 #define CONFIG_FSL_SATA_V2
19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
21 #ifdef CONFIG_RAMBOOT_PBL
22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
23 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
28 #define CONFIG_SPL_SERIAL_SUPPORT
29 #define CONFIG_SPL_FLUSH_IMAGE
30 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
31 #define CONFIG_FSL_LAW /* Use common FSL init code */
32 #define CONFIG_SYS_TEXT_BASE 0x00201000
33 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
34 #define CONFIG_SPL_PAD_TO 0x40000
35 #define CONFIG_SPL_MAX_SIZE 0x28000
36 #define RESET_VECTOR_OFFSET 0x27FFC
37 #define BOOT_PAGE_OFFSET 0x27000
40 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
41 #define CONFIG_SPL_MMC_MINIMAL
42 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
43 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
44 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
45 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
46 #ifndef CONFIG_SPL_BUILD
47 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
50 #define CONFIG_SPL_MMC_BOOT
53 #ifdef CONFIG_SPL_BUILD
54 #define CONFIG_SPL_SKIP_RELOCATE
55 #define CONFIG_SPL_COMMON_INIT_DDR
56 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
57 #define CONFIG_SYS_NO_FLASH
61 #endif /* CONFIG_RAMBOOT_PBL */
63 #define CONFIG_DDR_ECC
65 #define CONFIG_CMD_REGINFO
67 /* High Level Configuration Options */
69 #define CONFIG_E500 /* BOOKE e500 family */
70 #define CONFIG_E500MC /* BOOKE e500mc family */
71 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
72 #define CONFIG_MP /* support multiple processors */
74 #ifndef CONFIG_SYS_TEXT_BASE
75 #define CONFIG_SYS_TEXT_BASE 0xeff40000
78 #ifndef CONFIG_RESET_VECTOR_ADDRESS
79 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
82 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
83 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
84 #define CONFIG_FSL_IFC /* Enable IFC Support */
85 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
86 #define CONFIG_PCI /* Enable PCI/PCIE */
87 #define CONFIG_PCIE1 /* PCIE controller 1 */
88 #define CONFIG_PCIE2 /* PCIE controller 2 */
89 #define CONFIG_PCIE3 /* PCIE controller 3 */
90 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
91 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
93 #define CONFIG_FSL_LAW /* Use common FSL init code */
95 #define CONFIG_ENV_OVERWRITE
98 * These can be toggled for performance analysis, otherwise use default.
100 #define CONFIG_SYS_CACHE_STASHING
101 #define CONFIG_BTB /* toggle branch predition */
102 #ifdef CONFIG_DDR_ECC
103 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
104 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
107 #define CONFIG_ENABLE_36BIT_PHYS
109 #define CONFIG_ADDR_MAP
110 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
112 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
113 #define CONFIG_SYS_MEMTEST_END 0x00400000
114 #define CONFIG_SYS_ALT_MEMTEST
115 #define CONFIG_PANIC_HANG /* do not reset board on panic */
118 * Config the L3 Cache as L3 SRAM
120 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
121 #define CONFIG_SYS_L3_SIZE (512 << 10)
122 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
123 #ifdef CONFIG_RAMBOOT_PBL
124 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
126 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
127 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
128 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
129 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
131 #define CONFIG_SYS_DCSRBAR 0xf0000000
132 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
137 #define CONFIG_VERY_BIG_RAM
138 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
139 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
141 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
142 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
143 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
144 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
146 #define CONFIG_DDR_SPD
147 #define CONFIG_SYS_FSL_DDR3
152 #define CONFIG_SYS_FLASH_BASE 0xe0000000
153 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
155 #ifdef CONFIG_SPL_BUILD
156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
158 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
161 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
162 #define CONFIG_MISC_INIT_R
164 #define CONFIG_HWCONFIG
166 /* define to use L1 as initial stack */
167 #define CONFIG_L1_INIT_RAM
168 #define CONFIG_SYS_INIT_RAM_LOCK
169 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
170 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
171 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
172 /* The assembler doesn't like typecast */
173 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
174 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
175 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
176 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
178 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
179 GENERATED_GBL_DATA_SIZE)
180 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
182 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
183 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
185 /* Serial Port - controlled on board with jumper J8
189 #define CONFIG_CONS_INDEX 1
190 #define CONFIG_SYS_NS16550_SERIAL
191 #define CONFIG_SYS_NS16550_REG_SIZE 1
192 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
194 #define CONFIG_SYS_BAUDRATE_TABLE \
195 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
197 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
198 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
199 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
200 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
203 #define CONFIG_SYS_I2C
204 #define CONFIG_SYS_I2C_FSL
205 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
206 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
207 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
208 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
212 * Memory space is mapped 1-1, but I/O space must start from 0.
215 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
216 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
217 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
218 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
219 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
220 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
221 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
222 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
223 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
225 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
226 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
227 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
228 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
229 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
230 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
231 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
232 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
233 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
235 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
236 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
237 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
238 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
239 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
240 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
241 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
242 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
243 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
245 /* controller 4, Base address 203000 */
246 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
247 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
248 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
249 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
250 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
251 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
254 #define CONFIG_PCI_INDIRECT_BRIDGE
255 #define CONFIG_PCI_PNP /* do pci plug-and-play */
257 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
258 #define CONFIG_DOS_PARTITION
259 #endif /* CONFIG_PCI */
262 #ifdef CONFIG_FSL_SATA_V2
263 #define CONFIG_LIBATA
264 #define CONFIG_FSL_SATA
266 #define CONFIG_SYS_SATA_MAX_DEVICE 2
268 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
269 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
271 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
272 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
275 #define CONFIG_CMD_SATA
276 #define CONFIG_DOS_PARTITION
279 #ifdef CONFIG_FMAN_ENET
280 #define CONFIG_MII /* MII PHY management */
281 #define CONFIG_ETHPRIME "FM1@DTSEC1"
282 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
288 #define CONFIG_LOADS_ECHO /* echo on for serial download */
289 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
292 * Command line configuration.
294 #define CONFIG_CMD_ERRATA
295 #define CONFIG_CMD_IRQ
298 #define CONFIG_CMD_PCI
302 * Miscellaneous configurable options
304 #define CONFIG_SYS_LONGHELP /* undef to save memory */
305 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
306 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
307 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
308 #ifdef CONFIG_CMD_KGDB
309 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
311 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
313 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
314 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
315 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
318 * For booting Linux, the board info and command line data
319 * have to be in the first 64 MB of memory, since this is
320 * the maximum mapped by the Linux kernel during initialization.
322 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
323 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
325 #ifdef CONFIG_CMD_KGDB
326 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
330 * Environment Configuration
332 #define CONFIG_ROOTPATH "/opt/nfsroot"
333 #define CONFIG_BOOTFILE "uImage"
334 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
336 /* default location for tftp and bootm */
337 #define CONFIG_LOADADDR 1000000
339 #define CONFIG_BAUDRATE 115200
341 #define CONFIG_HVBOOT \
342 "setenv bootargs config-addr=0x60000000; " \
343 "bootm 0x01000000 - 0x00f00000"
345 #ifdef CONFIG_SYS_NO_FLASH
346 #ifndef CONFIG_RAMBOOT_PBL
347 #define CONFIG_ENV_IS_NOWHERE
350 #define CONFIG_FLASH_CFI_DRIVER
351 #define CONFIG_SYS_FLASH_CFI
352 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
355 #if defined(CONFIG_SPIFLASH)
356 #define CONFIG_SYS_EXTRA_ENV_RELOC
357 #define CONFIG_ENV_IS_IN_SPI_FLASH
358 #define CONFIG_ENV_SPI_BUS 0
359 #define CONFIG_ENV_SPI_CS 0
360 #define CONFIG_ENV_SPI_MAX_HZ 10000000
361 #define CONFIG_ENV_SPI_MODE 0
362 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
363 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
364 #define CONFIG_ENV_SECT_SIZE 0x10000
365 #elif defined(CONFIG_SDCARD)
366 #define CONFIG_SYS_EXTRA_ENV_RELOC
367 #define CONFIG_ENV_IS_IN_MMC
368 #define CONFIG_SYS_MMC_ENV_DEV 0
369 #define CONFIG_ENV_SIZE 0x2000
370 #define CONFIG_ENV_OFFSET (512 * 0x800)
371 #elif defined(CONFIG_NAND)
372 #define CONFIG_SYS_EXTRA_ENV_RELOC
373 #define CONFIG_ENV_IS_IN_NAND
374 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
375 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
376 #elif defined(CONFIG_ENV_IS_NOWHERE)
377 #define CONFIG_ENV_SIZE 0x2000
379 #define CONFIG_ENV_IS_IN_FLASH
380 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
381 #define CONFIG_ENV_SIZE 0x2000
382 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
385 #define CONFIG_SYS_CLK_FREQ 66666666
386 #define CONFIG_DDR_CLK_FREQ 133333333
389 unsigned long get_board_sys_clk(void);
390 unsigned long get_board_ddr_clk(void);
396 #define CONFIG_SYS_SPD_BUS_NUM 0
397 #define SPD_EEPROM_ADDRESS1 0x52
398 #define SPD_EEPROM_ADDRESS2 0x54
399 #define SPD_EEPROM_ADDRESS3 0x56
400 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
401 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
406 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
407 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
409 CSPR_PORT_SIZE_16 | \
412 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
413 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
414 CSPR_PORT_SIZE_16 | \
417 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
418 /* NOR Flash Timing Params */
419 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
421 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
422 FTIM0_NOR_TEADC(0x5) | \
423 FTIM0_NOR_TEAHC(0x5))
424 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
425 FTIM1_NOR_TRAD_NOR(0x1A) |\
426 FTIM1_NOR_TSEQRAD_NOR(0x13))
427 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
428 FTIM2_NOR_TCH(0x4) | \
429 FTIM2_NOR_TWPH(0x0E) | \
431 #define CONFIG_SYS_NOR_FTIM3 0x0
433 #define CONFIG_SYS_FLASH_QUIET_TEST
434 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
436 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
437 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
438 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
439 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
441 #define CONFIG_SYS_FLASH_EMPTY_INFO
442 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
443 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
445 /* NAND Flash on IFC */
446 #define CONFIG_NAND_FSL_IFC
447 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
448 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
449 #define CONFIG_SYS_NAND_BASE 0xff800000
450 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
452 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
453 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
454 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
455 | CSPR_MSEL_NAND /* MSEL = NAND */ \
457 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
459 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
460 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
461 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
462 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
463 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
464 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
465 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
467 #define CONFIG_SYS_NAND_ONFI_DETECTION
469 /* ONFI NAND Flash mode0 Timing Params */
470 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
471 FTIM0_NAND_TWP(0x18) | \
472 FTIM0_NAND_TWCHT(0x07) | \
473 FTIM0_NAND_TWH(0x0a))
474 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
475 FTIM1_NAND_TWBE(0x39) | \
476 FTIM1_NAND_TRR(0x0e) | \
477 FTIM1_NAND_TRP(0x18))
478 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
479 FTIM2_NAND_TREH(0x0a) | \
480 FTIM2_NAND_TWHRE(0x1e))
481 #define CONFIG_SYS_NAND_FTIM3 0x0
483 #define CONFIG_SYS_NAND_DDR_LAW 11
484 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
485 #define CONFIG_SYS_MAX_NAND_DEVICE 1
486 #define CONFIG_CMD_NAND
488 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
490 #if defined(CONFIG_NAND)
491 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
492 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
493 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
494 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
495 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
496 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
497 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
498 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
499 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
500 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
501 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
502 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
503 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
504 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
505 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
506 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
508 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
509 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
510 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
511 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
512 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
513 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
514 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
515 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
516 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
517 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
518 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
519 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
520 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
521 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
522 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
523 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
525 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
526 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
527 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
528 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
529 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
530 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
531 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
532 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
535 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
536 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
537 #define CONFIG_SYS_CSPR3_EXT (0xf)
538 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
543 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
544 #define CONFIG_SYS_CSOR3 0x0
546 /* CPLD Timing parameters for IFC CS3 */
547 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
548 FTIM0_GPCM_TEADC(0x0e) | \
549 FTIM0_GPCM_TEAHC(0x0e))
550 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
551 FTIM1_GPCM_TRAD(0x1f))
552 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
553 FTIM2_GPCM_TCH(0x8) | \
554 FTIM2_GPCM_TWP(0x1f))
555 #define CONFIG_SYS_CS3_FTIM3 0x0
557 #if defined(CONFIG_RAMBOOT_PBL)
558 #define CONFIG_SYS_RAMBOOT
562 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
563 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
564 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
565 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
567 #define I2C_MUX_CH_DEFAULT 0x8
568 #define I2C_MUX_CH_VOL_MONITOR 0xa
569 #define I2C_MUX_CH_VSC3316_FS 0xc
570 #define I2C_MUX_CH_VSC3316_BS 0xd
572 /* Voltage monitor on channel 2*/
573 #define I2C_VOL_MONITOR_ADDR 0x40
574 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
575 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
576 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
578 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
579 #ifndef CONFIG_SPL_BUILD
582 #define CONFIG_VOL_MONITOR_IR36021_SET
583 #define CONFIG_VOL_MONITOR_IR36021_READ
584 /* The lowest and highest voltage allowed for T4240RDB */
585 #define VDD_MV_MIN 819
586 #define VDD_MV_MAX 1212
589 * eSPI - Enhanced SPI
591 #define CONFIG_SF_DEFAULT_SPEED 10000000
592 #define CONFIG_SF_DEFAULT_MODE 0
595 #ifndef CONFIG_NOBQFMAN
596 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
597 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
598 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
599 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
600 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
601 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
602 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
603 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
604 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
605 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
606 CONFIG_SYS_BMAN_CENA_SIZE)
607 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
608 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
609 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
610 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
611 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
612 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
613 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
614 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
615 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
616 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
617 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
618 CONFIG_SYS_QMAN_CENA_SIZE)
619 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
620 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
622 #define CONFIG_SYS_DPAA_FMAN
623 #define CONFIG_SYS_DPAA_PME
624 #define CONFIG_SYS_PMAN
625 #define CONFIG_SYS_DPAA_DCE
626 #define CONFIG_SYS_DPAA_RMAN
627 #define CONFIG_SYS_INTERLAKEN
629 /* Default address of microcode for the Linux Fman driver */
630 #if defined(CONFIG_SPIFLASH)
632 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
633 * env, so we got 0x110000.
635 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
636 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
637 #elif defined(CONFIG_SDCARD)
639 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
640 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
641 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
643 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
644 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
645 #elif defined(CONFIG_NAND)
646 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
647 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
649 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
650 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
652 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
653 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
654 #endif /* CONFIG_NOBQFMAN */
656 #ifdef CONFIG_SYS_DPAA_FMAN
657 #define CONFIG_FMAN_ENET
658 #define CONFIG_PHYLIB_10G
659 #define CONFIG_PHY_VITESSE
660 #define CONFIG_PHY_CORTINA
661 #define CONFIG_SYS_CORTINA_FW_IN_NOR
662 #define CONFIG_CORTINA_FW_ADDR 0xefe00000
663 #define CONFIG_CORTINA_FW_LENGTH 0x40000
664 #define CONFIG_PHY_TERANETICS
665 #define SGMII_PHY_ADDR1 0x0
666 #define SGMII_PHY_ADDR2 0x1
667 #define SGMII_PHY_ADDR3 0x2
668 #define SGMII_PHY_ADDR4 0x3
669 #define SGMII_PHY_ADDR5 0x4
670 #define SGMII_PHY_ADDR6 0x5
671 #define SGMII_PHY_ADDR7 0x6
672 #define SGMII_PHY_ADDR8 0x7
673 #define FM1_10GEC1_PHY_ADDR 0x10
674 #define FM1_10GEC2_PHY_ADDR 0x11
675 #define FM2_10GEC1_PHY_ADDR 0x12
676 #define FM2_10GEC2_PHY_ADDR 0x13
677 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
678 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
679 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
680 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
684 #ifdef CONFIG_FSL_SATA_V2
685 #define CONFIG_LIBATA
686 #define CONFIG_FSL_SATA
688 #define CONFIG_SYS_SATA_MAX_DEVICE 2
690 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
691 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
693 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
694 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
697 #define CONFIG_CMD_SATA
698 #define CONFIG_DOS_PARTITION
701 #ifdef CONFIG_FMAN_ENET
702 #define CONFIG_MII /* MII PHY management */
703 #define CONFIG_ETHPRIME "FM1@DTSEC1"
704 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
710 #define CONFIG_USB_EHCI
711 #define CONFIG_USB_EHCI_FSL
712 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
713 #define CONFIG_HAS_FSL_DR_USB
718 #define CONFIG_FSL_ESDHC
719 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
720 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
721 #define CONFIG_GENERIC_MMC
722 #define CONFIG_DOS_PARTITION
723 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
726 /* Hash command with SHA acceleration supported in hardware */
727 #ifdef CONFIG_FSL_CAAM
728 #define CONFIG_CMD_HASH
729 #define CONFIG_SHA_HW_ACCEL
733 #define __USB_PHY_TYPE utmi
736 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
737 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
738 * interleaving. It can be cacheline, page, bank, superbank.
739 * See doc/README.fsl-ddr for details.
741 #ifdef CONFIG_PPC_T4240
742 #define CTRL_INTLV_PREFERED 3way_4KB
744 #define CTRL_INTLV_PREFERED cacheline
747 #define CONFIG_EXTRA_ENV_SETTINGS \
748 "hwconfig=fsl_ddr:" \
749 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
751 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
753 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
754 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
755 "tftpflash=tftpboot $loadaddr $uboot && " \
756 "protect off $ubootaddr +$filesize && " \
757 "erase $ubootaddr +$filesize && " \
758 "cp.b $loadaddr $ubootaddr $filesize && " \
759 "protect on $ubootaddr +$filesize && " \
760 "cmp.b $loadaddr $ubootaddr $filesize\0" \
761 "consoledev=ttyS0\0" \
762 "ramdiskaddr=2000000\0" \
763 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
764 "fdtaddr=1e00000\0" \
765 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
768 #define CONFIG_HVBOOT \
769 "setenv bootargs config-addr=0x60000000; " \
770 "bootm 0x01000000 - 0x00f00000"
772 #define CONFIG_LINUX \
773 "setenv bootargs root=/dev/ram rw " \
774 "console=$consoledev,$baudrate $othbootargs;" \
775 "setenv ramdiskaddr 0x02000000;" \
776 "setenv fdtaddr 0x00c00000;" \
777 "setenv loadaddr 0x1000000;" \
778 "bootm $loadaddr $ramdiskaddr $fdtaddr"
780 #define CONFIG_HDBOOT \
781 "setenv bootargs root=/dev/$bdev rw " \
782 "console=$consoledev,$baudrate $othbootargs;" \
783 "tftp $loadaddr $bootfile;" \
784 "tftp $fdtaddr $fdtfile;" \
785 "bootm $loadaddr - $fdtaddr"
787 #define CONFIG_NFSBOOTCOMMAND \
788 "setenv bootargs root=/dev/nfs rw " \
789 "nfsroot=$serverip:$rootpath " \
790 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
791 "console=$consoledev,$baudrate $othbootargs;" \
792 "tftp $loadaddr $bootfile;" \
793 "tftp $fdtaddr $fdtfile;" \
794 "bootm $loadaddr - $fdtaddr"
796 #define CONFIG_RAMBOOTCOMMAND \
797 "setenv bootargs root=/dev/ram rw " \
798 "console=$consoledev,$baudrate $othbootargs;" \
799 "tftp $ramdiskaddr $ramdiskfile;" \
800 "tftp $loadaddr $bootfile;" \
801 "tftp $fdtaddr $fdtfile;" \
802 "bootm $loadaddr $ramdiskaddr $fdtaddr"
804 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
806 #include <asm/fsl_secure_boot.h>
808 #endif /* __CONFIG_H */