include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #define CONFIG_FSL_SATA_V2
  16 #define CONFIG_PCIE4
  17
  18 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  19
  20 #ifdef CONFIG_RAMBOOT_PBL
  21 #ifndef CONFIG_SDCARD
  22 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  23 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  24 #else
  25 #define CONFIG_SPL_FLUSH_IMAGE
  26 #define CONFIG_SPL_PAD_TO               0x40000
  27 #define CONFIG_SPL_MAX_SIZE             0x28000
  28 #define RESET_VECTOR_OFFSET             0x27FFC
  29 #define BOOT_PAGE_OFFSET                0x27000
  30
  31 #ifdef  CONFIG_SDCARD
  32 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  33 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  34 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  35 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  36 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  37 #ifndef CONFIG_SPL_BUILD
  38 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  39 #endif
  40 #endif
  41
  42 #ifdef CONFIG_SPL_BUILD
  43 #define CONFIG_SPL_SKIP_RELOCATE
  44 #define CONFIG_SPL_COMMON_INIT_DDR
  45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  46 #endif
  47
  48 #endif
  49 #endif /* CONFIG_RAMBOOT_PBL */
  50
  51 /* High Level Configuration Options */
  52 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  53
  54 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  55 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  56 #endif
  57
  58 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  59 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  60 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  61 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  62 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  63
  64 /*
  65  * These can be toggled for performance analysis, otherwise use default.
  66  */
  67 #define CONFIG_SYS_CACHE_STASHING
  68 #ifdef CONFIG_DDR_ECC
  69 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  70 #endif
  71
  72 #define CONFIG_ENABLE_36BIT_PHYS
  73
  74 /*
  75  *  Config the L3 Cache as L3 SRAM
  76  */
  77 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  78 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  79 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  80 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  81 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
  82 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
  83 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
  84
  85 #define CONFIG_SYS_DCSRBAR              0xf0000000
  86 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  87
  88 /*
  89  * DDR Setup
  90  */
  91 #define CONFIG_VERY_BIG_RAM
  92 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  93 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  94
  95 /*
  96  * IFC Definitions
  97  */
  98 #define CONFIG_SYS_FLASH_BASE   0xe0000000
  99 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 100
 101 #define CONFIG_HWCONFIG
 102
 103 /* define to use L1 as initial stack */
 104 #define CONFIG_L1_INIT_RAM
 105 #define CONFIG_SYS_INIT_RAM_LOCK
 106 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 107 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 108 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 109 /* The assembler doesn't like typecast */
 110 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 111         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 112           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 113 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 114
 115 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 116                                         GENERATED_GBL_DATA_SIZE)
 117 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 118
 119 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 120
 121 /* Serial Port - controlled on board with jumper J8
 122  * open - index 2
 123  * shorted - index 1
 124  */
 125 #define CONFIG_SYS_NS16550_SERIAL
 126 #define CONFIG_SYS_NS16550_REG_SIZE     1
 127 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 128
 129 #define CONFIG_SYS_BAUDRATE_TABLE       \
 130         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 131
 132 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 133 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 134 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 135 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 136
 137 /* I2C */
 138
 139 /*
 140  * General PCI
 141  * Memory space is mapped 1-1, but I/O space must start from 0.
 142  */
 143
 144 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 145 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 146 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 147 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 148 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 149
 150 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 151 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 152 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 153 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 154 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 155
 156 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 157 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 158 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 159 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 160 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 161
 162 /* controller 4, Base address 203000 */
 163 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 164 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 165 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 166
 167 #ifdef CONFIG_PCI
 168 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 169 #endif  /* CONFIG_PCI */
 170
 171 /* SATA */
 172 #ifdef CONFIG_FSL_SATA_V2
 173 #define CONFIG_SATA1
 174 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 175 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 176 #define CONFIG_SATA2
 177 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 178 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 179
 180 #define CONFIG_LBA48
 181 #endif
 182
 183 /*
 184  * Environment
 185  */
 186 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 187 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 188
 189 /*
 190  * Miscellaneous configurable options
 191  */
 192
 193 /*
 194  * For booting Linux, the board info and command line data
 195  * have to be in the first 64 MB of memory, since this is
 196  * the maximum mapped by the Linux kernel during initialization.
 197  */
 198 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 199 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 200
 201 /*
 202  * Environment Configuration
 203  */
 204 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 205 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 206
 207 #define HVBOOT                                  \
 208         "setenv bootargs config-addr=0x60000000; "      \
 209         "bootm 0x01000000 - 0x00f00000"
 210
 211 /*
 212  * DDR Setup
 213  */
 214 #define CONFIG_SYS_SPD_BUS_NUM  0
 215 #define SPD_EEPROM_ADDRESS1     0x52
 216 #define SPD_EEPROM_ADDRESS2     0x54
 217 #define SPD_EEPROM_ADDRESS3     0x56
 218 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 219 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 220
 221 /*
 222  * IFC Definitions
 223  */
 224 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 225 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 226                                 + 0x8000000) | \
 227                                 CSPR_PORT_SIZE_16 | \
 228                                 CSPR_MSEL_NOR | \
 229                                 CSPR_V)
 230 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 231 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 232                                 CSPR_PORT_SIZE_16 | \
 233                                 CSPR_MSEL_NOR | \
 234                                 CSPR_V)
 235 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 236 /* NOR Flash Timing Params */
 237 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 238
 239 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 240                                 FTIM0_NOR_TEADC(0x5) | \
 241                                 FTIM0_NOR_TEAHC(0x5))
 242 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 243                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 244                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 245 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 246                                 FTIM2_NOR_TCH(0x4) | \
 247                                 FTIM2_NOR_TWPH(0x0E) | \
 248                                 FTIM2_NOR_TWP(0x1c))
 249 #define CONFIG_SYS_NOR_FTIM3    0x0
 250
 251 #define CONFIG_SYS_FLASH_QUIET_TEST
 252 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 253
 254 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 255 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 256 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 257
 258 #define CONFIG_SYS_FLASH_EMPTY_INFO
 259 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 260                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 261
 262 /* NAND Flash on IFC */
 263 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 264 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 265 #define CONFIG_SYS_NAND_BASE            0xff800000
 266 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 267
 268 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 269 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 270                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 271                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 272                                 | CSPR_V)
 273 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 274
 275 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 276                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 277                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 278                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 279                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 280                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 281                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 282
 283 /* ONFI NAND Flash mode0 Timing Params */
 284 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 285                                         FTIM0_NAND_TWP(0x18)   | \
 286                                         FTIM0_NAND_TWCHT(0x07) | \
 287                                         FTIM0_NAND_TWH(0x0a))
 288 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 289                                         FTIM1_NAND_TWBE(0x39)  | \
 290                                         FTIM1_NAND_TRR(0x0e)   | \
 291                                         FTIM1_NAND_TRP(0x18))
 292 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 293                                         FTIM2_NAND_TREH(0x0a) | \
 294                                         FTIM2_NAND_TWHRE(0x1e))
 295 #define CONFIG_SYS_NAND_FTIM3           0x0
 296
 297 #define CONFIG_SYS_NAND_DDR_LAW         11
 298 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 299 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 300
 301 #if defined(CONFIG_MTD_RAW_NAND)
 302 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 303 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 304 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 305 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 306 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 307 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 308 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 309 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 310 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 311 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 312 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 313 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 314 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 315 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 316 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 317 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 318 #else
 319 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 320 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 321 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 322 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 323 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 324 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 325 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 326 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 327 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 328 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 329 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 330 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 331 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 332 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 333 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 334 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 335 #endif
 336 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 337 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 338 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 339 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 340 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 341 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 342 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 343 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 344
 345 /* CPLD on IFC */
 346 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 347 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 348 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 349 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 350                                 | CSPR_PORT_SIZE_8 \
 351                                 | CSPR_MSEL_GPCM \
 352                                 | CSPR_V)
 353
 354 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 355 #define CONFIG_SYS_CSOR3        0x0
 356
 357 /* CPLD Timing parameters for IFC CS3 */
 358 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 359                                         FTIM0_GPCM_TEADC(0x0e) | \
 360                                         FTIM0_GPCM_TEAHC(0x0e))
 361 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 362                                         FTIM1_GPCM_TRAD(0x1f))
 363 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 364                                         FTIM2_GPCM_TCH(0x8) | \
 365                                         FTIM2_GPCM_TWP(0x1f))
 366 #define CONFIG_SYS_CS3_FTIM3            0x0
 367
 368 #if defined(CONFIG_RAMBOOT_PBL)
 369 #define CONFIG_SYS_RAMBOOT
 370 #endif
 371
 372 /* I2C */
 373 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 374 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 375
 376 #define I2C_MUX_CH_DEFAULT      0x8
 377 #define I2C_MUX_CH_VOL_MONITOR  0xa
 378 #define I2C_MUX_CH_VSC3316_FS   0xc
 379 #define I2C_MUX_CH_VSC3316_BS   0xd
 380
 381 /* Voltage monitor on channel 2*/
 382 #define I2C_VOL_MONITOR_ADDR            0x40
 383 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 384 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 385 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 386
 387 /* The lowest and highest voltage allowed for T4240RDB */
 388 #define VDD_MV_MIN                      819
 389 #define VDD_MV_MAX                      1212
 390
 391 /*
 392  * eSPI - Enhanced SPI
 393  */
 394
 395 /* Qman/Bman */
 396 #ifndef CONFIG_NOBQFMAN
 397 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 398 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 399 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 400 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 401 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 402 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 403 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 404 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 405 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 406                                         CONFIG_SYS_BMAN_CENA_SIZE)
 407 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 408 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 409 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 410 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 411 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 412 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 413 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 414 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 415 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 416 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 417 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 418                                         CONFIG_SYS_QMAN_CENA_SIZE)
 419 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 420 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 421
 422 #define CONFIG_SYS_DPAA_FMAN
 423 #define CONFIG_SYS_DPAA_PME
 424 #define CONFIG_SYS_PMAN
 425 #define CONFIG_SYS_DPAA_DCE
 426 #define CONFIG_SYS_DPAA_RMAN
 427 #define CONFIG_SYS_INTERLAKEN
 428
 429 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 430 #endif /* CONFIG_NOBQFMAN */
 431
 432 #ifdef CONFIG_SYS_DPAA_FMAN
 433 #define SGMII_PHY_ADDR1 0x0
 434 #define SGMII_PHY_ADDR2 0x1
 435 #define SGMII_PHY_ADDR3 0x2
 436 #define SGMII_PHY_ADDR4 0x3
 437 #define SGMII_PHY_ADDR5 0x4
 438 #define SGMII_PHY_ADDR6 0x5
 439 #define SGMII_PHY_ADDR7 0x6
 440 #define SGMII_PHY_ADDR8 0x7
 441 #define FM1_10GEC1_PHY_ADDR     0x10
 442 #define FM1_10GEC2_PHY_ADDR     0x11
 443 #define FM2_10GEC1_PHY_ADDR     0x12
 444 #define FM2_10GEC2_PHY_ADDR     0x13
 445 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 446 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 447 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 448 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 449 #endif
 450
 451 /* SATA */
 452 #ifdef CONFIG_FSL_SATA_V2
 453 #define CONFIG_SATA1
 454 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 455 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 456 #define CONFIG_SATA2
 457 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 458 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 459
 460 #define CONFIG_LBA48
 461 #endif
 462
 463 /*
 464 * USB
 465 */
 466 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 467 #define CONFIG_HAS_FSL_DR_USB
 468
 469 #ifdef CONFIG_MMC
 470 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 471 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 472 #endif
 473
 474
 475 #define __USB_PHY_TYPE  utmi
 476
 477 /*
 478  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 479  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 480  * interleaving. It can be cacheline, page, bank, superbank.
 481  * See doc/README.fsl-ddr for details.
 482  */
 483 #ifdef CONFIG_ARCH_T4240
 484 #define CTRL_INTLV_PREFERED 3way_4KB
 485 #else
 486 #define CTRL_INTLV_PREFERED cacheline
 487 #endif
 488
 489 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 490         "hwconfig=fsl_ddr:"                                     \
 491         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 492         "bank_intlv=auto;"                                      \
 493         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 494         "netdev=eth0\0"                                         \
 495         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 496         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 497         "tftpflash=tftpboot $loadaddr $uboot && "               \
 498         "protect off $ubootaddr +$filesize && "                 \
 499         "erase $ubootaddr +$filesize && "                       \
 500         "cp.b $loadaddr $ubootaddr $filesize && "               \
 501         "protect on $ubootaddr +$filesize && "                  \
 502         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 503         "consoledev=ttyS0\0"                                    \
 504         "ramdiskaddr=2000000\0"                                 \
 505         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 506         "fdtaddr=1e00000\0"                                     \
 507         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 508         "bdev=sda3\0"
 509
 510 #define HVBOOT                                  \
 511         "setenv bootargs config-addr=0x60000000; "      \
 512         "bootm 0x01000000 - 0x00f00000"
 513
 514 #include <asm/fsl_secure_boot.h>
 515
 516 #endif  /* __CONFIG_H */