1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T4240 RDB board configuration file
13 #include <linux/stringify.h>
15 #define CONFIG_FSL_SATA_V2
18 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
20 #ifdef CONFIG_RAMBOOT_PBL
22 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
23 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
25 #define CONFIG_SPL_FLUSH_IMAGE
26 #define CONFIG_SPL_PAD_TO 0x40000
27 #define CONFIG_SPL_MAX_SIZE 0x28000
28 #define RESET_VECTOR_OFFSET 0x27FFC
29 #define BOOT_PAGE_OFFSET 0x27000
32 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
33 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
34 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
35 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
36 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
37 #ifndef CONFIG_SPL_BUILD
38 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
42 #ifdef CONFIG_SPL_BUILD
43 #define CONFIG_SPL_SKIP_RELOCATE
44 #define CONFIG_SPL_COMMON_INIT_DDR
45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
49 #endif /* CONFIG_RAMBOOT_PBL */
51 /* High Level Configuration Options */
52 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
54 #ifndef CONFIG_RESET_VECTOR_ADDRESS
55 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
58 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
59 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
60 #define CONFIG_PCIE1 /* PCIE controller 1 */
61 #define CONFIG_PCIE2 /* PCIE controller 2 */
62 #define CONFIG_PCIE3 /* PCIE controller 3 */
65 * These can be toggled for performance analysis, otherwise use default.
67 #define CONFIG_SYS_CACHE_STASHING
68 #define CONFIG_BTB /* toggle branch predition */
70 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
73 #define CONFIG_ENABLE_36BIT_PHYS
76 * Config the L3 Cache as L3 SRAM
78 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
79 #define CONFIG_SYS_L3_SIZE (512 << 10)
80 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
81 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
82 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
83 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
84 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
86 #define CONFIG_SYS_DCSRBAR 0xf0000000
87 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
92 #define CONFIG_VERY_BIG_RAM
93 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
96 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
97 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
102 #define CONFIG_SYS_FLASH_BASE 0xe0000000
103 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
105 #ifdef CONFIG_SPL_BUILD
106 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
108 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
111 #define CONFIG_HWCONFIG
113 /* define to use L1 as initial stack */
114 #define CONFIG_L1_INIT_RAM
115 #define CONFIG_SYS_INIT_RAM_LOCK
116 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
117 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
118 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
119 /* The assembler doesn't like typecast */
120 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
121 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
122 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
123 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
125 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
126 GENERATED_GBL_DATA_SIZE)
127 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
129 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
131 /* Serial Port - controlled on board with jumper J8
135 #define CONFIG_SYS_NS16550_SERIAL
136 #define CONFIG_SYS_NS16550_REG_SIZE 1
137 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
139 #define CONFIG_SYS_BAUDRATE_TABLE \
140 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
142 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
143 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
144 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
145 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
151 * Memory space is mapped 1-1, but I/O space must start from 0.
154 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
155 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
156 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
157 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
158 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
160 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
161 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
162 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
163 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
164 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
166 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
167 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
168 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
169 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
170 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
172 /* controller 4, Base address 203000 */
173 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
174 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
175 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
178 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
179 #endif /* CONFIG_PCI */
182 #ifdef CONFIG_FSL_SATA_V2
183 #define CONFIG_SYS_SATA_MAX_DEVICE 2
185 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
186 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
188 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
189 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
194 #ifdef CONFIG_FMAN_ENET
195 #define CONFIG_ETHPRIME "FM1@DTSEC1"
201 #define CONFIG_LOADS_ECHO /* echo on for serial download */
202 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
205 * Miscellaneous configurable options
209 * For booting Linux, the board info and command line data
210 * have to be in the first 64 MB of memory, since this is
211 * the maximum mapped by the Linux kernel during initialization.
213 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
214 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
217 * Environment Configuration
219 #define CONFIG_ROOTPATH "/opt/nfsroot"
220 #define CONFIG_BOOTFILE "uImage"
221 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
224 "setenv bootargs config-addr=0x60000000; " \
225 "bootm 0x01000000 - 0x00f00000"
227 #define CONFIG_SYS_CLK_FREQ 66666666
230 unsigned long get_board_sys_clk(void);
236 #define CONFIG_SYS_SPD_BUS_NUM 0
237 #define SPD_EEPROM_ADDRESS1 0x52
238 #define SPD_EEPROM_ADDRESS2 0x54
239 #define SPD_EEPROM_ADDRESS3 0x56
240 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
241 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
246 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
247 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
249 CSPR_PORT_SIZE_16 | \
252 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
253 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
254 CSPR_PORT_SIZE_16 | \
257 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
258 /* NOR Flash Timing Params */
259 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
261 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
262 FTIM0_NOR_TEADC(0x5) | \
263 FTIM0_NOR_TEAHC(0x5))
264 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
265 FTIM1_NOR_TRAD_NOR(0x1A) |\
266 FTIM1_NOR_TSEQRAD_NOR(0x13))
267 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
268 FTIM2_NOR_TCH(0x4) | \
269 FTIM2_NOR_TWPH(0x0E) | \
271 #define CONFIG_SYS_NOR_FTIM3 0x0
273 #define CONFIG_SYS_FLASH_QUIET_TEST
274 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
276 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
277 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
278 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
279 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
281 #define CONFIG_SYS_FLASH_EMPTY_INFO
282 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
283 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
285 /* NAND Flash on IFC */
286 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
287 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
288 #define CONFIG_SYS_NAND_BASE 0xff800000
289 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
291 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
292 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
293 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
294 | CSPR_MSEL_NAND /* MSEL = NAND */ \
296 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
298 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
299 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
300 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
301 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
302 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
303 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
304 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
306 /* ONFI NAND Flash mode0 Timing Params */
307 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
308 FTIM0_NAND_TWP(0x18) | \
309 FTIM0_NAND_TWCHT(0x07) | \
310 FTIM0_NAND_TWH(0x0a))
311 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
312 FTIM1_NAND_TWBE(0x39) | \
313 FTIM1_NAND_TRR(0x0e) | \
314 FTIM1_NAND_TRP(0x18))
315 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
316 FTIM2_NAND_TREH(0x0a) | \
317 FTIM2_NAND_TWHRE(0x1e))
318 #define CONFIG_SYS_NAND_FTIM3 0x0
320 #define CONFIG_SYS_NAND_DDR_LAW 11
321 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
322 #define CONFIG_SYS_MAX_NAND_DEVICE 1
324 #if defined(CONFIG_MTD_RAW_NAND)
325 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
326 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
327 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
328 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
329 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
330 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
331 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
332 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
333 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
334 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
335 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
336 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
337 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
338 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
339 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
340 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
342 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
343 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
344 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
345 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
346 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
347 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
348 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
349 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
350 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
351 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
352 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
353 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
354 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
355 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
356 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
357 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
359 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
360 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
361 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
362 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
363 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
364 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
365 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
366 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
369 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
370 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
371 #define CONFIG_SYS_CSPR3_EXT (0xf)
372 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
377 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
378 #define CONFIG_SYS_CSOR3 0x0
380 /* CPLD Timing parameters for IFC CS3 */
381 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
382 FTIM0_GPCM_TEADC(0x0e) | \
383 FTIM0_GPCM_TEAHC(0x0e))
384 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
385 FTIM1_GPCM_TRAD(0x1f))
386 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
387 FTIM2_GPCM_TCH(0x8) | \
388 FTIM2_GPCM_TWP(0x1f))
389 #define CONFIG_SYS_CS3_FTIM3 0x0
391 #if defined(CONFIG_RAMBOOT_PBL)
392 #define CONFIG_SYS_RAMBOOT
396 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
397 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
399 #define I2C_MUX_CH_DEFAULT 0x8
400 #define I2C_MUX_CH_VOL_MONITOR 0xa
401 #define I2C_MUX_CH_VSC3316_FS 0xc
402 #define I2C_MUX_CH_VSC3316_BS 0xd
404 /* Voltage monitor on channel 2*/
405 #define I2C_VOL_MONITOR_ADDR 0x40
406 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
407 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
408 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
410 /* The lowest and highest voltage allowed for T4240RDB */
411 #define VDD_MV_MIN 819
412 #define VDD_MV_MAX 1212
415 * eSPI - Enhanced SPI
419 #ifndef CONFIG_NOBQFMAN
420 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
421 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
422 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
423 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
424 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
425 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
426 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
427 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
428 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
429 CONFIG_SYS_BMAN_CENA_SIZE)
430 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
431 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
432 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
433 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
434 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
435 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
436 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
437 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
438 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
439 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
440 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
441 CONFIG_SYS_QMAN_CENA_SIZE)
442 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
443 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
445 #define CONFIG_SYS_DPAA_FMAN
446 #define CONFIG_SYS_DPAA_PME
447 #define CONFIG_SYS_PMAN
448 #define CONFIG_SYS_DPAA_DCE
449 #define CONFIG_SYS_DPAA_RMAN
450 #define CONFIG_SYS_INTERLAKEN
452 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
453 #endif /* CONFIG_NOBQFMAN */
455 #ifdef CONFIG_SYS_DPAA_FMAN
456 #define SGMII_PHY_ADDR1 0x0
457 #define SGMII_PHY_ADDR2 0x1
458 #define SGMII_PHY_ADDR3 0x2
459 #define SGMII_PHY_ADDR4 0x3
460 #define SGMII_PHY_ADDR5 0x4
461 #define SGMII_PHY_ADDR6 0x5
462 #define SGMII_PHY_ADDR7 0x6
463 #define SGMII_PHY_ADDR8 0x7
464 #define FM1_10GEC1_PHY_ADDR 0x10
465 #define FM1_10GEC2_PHY_ADDR 0x11
466 #define FM2_10GEC1_PHY_ADDR 0x12
467 #define FM2_10GEC2_PHY_ADDR 0x13
468 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
469 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
470 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
471 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
475 #ifdef CONFIG_FSL_SATA_V2
476 #define CONFIG_SYS_SATA_MAX_DEVICE 2
478 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
479 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
481 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
482 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
487 #ifdef CONFIG_FMAN_ENET
488 #define CONFIG_ETHPRIME "FM1@DTSEC1"
494 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
495 #define CONFIG_HAS_FSL_DR_USB
498 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
499 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
503 #define __USB_PHY_TYPE utmi
506 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
507 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
508 * interleaving. It can be cacheline, page, bank, superbank.
509 * See doc/README.fsl-ddr for details.
511 #ifdef CONFIG_ARCH_T4240
512 #define CTRL_INTLV_PREFERED 3way_4KB
514 #define CTRL_INTLV_PREFERED cacheline
517 #define CONFIG_EXTRA_ENV_SETTINGS \
518 "hwconfig=fsl_ddr:" \
519 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
521 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
523 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
524 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
525 "tftpflash=tftpboot $loadaddr $uboot && " \
526 "protect off $ubootaddr +$filesize && " \
527 "erase $ubootaddr +$filesize && " \
528 "cp.b $loadaddr $ubootaddr $filesize && " \
529 "protect on $ubootaddr +$filesize && " \
530 "cmp.b $loadaddr $ubootaddr $filesize\0" \
531 "consoledev=ttyS0\0" \
532 "ramdiskaddr=2000000\0" \
533 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
534 "fdtaddr=1e00000\0" \
535 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
539 "setenv bootargs config-addr=0x60000000; " \
540 "bootm 0x01000000 - 0x00f00000"
542 #include <asm/fsl_secure_boot.h>
544 #endif /* __CONFIG_H */