2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T4240 RDB board configuration file
13 #define CONFIG_T4240RDB
14 #define CONFIG_PHYS_64BIT
15 #define CONFIG_SYS_GENERIC_BOARD
16 #define CONFIG_DISPLAY_BOARDINFO
18 #define CONFIG_FSL_SATA_V2
21 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
23 #ifdef CONFIG_RAMBOOT_PBL
24 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
25 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
27 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
30 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
31 #define CONFIG_SPL_ENV_SUPPORT
32 #define CONFIG_SPL_SERIAL_SUPPORT
33 #define CONFIG_SPL_FLUSH_IMAGE
34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
35 #define CONFIG_SPL_LIBGENERIC_SUPPORT
36 #define CONFIG_SPL_LIBCOMMON_SUPPORT
37 #define CONFIG_SPL_I2C_SUPPORT
38 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
39 #define CONFIG_FSL_LAW /* Use common FSL init code */
40 #define CONFIG_SYS_TEXT_BASE 0x00201000
41 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
42 #define CONFIG_SPL_PAD_TO 0x40000
43 #define CONFIG_SPL_MAX_SIZE 0x28000
44 #define RESET_VECTOR_OFFSET 0x27FFC
45 #define BOOT_PAGE_OFFSET 0x27000
48 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
49 #define CONFIG_SPL_MMC_SUPPORT
50 #define CONFIG_SPL_MMC_MINIMAL
51 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
52 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
53 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
54 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
55 #ifndef CONFIG_SPL_BUILD
56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
59 #define CONFIG_SPL_MMC_BOOT
62 #ifdef CONFIG_SPL_BUILD
63 #define CONFIG_SPL_SKIP_RELOCATE
64 #define CONFIG_SPL_COMMON_INIT_DDR
65 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
66 #define CONFIG_SYS_NO_FLASH
70 #endif /* CONFIG_RAMBOOT_PBL */
72 #define CONFIG_DDR_ECC
74 #define CONFIG_CMD_REGINFO
76 /* High Level Configuration Options */
78 #define CONFIG_E500 /* BOOKE e500 family */
79 #define CONFIG_E500MC /* BOOKE e500mc family */
80 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
81 #define CONFIG_MP /* support multiple processors */
83 #ifndef CONFIG_SYS_TEXT_BASE
84 #define CONFIG_SYS_TEXT_BASE 0xeff40000
87 #ifndef CONFIG_RESET_VECTOR_ADDRESS
88 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
91 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
92 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
93 #define CONFIG_FSL_IFC /* Enable IFC Support */
94 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
95 #define CONFIG_PCI /* Enable PCI/PCIE */
96 #define CONFIG_PCIE1 /* PCIE controler 1 */
97 #define CONFIG_PCIE2 /* PCIE controler 2 */
98 #define CONFIG_PCIE3 /* PCIE controler 3 */
99 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
100 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
102 #define CONFIG_FSL_LAW /* Use common FSL init code */
104 #define CONFIG_ENV_OVERWRITE
107 * These can be toggled for performance analysis, otherwise use default.
109 #define CONFIG_SYS_CACHE_STASHING
110 #define CONFIG_BTB /* toggle branch predition */
111 #ifdef CONFIG_DDR_ECC
112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
113 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
116 #define CONFIG_ENABLE_36BIT_PHYS
118 #define CONFIG_ADDR_MAP
119 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
121 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
122 #define CONFIG_SYS_MEMTEST_END 0x00400000
123 #define CONFIG_SYS_ALT_MEMTEST
124 #define CONFIG_PANIC_HANG /* do not reset board on panic */
127 * Config the L3 Cache as L3 SRAM
129 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
130 #define CONFIG_SYS_L3_SIZE (512 << 10)
131 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
132 #ifdef CONFIG_RAMBOOT_PBL
133 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
135 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
136 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
137 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
138 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
140 #define CONFIG_SYS_DCSRBAR 0xf0000000
141 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
146 #define CONFIG_VERY_BIG_RAM
147 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
148 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
150 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
151 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
152 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
153 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
155 #define CONFIG_DDR_SPD
156 #define CONFIG_SYS_FSL_DDR3
162 #define CONFIG_SYS_FLASH_BASE 0xe0000000
163 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
166 #ifdef CONFIG_SPL_BUILD
167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
172 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
173 #define CONFIG_MISC_INIT_R
175 #define CONFIG_HWCONFIG
177 /* define to use L1 as initial stack */
178 #define CONFIG_L1_INIT_RAM
179 #define CONFIG_SYS_INIT_RAM_LOCK
180 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
182 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
183 /* The assembler doesn't like typecast */
184 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
185 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
186 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
187 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
189 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
190 GENERATED_GBL_DATA_SIZE)
191 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
193 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
194 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
196 /* Serial Port - controlled on board with jumper J8
200 #define CONFIG_CONS_INDEX 1
201 #define CONFIG_SYS_NS16550
202 #define CONFIG_SYS_NS16550_SERIAL
203 #define CONFIG_SYS_NS16550_REG_SIZE 1
204 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
206 #define CONFIG_SYS_BAUDRATE_TABLE \
207 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
209 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
210 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
211 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
212 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
214 /* Use the HUSH parser */
215 #define CONFIG_SYS_HUSH_PARSER
216 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
218 /* pass open firmware flat tree */
219 #define CONFIG_OF_LIBFDT
220 #define CONFIG_OF_BOARD_SETUP
221 #define CONFIG_OF_STDOUT_VIA_ALIAS
223 /* new uImage format support */
225 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
228 #define CONFIG_SYS_I2C
229 #define CONFIG_SYS_I2C_FSL
230 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
231 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
232 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
233 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
237 * Memory space is mapped 1-1, but I/O space must start from 0.
240 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
241 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
242 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
243 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
244 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
245 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
246 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
247 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
248 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
250 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
251 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
252 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
253 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
254 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
255 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
256 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
257 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
258 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
260 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
261 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
262 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
263 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
264 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
265 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
266 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
267 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
268 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
270 /* controller 4, Base address 203000 */
271 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
272 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
273 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
274 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
275 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
276 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
279 #define CONFIG_PCI_INDIRECT_BRIDGE
280 #define CONFIG_NET_MULTI
281 #define CONFIG_PCI_PNP /* do pci plug-and-play */
284 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
285 #define CONFIG_DOS_PARTITION
286 #endif /* CONFIG_PCI */
289 #ifdef CONFIG_FSL_SATA_V2
290 #define CONFIG_LIBATA
291 #define CONFIG_FSL_SATA
293 #define CONFIG_SYS_SATA_MAX_DEVICE 2
295 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
296 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
298 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
299 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
302 #define CONFIG_CMD_SATA
303 #define CONFIG_DOS_PARTITION
304 #define CONFIG_CMD_EXT2
307 #ifdef CONFIG_FMAN_ENET
308 #define CONFIG_MII /* MII PHY management */
309 #define CONFIG_ETHPRIME "FM1@DTSEC1"
310 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
316 #define CONFIG_LOADS_ECHO /* echo on for serial download */
317 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
320 * Command line configuration.
322 #include <config_cmd_default.h>
324 #define CONFIG_CMD_DHCP
325 #define CONFIG_CMD_ELF
326 #define CONFIG_CMD_ERRATA
327 #define CONFIG_CMD_GREPENV
328 #define CONFIG_CMD_IRQ
329 #define CONFIG_CMD_I2C
330 #define CONFIG_CMD_MII
331 #define CONFIG_CMD_PING
334 #define CONFIG_CMD_PCI
335 #define CONFIG_CMD_NET
339 * Miscellaneous configurable options
341 #define CONFIG_SYS_LONGHELP /* undef to save memory */
342 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
343 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
344 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
345 #ifdef CONFIG_CMD_KGDB
346 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
348 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
350 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
351 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
352 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
355 * For booting Linux, the board info and command line data
356 * have to be in the first 64 MB of memory, since this is
357 * the maximum mapped by the Linux kernel during initialization.
359 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
360 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
362 #ifdef CONFIG_CMD_KGDB
363 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
367 * Environment Configuration
369 #define CONFIG_ROOTPATH "/opt/nfsroot"
370 #define CONFIG_BOOTFILE "uImage"
371 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
373 /* default location for tftp and bootm */
374 #define CONFIG_LOADADDR 1000000
377 #define CONFIG_BAUDRATE 115200
379 #define CONFIG_HVBOOT \
380 "setenv bootargs config-addr=0x60000000; " \
381 "bootm 0x01000000 - 0x00f00000"
383 #ifdef CONFIG_SYS_NO_FLASH
384 #ifndef CONFIG_RAMBOOT_PBL
385 #define CONFIG_ENV_IS_NOWHERE
388 #define CONFIG_FLASH_CFI_DRIVER
389 #define CONFIG_SYS_FLASH_CFI
390 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
393 #if defined(CONFIG_SPIFLASH)
394 #define CONFIG_SYS_EXTRA_ENV_RELOC
395 #define CONFIG_ENV_IS_IN_SPI_FLASH
396 #define CONFIG_ENV_SPI_BUS 0
397 #define CONFIG_ENV_SPI_CS 0
398 #define CONFIG_ENV_SPI_MAX_HZ 10000000
399 #define CONFIG_ENV_SPI_MODE 0
400 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
401 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
402 #define CONFIG_ENV_SECT_SIZE 0x10000
403 #elif defined(CONFIG_SDCARD)
404 #define CONFIG_SYS_EXTRA_ENV_RELOC
405 #define CONFIG_ENV_IS_IN_MMC
406 #define CONFIG_SYS_MMC_ENV_DEV 0
407 #define CONFIG_ENV_SIZE 0x2000
408 #define CONFIG_ENV_OFFSET (512 * 0x800)
409 #elif defined(CONFIG_NAND)
410 #define CONFIG_SYS_EXTRA_ENV_RELOC
411 #define CONFIG_ENV_IS_IN_NAND
412 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
413 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
414 #elif defined(CONFIG_ENV_IS_NOWHERE)
415 #define CONFIG_ENV_SIZE 0x2000
417 #define CONFIG_ENV_IS_IN_FLASH
418 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
419 #define CONFIG_ENV_SIZE 0x2000
420 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
423 #define CONFIG_SYS_CLK_FREQ 66666666
424 #define CONFIG_DDR_CLK_FREQ 133333333
427 unsigned long get_board_sys_clk(void);
428 unsigned long get_board_ddr_clk(void);
434 #define CONFIG_SYS_SPD_BUS_NUM 0
435 #define SPD_EEPROM_ADDRESS1 0x52
436 #define SPD_EEPROM_ADDRESS2 0x54
437 #define SPD_EEPROM_ADDRESS3 0x56
438 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
439 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
444 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
445 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
447 CSPR_PORT_SIZE_16 | \
450 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
451 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
452 CSPR_PORT_SIZE_16 | \
455 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
456 /* NOR Flash Timing Params */
457 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
459 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
460 FTIM0_NOR_TEADC(0x5) | \
461 FTIM0_NOR_TEAHC(0x5))
462 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
463 FTIM1_NOR_TRAD_NOR(0x1A) |\
464 FTIM1_NOR_TSEQRAD_NOR(0x13))
465 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
466 FTIM2_NOR_TCH(0x4) | \
467 FTIM2_NOR_TWPH(0x0E) | \
469 #define CONFIG_SYS_NOR_FTIM3 0x0
471 #define CONFIG_SYS_FLASH_QUIET_TEST
472 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
474 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
475 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
476 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
477 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
479 #define CONFIG_SYS_FLASH_EMPTY_INFO
480 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
481 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
483 /* NAND Flash on IFC */
484 #define CONFIG_NAND_FSL_IFC
485 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
486 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
487 #define CONFIG_SYS_NAND_BASE 0xff800000
488 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
490 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
491 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
492 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
493 | CSPR_MSEL_NAND /* MSEL = NAND */ \
495 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
497 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
498 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
499 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
500 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
501 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
502 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
503 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
505 #define CONFIG_SYS_NAND_ONFI_DETECTION
507 /* ONFI NAND Flash mode0 Timing Params */
508 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
509 FTIM0_NAND_TWP(0x18) | \
510 FTIM0_NAND_TWCHT(0x07) | \
511 FTIM0_NAND_TWH(0x0a))
512 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
513 FTIM1_NAND_TWBE(0x39) | \
514 FTIM1_NAND_TRR(0x0e) | \
515 FTIM1_NAND_TRP(0x18))
516 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
517 FTIM2_NAND_TREH(0x0a) | \
518 FTIM2_NAND_TWHRE(0x1e))
519 #define CONFIG_SYS_NAND_FTIM3 0x0
521 #define CONFIG_SYS_NAND_DDR_LAW 11
522 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
523 #define CONFIG_SYS_MAX_NAND_DEVICE 1
524 #define CONFIG_CMD_NAND
526 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
528 #if defined(CONFIG_NAND)
529 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
530 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
531 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
532 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
533 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
534 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
535 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
536 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
537 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
538 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
539 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
540 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
541 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
542 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
543 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
544 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
546 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
547 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
548 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
549 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
550 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
551 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
552 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
553 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
554 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
555 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
556 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
557 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
558 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
559 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
560 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
561 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
563 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
564 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
565 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
566 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
567 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
568 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
569 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
570 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
573 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
574 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
575 #define CONFIG_SYS_CSPR3_EXT (0xf)
576 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
581 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
582 #define CONFIG_SYS_CSOR3 0x0
584 /* CPLD Timing parameters for IFC CS3 */
585 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
586 FTIM0_GPCM_TEADC(0x0e) | \
587 FTIM0_GPCM_TEAHC(0x0e))
588 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
589 FTIM1_GPCM_TRAD(0x1f))
590 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
591 FTIM2_GPCM_TCH(0x8) | \
592 FTIM2_GPCM_TWP(0x1f))
593 #define CONFIG_SYS_CS3_FTIM3 0x0
595 #if defined(CONFIG_RAMBOOT_PBL)
596 #define CONFIG_SYS_RAMBOOT
601 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
602 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
603 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
604 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
606 #define I2C_MUX_CH_DEFAULT 0x8
607 #define I2C_MUX_CH_VOL_MONITOR 0xa
608 #define I2C_MUX_CH_VSC3316_FS 0xc
609 #define I2C_MUX_CH_VSC3316_BS 0xd
611 /* Voltage monitor on channel 2*/
612 #define I2C_VOL_MONITOR_ADDR 0x40
613 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
614 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
615 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
618 * eSPI - Enhanced SPI
620 #define CONFIG_FSL_ESPI
621 #define CONFIG_SPI_FLASH
622 #define CONFIG_SPI_FLASH_SST
623 #define CONFIG_CMD_SF
624 #define CONFIG_SF_DEFAULT_SPEED 10000000
625 #define CONFIG_SF_DEFAULT_MODE 0
629 #ifndef CONFIG_NOBQFMAN
630 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
631 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
632 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
633 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
634 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
635 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
636 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
637 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
638 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
639 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
640 CONFIG_SYS_BMAN_CENA_SIZE)
641 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
642 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
643 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
644 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
645 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
646 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
647 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
648 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
649 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
650 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
651 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
652 CONFIG_SYS_QMAN_CENA_SIZE)
653 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
654 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
656 #define CONFIG_SYS_DPAA_FMAN
657 #define CONFIG_SYS_DPAA_PME
658 #define CONFIG_SYS_PMAN
659 #define CONFIG_SYS_DPAA_DCE
660 #define CONFIG_SYS_DPAA_RMAN
661 #define CONFIG_SYS_INTERLAKEN
663 /* Default address of microcode for the Linux Fman driver */
664 #if defined(CONFIG_SPIFLASH)
666 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
667 * env, so we got 0x110000.
669 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
670 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
671 #elif defined(CONFIG_SDCARD)
673 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
674 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
675 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
677 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
678 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
679 #elif defined(CONFIG_NAND)
680 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
681 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
683 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
684 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
686 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
687 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
688 #endif /* CONFIG_NOBQFMAN */
690 #ifdef CONFIG_SYS_DPAA_FMAN
691 #define CONFIG_FMAN_ENET
692 #define CONFIG_PHYLIB_10G
693 #define CONFIG_PHY_VITESSE
694 #define CONFIG_PHY_CORTINA
695 #define CONFIG_SYS_CORTINA_FW_IN_NOR
696 #define CONFIG_CORTINA_FW_ADDR 0xefe00000
697 #define CONFIG_CORTINA_FW_LENGTH 0x40000
698 #define CONFIG_PHY_TERANETICS
699 #define SGMII_PHY_ADDR1 0x0
700 #define SGMII_PHY_ADDR2 0x1
701 #define SGMII_PHY_ADDR3 0x2
702 #define SGMII_PHY_ADDR4 0x3
703 #define SGMII_PHY_ADDR5 0x4
704 #define SGMII_PHY_ADDR6 0x5
705 #define SGMII_PHY_ADDR7 0x6
706 #define SGMII_PHY_ADDR8 0x7
707 #define FM1_10GEC1_PHY_ADDR 0x10
708 #define FM1_10GEC2_PHY_ADDR 0x11
709 #define FM2_10GEC1_PHY_ADDR 0x12
710 #define FM2_10GEC2_PHY_ADDR 0x13
711 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
712 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
713 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
714 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
719 #ifdef CONFIG_FSL_SATA_V2
720 #define CONFIG_LIBATA
721 #define CONFIG_FSL_SATA
723 #define CONFIG_SYS_SATA_MAX_DEVICE 2
725 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
726 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
728 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
729 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
732 #define CONFIG_CMD_SATA
733 #define CONFIG_DOS_PARTITION
734 #define CONFIG_CMD_EXT2
737 #ifdef CONFIG_FMAN_ENET
738 #define CONFIG_MII /* MII PHY management */
739 #define CONFIG_ETHPRIME "FM1@DTSEC1"
740 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
746 #define CONFIG_CMD_USB
747 #define CONFIG_USB_STORAGE
748 #define CONFIG_USB_EHCI
749 #define CONFIG_USB_EHCI_FSL
750 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
751 #define CONFIG_CMD_EXT2
752 #define CONFIG_HAS_FSL_DR_USB
757 #define CONFIG_FSL_ESDHC
758 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
759 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
760 #define CONFIG_CMD_MMC
761 #define CONFIG_GENERIC_MMC
762 #define CONFIG_CMD_EXT2
763 #define CONFIG_CMD_FAT
764 #define CONFIG_DOS_PARTITION
765 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
768 /* Hash command with SHA acceleration supported in hardware */
769 #ifdef CONFIG_FSL_CAAM
770 #define CONFIG_CMD_HASH
771 #define CONFIG_SHA_HW_ACCEL
774 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
776 #define __USB_PHY_TYPE utmi
779 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
780 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
781 * interleaving. It can be cacheline, page, bank, superbank.
782 * See doc/README.fsl-ddr for details.
784 #ifdef CONFIG_PPC_T4240
785 #define CTRL_INTLV_PREFERED 3way_4KB
787 #define CTRL_INTLV_PREFERED cacheline
790 #define CONFIG_EXTRA_ENV_SETTINGS \
791 "hwconfig=fsl_ddr:" \
792 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
794 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
796 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
797 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
798 "tftpflash=tftpboot $loadaddr $uboot && " \
799 "protect off $ubootaddr +$filesize && " \
800 "erase $ubootaddr +$filesize && " \
801 "cp.b $loadaddr $ubootaddr $filesize && " \
802 "protect on $ubootaddr +$filesize && " \
803 "cmp.b $loadaddr $ubootaddr $filesize\0" \
804 "consoledev=ttyS0\0" \
805 "ramdiskaddr=2000000\0" \
806 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
808 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
811 #define CONFIG_HVBOOT \
812 "setenv bootargs config-addr=0x60000000; " \
813 "bootm 0x01000000 - 0x00f00000"
815 #define CONFIG_LINUX \
816 "setenv bootargs root=/dev/ram rw " \
817 "console=$consoledev,$baudrate $othbootargs;" \
818 "setenv ramdiskaddr 0x02000000;" \
819 "setenv fdtaddr 0x00c00000;" \
820 "setenv loadaddr 0x1000000;" \
821 "bootm $loadaddr $ramdiskaddr $fdtaddr"
823 #define CONFIG_HDBOOT \
824 "setenv bootargs root=/dev/$bdev rw " \
825 "console=$consoledev,$baudrate $othbootargs;" \
826 "tftp $loadaddr $bootfile;" \
827 "tftp $fdtaddr $fdtfile;" \
828 "bootm $loadaddr - $fdtaddr"
830 #define CONFIG_NFSBOOTCOMMAND \
831 "setenv bootargs root=/dev/nfs rw " \
832 "nfsroot=$serverip:$rootpath " \
833 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
834 "console=$consoledev,$baudrate $othbootargs;" \
835 "tftp $loadaddr $bootfile;" \
836 "tftp $fdtaddr $fdtfile;" \
837 "bootm $loadaddr - $fdtaddr"
839 #define CONFIG_RAMBOOTCOMMAND \
840 "setenv bootargs root=/dev/ram rw " \
841 "console=$consoledev,$baudrate $othbootargs;" \
842 "tftp $ramdiskaddr $ramdiskfile;" \
843 "tftp $loadaddr $bootfile;" \
844 "tftp $fdtaddr $fdtfile;" \
845 "bootm $loadaddr $ramdiskaddr $fdtaddr"
847 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
849 #include <asm/fsl_secure_boot.h>
851 #ifdef CONFIG_SECURE_BOOT
852 /* Secure Boot target was not getting build for T4240 because of
853 * increased binary size. So the size is being reduced by removing USB
854 * which is anyways not used in Secure Environment.
856 #undef CONFIG_CMD_USB
857 #define CONFIG_CMD_BLOB
860 #endif /* __CONFIG_H */