1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
8 * T4240 RDB board configuration file
13 #include <linux/stringify.h>
15 #define CONFIG_FSL_SATA_V2
18 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
20 #ifdef CONFIG_RAMBOOT_PBL
21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
26 #define CONFIG_SPL_FLUSH_IMAGE
27 #define CONFIG_SPL_PAD_TO 0x40000
28 #define CONFIG_SPL_MAX_SIZE 0x28000
29 #define RESET_VECTOR_OFFSET 0x27FFC
30 #define BOOT_PAGE_OFFSET 0x27000
33 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
34 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
35 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
36 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
37 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
38 #ifndef CONFIG_SPL_BUILD
39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
41 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
44 #ifdef CONFIG_SPL_BUILD
45 #define CONFIG_SPL_SKIP_RELOCATE
46 #define CONFIG_SPL_COMMON_INIT_DDR
47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
51 #endif /* CONFIG_RAMBOOT_PBL */
53 #define CONFIG_DDR_ECC
55 /* High Level Configuration Options */
56 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
63 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
64 #define CONFIG_PCIE1 /* PCIE controller 1 */
65 #define CONFIG_PCIE2 /* PCIE controller 2 */
66 #define CONFIG_PCIE3 /* PCIE controller 3 */
67 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
69 #define CONFIG_ENV_OVERWRITE
72 * These can be toggled for performance analysis, otherwise use default.
74 #define CONFIG_SYS_CACHE_STASHING
75 #define CONFIG_BTB /* toggle branch predition */
77 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
78 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
81 #define CONFIG_ENABLE_36BIT_PHYS
84 * Config the L3 Cache as L3 SRAM
86 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
87 #define CONFIG_SYS_L3_SIZE (512 << 10)
88 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
89 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
90 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
91 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
92 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
94 #define CONFIG_SYS_DCSRBAR 0xf0000000
95 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
100 #define CONFIG_VERY_BIG_RAM
101 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
102 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
104 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
105 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
107 #define CONFIG_DDR_SPD
112 #define CONFIG_SYS_FLASH_BASE 0xe0000000
113 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
115 #ifdef CONFIG_SPL_BUILD
116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
118 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
121 #define CONFIG_HWCONFIG
123 /* define to use L1 as initial stack */
124 #define CONFIG_L1_INIT_RAM
125 #define CONFIG_SYS_INIT_RAM_LOCK
126 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
127 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
128 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
129 /* The assembler doesn't like typecast */
130 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
131 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
132 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
133 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
135 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
136 GENERATED_GBL_DATA_SIZE)
137 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
139 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
140 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
142 /* Serial Port - controlled on board with jumper J8
146 #define CONFIG_SYS_NS16550_SERIAL
147 #define CONFIG_SYS_NS16550_REG_SIZE 1
148 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
150 #define CONFIG_SYS_BAUDRATE_TABLE \
151 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
153 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
154 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
155 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
156 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
159 #ifndef CONFIG_DM_I2C
160 #define CONFIG_SYS_I2C
161 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
162 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
163 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
164 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
166 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
167 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
170 #define CONFIG_SYS_I2C_FSL
174 * Memory space is mapped 1-1, but I/O space must start from 0.
177 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
178 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
179 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
180 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
181 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
183 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
184 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
185 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
186 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
187 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
189 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
190 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
191 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
192 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
193 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
195 /* controller 4, Base address 203000 */
196 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
197 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
198 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
201 #if !defined(CONFIG_DM_PCI)
202 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
203 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
204 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
205 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
206 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
207 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
208 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
209 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
210 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
211 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
212 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
213 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
214 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
215 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
216 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
217 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
218 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
219 #define CONFIG_PCI_INDIRECT_BRIDGE
222 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
223 #endif /* CONFIG_PCI */
226 #ifdef CONFIG_FSL_SATA_V2
227 #define CONFIG_SYS_SATA_MAX_DEVICE 2
229 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
230 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
232 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
233 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
238 #ifdef CONFIG_FMAN_ENET
239 #define CONFIG_ETHPRIME "FM1@DTSEC1"
245 #define CONFIG_LOADS_ECHO /* echo on for serial download */
246 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
249 * Miscellaneous configurable options
251 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
254 * For booting Linux, the board info and command line data
255 * have to be in the first 64 MB of memory, since this is
256 * the maximum mapped by the Linux kernel during initialization.
258 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
259 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
261 #ifdef CONFIG_CMD_KGDB
262 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
266 * Environment Configuration
268 #define CONFIG_ROOTPATH "/opt/nfsroot"
269 #define CONFIG_BOOTFILE "uImage"
270 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
272 /* default location for tftp and bootm */
273 #define CONFIG_LOADADDR 1000000
275 #define CONFIG_HVBOOT \
276 "setenv bootargs config-addr=0x60000000; " \
277 "bootm 0x01000000 - 0x00f00000"
279 #if defined(CONFIG_SPIFLASH)
280 #elif defined(CONFIG_SDCARD)
281 #define CONFIG_SYS_MMC_ENV_DEV 0
284 #define CONFIG_SYS_CLK_FREQ 66666666
285 #define CONFIG_DDR_CLK_FREQ 133333333
288 unsigned long get_board_sys_clk(void);
289 unsigned long get_board_ddr_clk(void);
295 #define CONFIG_SYS_SPD_BUS_NUM 0
296 #define SPD_EEPROM_ADDRESS1 0x52
297 #define SPD_EEPROM_ADDRESS2 0x54
298 #define SPD_EEPROM_ADDRESS3 0x56
299 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
300 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
305 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
306 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
308 CSPR_PORT_SIZE_16 | \
311 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
312 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
313 CSPR_PORT_SIZE_16 | \
316 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
317 /* NOR Flash Timing Params */
318 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
320 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
321 FTIM0_NOR_TEADC(0x5) | \
322 FTIM0_NOR_TEAHC(0x5))
323 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
324 FTIM1_NOR_TRAD_NOR(0x1A) |\
325 FTIM1_NOR_TSEQRAD_NOR(0x13))
326 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
327 FTIM2_NOR_TCH(0x4) | \
328 FTIM2_NOR_TWPH(0x0E) | \
330 #define CONFIG_SYS_NOR_FTIM3 0x0
332 #define CONFIG_SYS_FLASH_QUIET_TEST
333 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
335 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
336 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
337 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
338 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
340 #define CONFIG_SYS_FLASH_EMPTY_INFO
341 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
342 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
344 /* NAND Flash on IFC */
345 #define CONFIG_NAND_FSL_IFC
346 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
347 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
348 #define CONFIG_SYS_NAND_BASE 0xff800000
349 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
351 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
352 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
353 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
354 | CSPR_MSEL_NAND /* MSEL = NAND */ \
356 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
358 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
359 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
360 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
361 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
362 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
363 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
364 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
366 #define CONFIG_SYS_NAND_ONFI_DETECTION
368 /* ONFI NAND Flash mode0 Timing Params */
369 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
370 FTIM0_NAND_TWP(0x18) | \
371 FTIM0_NAND_TWCHT(0x07) | \
372 FTIM0_NAND_TWH(0x0a))
373 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
374 FTIM1_NAND_TWBE(0x39) | \
375 FTIM1_NAND_TRR(0x0e) | \
376 FTIM1_NAND_TRP(0x18))
377 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
378 FTIM2_NAND_TREH(0x0a) | \
379 FTIM2_NAND_TWHRE(0x1e))
380 #define CONFIG_SYS_NAND_FTIM3 0x0
382 #define CONFIG_SYS_NAND_DDR_LAW 11
383 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
384 #define CONFIG_SYS_MAX_NAND_DEVICE 1
386 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
388 #if defined(CONFIG_MTD_RAW_NAND)
389 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
390 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
391 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
392 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
393 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
394 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
395 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
396 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
397 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
398 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
399 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
400 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
401 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
402 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
403 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
404 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
406 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
407 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
408 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
409 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
410 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
411 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
412 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
413 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
414 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
415 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
416 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
417 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
418 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
419 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
420 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
421 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
423 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
424 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
425 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
426 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
427 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
428 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
429 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
430 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
433 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
434 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
435 #define CONFIG_SYS_CSPR3_EXT (0xf)
436 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
441 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
442 #define CONFIG_SYS_CSOR3 0x0
444 /* CPLD Timing parameters for IFC CS3 */
445 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
446 FTIM0_GPCM_TEADC(0x0e) | \
447 FTIM0_GPCM_TEAHC(0x0e))
448 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
449 FTIM1_GPCM_TRAD(0x1f))
450 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
451 FTIM2_GPCM_TCH(0x8) | \
452 FTIM2_GPCM_TWP(0x1f))
453 #define CONFIG_SYS_CS3_FTIM3 0x0
455 #if defined(CONFIG_RAMBOOT_PBL)
456 #define CONFIG_SYS_RAMBOOT
460 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
461 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
462 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
463 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
465 #define I2C_MUX_CH_DEFAULT 0x8
466 #define I2C_MUX_CH_VOL_MONITOR 0xa
467 #define I2C_MUX_CH_VSC3316_FS 0xc
468 #define I2C_MUX_CH_VSC3316_BS 0xd
470 /* Voltage monitor on channel 2*/
471 #define I2C_VOL_MONITOR_ADDR 0x40
472 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
473 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
474 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
476 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
477 #ifndef CONFIG_SPL_BUILD
480 #define CONFIG_VOL_MONITOR_IR36021_SET
481 #define CONFIG_VOL_MONITOR_IR36021_READ
482 /* The lowest and highest voltage allowed for T4240RDB */
483 #define VDD_MV_MIN 819
484 #define VDD_MV_MAX 1212
487 * eSPI - Enhanced SPI
491 #ifndef CONFIG_NOBQFMAN
492 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
493 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
494 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
495 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
496 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
497 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
498 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
499 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
500 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
501 CONFIG_SYS_BMAN_CENA_SIZE)
502 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
503 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
504 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
505 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
506 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
507 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
508 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
509 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
510 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
511 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
512 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
513 CONFIG_SYS_QMAN_CENA_SIZE)
514 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
515 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
517 #define CONFIG_SYS_DPAA_FMAN
518 #define CONFIG_SYS_DPAA_PME
519 #define CONFIG_SYS_PMAN
520 #define CONFIG_SYS_DPAA_DCE
521 #define CONFIG_SYS_DPAA_RMAN
522 #define CONFIG_SYS_INTERLAKEN
524 /* Default address of microcode for the Linux Fman driver */
525 #if defined(CONFIG_SPIFLASH)
527 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
528 * env, so we got 0x110000.
530 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
531 #elif defined(CONFIG_SDCARD)
533 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
534 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
535 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
537 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
538 #elif defined(CONFIG_MTD_RAW_NAND)
539 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
541 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
543 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
544 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
545 #endif /* CONFIG_NOBQFMAN */
547 #ifdef CONFIG_SYS_DPAA_FMAN
548 #define CONFIG_CORTINA_FW_ADDR 0xefe00000
549 #define CONFIG_CORTINA_FW_LENGTH 0x40000
550 #define SGMII_PHY_ADDR1 0x0
551 #define SGMII_PHY_ADDR2 0x1
552 #define SGMII_PHY_ADDR3 0x2
553 #define SGMII_PHY_ADDR4 0x3
554 #define SGMII_PHY_ADDR5 0x4
555 #define SGMII_PHY_ADDR6 0x5
556 #define SGMII_PHY_ADDR7 0x6
557 #define SGMII_PHY_ADDR8 0x7
558 #define FM1_10GEC1_PHY_ADDR 0x10
559 #define FM1_10GEC2_PHY_ADDR 0x11
560 #define FM2_10GEC1_PHY_ADDR 0x12
561 #define FM2_10GEC2_PHY_ADDR 0x13
562 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
563 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
564 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
565 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
569 #ifdef CONFIG_FSL_SATA_V2
570 #define CONFIG_SYS_SATA_MAX_DEVICE 2
572 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
573 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
575 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
576 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
581 #ifdef CONFIG_FMAN_ENET
582 #define CONFIG_ETHPRIME "FM1@DTSEC1"
588 #define CONFIG_USB_EHCI_FSL
589 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
590 #define CONFIG_HAS_FSL_DR_USB
593 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
594 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
595 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
599 #define __USB_PHY_TYPE utmi
602 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
603 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
604 * interleaving. It can be cacheline, page, bank, superbank.
605 * See doc/README.fsl-ddr for details.
607 #ifdef CONFIG_ARCH_T4240
608 #define CTRL_INTLV_PREFERED 3way_4KB
610 #define CTRL_INTLV_PREFERED cacheline
613 #define CONFIG_EXTRA_ENV_SETTINGS \
614 "hwconfig=fsl_ddr:" \
615 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
617 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
619 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
620 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
621 "tftpflash=tftpboot $loadaddr $uboot && " \
622 "protect off $ubootaddr +$filesize && " \
623 "erase $ubootaddr +$filesize && " \
624 "cp.b $loadaddr $ubootaddr $filesize && " \
625 "protect on $ubootaddr +$filesize && " \
626 "cmp.b $loadaddr $ubootaddr $filesize\0" \
627 "consoledev=ttyS0\0" \
628 "ramdiskaddr=2000000\0" \
629 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
630 "fdtaddr=1e00000\0" \
631 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
634 #define CONFIG_HVBOOT \
635 "setenv bootargs config-addr=0x60000000; " \
636 "bootm 0x01000000 - 0x00f00000"
638 #define CONFIG_LINUX \
639 "setenv bootargs root=/dev/ram rw " \
640 "console=$consoledev,$baudrate $othbootargs;" \
641 "setenv ramdiskaddr 0x02000000;" \
642 "setenv fdtaddr 0x00c00000;" \
643 "setenv loadaddr 0x1000000;" \
644 "bootm $loadaddr $ramdiskaddr $fdtaddr"
646 #define CONFIG_HDBOOT \
647 "setenv bootargs root=/dev/$bdev rw " \
648 "console=$consoledev,$baudrate $othbootargs;" \
649 "tftp $loadaddr $bootfile;" \
650 "tftp $fdtaddr $fdtfile;" \
651 "bootm $loadaddr - $fdtaddr"
653 #define CONFIG_NFSBOOTCOMMAND \
654 "setenv bootargs root=/dev/nfs rw " \
655 "nfsroot=$serverip:$rootpath " \
656 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
657 "console=$consoledev,$baudrate $othbootargs;" \
658 "tftp $loadaddr $bootfile;" \
659 "tftp $fdtaddr $fdtfile;" \
660 "bootm $loadaddr - $fdtaddr"
662 #define CONFIG_RAMBOOTCOMMAND \
663 "setenv bootargs root=/dev/ram rw " \
664 "console=$consoledev,$baudrate $othbootargs;" \
665 "tftp $ramdiskaddr $ramdiskfile;" \
666 "tftp $loadaddr $bootfile;" \
667 "tftp $fdtaddr $fdtfile;" \
668 "bootm $loadaddr $ramdiskaddr $fdtaddr"
670 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
672 #include <asm/fsl_secure_boot.h>
674 #endif /* __CONFIG_H */