Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
[platform/kernel/u-boot.git] / include / configs / T4240RDB.h
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * T4240 RDB board configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #define CONFIG_T4240RDB
14 #define CONFIG_PHYS_64BIT
15
16 #define CONFIG_FSL_SATA_V2
17 #define CONFIG_PCIE4
18
19 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
20
21 #ifdef CONFIG_RAMBOOT_PBL
22 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
23 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
24 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
25 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
26 #endif
27
28 #define CONFIG_DDR_ECC
29
30 #define CONFIG_CMD_REGINFO
31
32 /* High Level Configuration Options */
33 #define CONFIG_BOOKE
34 #define CONFIG_E500                     /* BOOKE e500 family */
35 #define CONFIG_E500MC                   /* BOOKE e500mc family */
36 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
37 #define CONFIG_MP                       /* support multiple processors */
38
39 #ifndef CONFIG_SYS_TEXT_BASE
40 #define CONFIG_SYS_TEXT_BASE    0xeff40000
41 #endif
42
43 #ifndef CONFIG_RESET_VECTOR_ADDRESS
44 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
45 #endif
46
47 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
48 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
49 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
50 #define CONFIG_PCI                      /* Enable PCI/PCIE */
51 #define CONFIG_PCIE1                    /* PCIE controler 1 */
52 #define CONFIG_PCIE2                    /* PCIE controler 2 */
53 #define CONFIG_PCIE3                    /* PCIE controler 3 */
54 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
55 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
56
57 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
58
59 #define CONFIG_ENV_OVERWRITE
60
61 /*
62  * These can be toggled for performance analysis, otherwise use default.
63  */
64 #define CONFIG_SYS_CACHE_STASHING
65 #define CONFIG_BTB                      /* toggle branch predition */
66 #ifdef CONFIG_DDR_ECC
67 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
68 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
69 #endif
70
71 #define CONFIG_ENABLE_36BIT_PHYS
72
73 #define CONFIG_ADDR_MAP
74 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
75
76 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
77 #define CONFIG_SYS_MEMTEST_END          0x00400000
78 #define CONFIG_SYS_ALT_MEMTEST
79 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
80
81 /*
82  *  Config the L3 Cache as L3 SRAM
83  */
84 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
85
86 #define CONFIG_SYS_DCSRBAR              0xf0000000
87 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
88
89 /*
90  * DDR Setup
91  */
92 #define CONFIG_VERY_BIG_RAM
93 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
94 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
95
96 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
97 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
98 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
99 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
100
101 #define CONFIG_DDR_SPD
102 #define CONFIG_SYS_FSL_DDR3
103
104
105 /*
106  * IFC Definitions
107  */
108 #define CONFIG_SYS_FLASH_BASE   0xe0000000
109 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
110
111
112 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
113
114 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
115 #define CONFIG_MISC_INIT_R
116
117 #define CONFIG_HWCONFIG
118
119 /* define to use L1 as initial stack */
120 #define CONFIG_L1_INIT_RAM
121 #define CONFIG_SYS_INIT_RAM_LOCK
122 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
123 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
124 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
125 /* The assembler doesn't like typecast */
126 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
127         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
128           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
129 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
130
131 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
132                                         GENERATED_GBL_DATA_SIZE)
133 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
134
135 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
136 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
137
138 /* Serial Port - controlled on board with jumper J8
139  * open - index 2
140  * shorted - index 1
141  */
142 #define CONFIG_CONS_INDEX       1
143 #define CONFIG_SYS_NS16550
144 #define CONFIG_SYS_NS16550_SERIAL
145 #define CONFIG_SYS_NS16550_REG_SIZE     1
146 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
147
148 #define CONFIG_SYS_BAUDRATE_TABLE       \
149         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
150
151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
153 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
154 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
155
156 /* Use the HUSH parser */
157 #define CONFIG_SYS_HUSH_PARSER
158 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
159
160 /* pass open firmware flat tree */
161 #define CONFIG_OF_LIBFDT
162 #define CONFIG_OF_BOARD_SETUP
163 #define CONFIG_OF_STDOUT_VIA_ALIAS
164
165 /* new uImage format support */
166 #define CONFIG_FIT
167 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
168
169 /* I2C */
170 #define CONFIG_SYS_I2C
171 #define CONFIG_SYS_I2C_FSL
172 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
173 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
174 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
175 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
176
177 /*
178  * General PCI
179  * Memory space is mapped 1-1, but I/O space must start from 0.
180  */
181
182 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
183 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
184 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
185 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
186 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
187 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
188 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
189 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
190 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
191
192 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
193 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
194 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
195 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
196 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
197 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
198 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
199 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
200 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
201
202 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
203 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
204 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
205 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
206 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
207 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
208 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
209 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
210 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
211
212 /* controller 4, Base address 203000 */
213 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
214 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
215 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
216 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
217 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
218 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
219
220 #ifdef CONFIG_PCI
221 #define CONFIG_PCI_INDIRECT_BRIDGE
222 #define CONFIG_NET_MULTI
223 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
224 #define CONFIG_E1000
225
226 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
227 #define CONFIG_DOS_PARTITION
228 #endif  /* CONFIG_PCI */
229
230 /* SATA */
231 #ifdef CONFIG_FSL_SATA_V2
232 #define CONFIG_LIBATA
233 #define CONFIG_FSL_SATA
234
235 #define CONFIG_SYS_SATA_MAX_DEVICE      2
236 #define CONFIG_SATA1
237 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
238 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
239 #define CONFIG_SATA2
240 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
241 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
242
243 #define CONFIG_LBA48
244 #define CONFIG_CMD_SATA
245 #define CONFIG_DOS_PARTITION
246 #define CONFIG_CMD_EXT2
247 #endif
248
249 #ifdef CONFIG_FMAN_ENET
250 #define CONFIG_MII              /* MII PHY management */
251 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
252 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
253 #endif
254
255 /*
256  * Environment
257  */
258 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
259 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
260
261 /*
262  * Command line configuration.
263  */
264 #include <config_cmd_default.h>
265
266 #define CONFIG_CMD_DHCP
267 #define CONFIG_CMD_ELF
268 #define CONFIG_CMD_ERRATA
269 #define CONFIG_CMD_GREPENV
270 #define CONFIG_CMD_IRQ
271 #define CONFIG_CMD_I2C
272 #define CONFIG_CMD_MII
273 #define CONFIG_CMD_PING
274 #define CONFIG_CMD_SETEXPR
275
276 #ifdef CONFIG_PCI
277 #define CONFIG_CMD_PCI
278 #define CONFIG_CMD_NET
279 #endif
280
281 /*
282  * Miscellaneous configurable options
283  */
284 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
285 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
286 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
287 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
288 #ifdef CONFIG_CMD_KGDB
289 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
290 #else
291 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
292 #endif
293 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
294 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
295 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
296
297 /*
298  * For booting Linux, the board info and command line data
299  * have to be in the first 64 MB of memory, since this is
300  * the maximum mapped by the Linux kernel during initialization.
301  */
302 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
303 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
304
305 #ifdef CONFIG_CMD_KGDB
306 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
307 #endif
308
309 /*
310  * Environment Configuration
311  */
312 #define CONFIG_ROOTPATH         "/opt/nfsroot"
313 #define CONFIG_BOOTFILE         "uImage"
314 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
315
316 /* default location for tftp and bootm */
317 #define CONFIG_LOADADDR         1000000
318
319
320 #define CONFIG_BAUDRATE 115200
321
322 #define CONFIG_HVBOOT                                   \
323         "setenv bootargs config-addr=0x60000000; "      \
324         "bootm 0x01000000 - 0x00f00000"
325
326 #ifdef CONFIG_SYS_NO_FLASH
327 #ifndef CONFIG_RAMBOOT_PBL
328 #define CONFIG_ENV_IS_NOWHERE
329 #endif
330 #else
331 #define CONFIG_FLASH_CFI_DRIVER
332 #define CONFIG_SYS_FLASH_CFI
333 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
334 #endif
335
336 #if defined(CONFIG_SPIFLASH)
337 #define CONFIG_SYS_EXTRA_ENV_RELOC
338 #define CONFIG_ENV_IS_IN_SPI_FLASH
339 #define CONFIG_ENV_SPI_BUS              0
340 #define CONFIG_ENV_SPI_CS               0
341 #define CONFIG_ENV_SPI_MAX_HZ           10000000
342 #define CONFIG_ENV_SPI_MODE             0
343 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
344 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
345 #define CONFIG_ENV_SECT_SIZE            0x10000
346 #elif defined(CONFIG_SDCARD)
347 #define CONFIG_SYS_EXTRA_ENV_RELOC
348 #define CONFIG_ENV_IS_IN_MMC
349 #define CONFIG_SYS_MMC_ENV_DEV          0
350 #define CONFIG_ENV_SIZE                 0x2000
351 #define CONFIG_ENV_OFFSET               (512 * 1658)
352 #elif defined(CONFIG_NAND)
353 #define CONFIG_SYS_EXTRA_ENV_RELOC
354 #define CONFIG_ENV_IS_IN_NAND
355 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
356 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
357 #elif defined(CONFIG_ENV_IS_NOWHERE)
358 #define CONFIG_ENV_SIZE         0x2000
359 #else
360 #define CONFIG_ENV_IS_IN_FLASH
361 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
362 #define CONFIG_ENV_SIZE         0x2000
363 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
364 #endif
365
366 #define CONFIG_SYS_CLK_FREQ     66666666
367 #define CONFIG_DDR_CLK_FREQ     133333333
368
369 #ifndef __ASSEMBLY__
370 unsigned long get_board_sys_clk(void);
371 unsigned long get_board_ddr_clk(void);
372 #endif
373
374 /*
375  * DDR Setup
376  */
377 #define CONFIG_SYS_SPD_BUS_NUM  0
378 #define SPD_EEPROM_ADDRESS1     0x52
379 #define SPD_EEPROM_ADDRESS2     0x54
380 #define SPD_EEPROM_ADDRESS3     0x56
381 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
382 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
383
384 /*
385  * IFC Definitions
386  */
387 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
388 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
389                                 + 0x8000000) | \
390                                 CSPR_PORT_SIZE_16 | \
391                                 CSPR_MSEL_NOR | \
392                                 CSPR_V)
393 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
394 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
395                                 CSPR_PORT_SIZE_16 | \
396                                 CSPR_MSEL_NOR | \
397                                 CSPR_V)
398 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
399 /* NOR Flash Timing Params */
400 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
401
402 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
403                                 FTIM0_NOR_TEADC(0x5) | \
404                                 FTIM0_NOR_TEAHC(0x5))
405 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
406                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
407                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
408 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
409                                 FTIM2_NOR_TCH(0x4) | \
410                                 FTIM2_NOR_TWPH(0x0E) | \
411                                 FTIM2_NOR_TWP(0x1c))
412 #define CONFIG_SYS_NOR_FTIM3    0x0
413
414 #define CONFIG_SYS_FLASH_QUIET_TEST
415 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
416
417 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
418 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
419 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
420 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
421
422 #define CONFIG_SYS_FLASH_EMPTY_INFO
423 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
424                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
425
426 /* NAND Flash on IFC */
427 #define CONFIG_NAND_FSL_IFC
428 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
429 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
430 #define CONFIG_SYS_NAND_BASE            0xff800000
431 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
432
433 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
434 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
435                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
436                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
437                                 | CSPR_V)
438 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
439
440 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
441                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
442                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
443                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
444                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
445                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
446                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
447
448 #define CONFIG_SYS_NAND_ONFI_DETECTION
449
450 /* ONFI NAND Flash mode0 Timing Params */
451 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
452                                         FTIM0_NAND_TWP(0x18)   | \
453                                         FTIM0_NAND_TWCHT(0x07) | \
454                                         FTIM0_NAND_TWH(0x0a))
455 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
456                                         FTIM1_NAND_TWBE(0x39)  | \
457                                         FTIM1_NAND_TRR(0x0e)   | \
458                                         FTIM1_NAND_TRP(0x18))
459 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
460                                         FTIM2_NAND_TREH(0x0a) | \
461                                         FTIM2_NAND_TWHRE(0x1e))
462 #define CONFIG_SYS_NAND_FTIM3           0x0
463
464 #define CONFIG_SYS_NAND_DDR_LAW         11
465 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
466 #define CONFIG_SYS_MAX_NAND_DEVICE      1
467 #define CONFIG_MTD_NAND_VERIFY_WRITE
468 #define CONFIG_CMD_NAND
469
470 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
471
472 #if defined(CONFIG_NAND)
473 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
474 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
475 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
476 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
477 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
478 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
479 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
480 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
481 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
482 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
483 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
484 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
485 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
486 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
487 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
488 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
489 #else
490 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
491 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
492 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
493 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
494 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
495 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
496 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
497 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
498 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
499 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
500 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
501 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
502 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
503 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
504 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
505 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
506 #endif
507 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
508 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
509 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
510 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
511 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
512 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
513 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
514 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
515
516 #if defined(CONFIG_RAMBOOT_PBL)
517 #define CONFIG_SYS_RAMBOOT
518 #endif
519
520
521 /* I2C */
522 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
523 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
524 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
525 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
526
527 #define I2C_MUX_CH_DEFAULT      0x8
528 #define I2C_MUX_CH_VOL_MONITOR  0xa
529 #define I2C_MUX_CH_VSC3316_FS   0xc
530 #define I2C_MUX_CH_VSC3316_BS   0xd
531
532 /* Voltage monitor on channel 2*/
533 #define I2C_VOL_MONITOR_ADDR            0x40
534 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
535 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
536 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
537
538 /*
539  * eSPI - Enhanced SPI
540  */
541 #define CONFIG_FSL_ESPI
542 #define CONFIG_SPI_FLASH
543 #define CONFIG_SPI_FLASH_SST
544 #define CONFIG_CMD_SF
545 #define CONFIG_SF_DEFAULT_SPEED         10000000
546 #define CONFIG_SF_DEFAULT_MODE          0
547
548
549 /* Qman/Bman */
550 #ifndef CONFIG_NOBQFMAN
551 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
552 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
553 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
554 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
555 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
556 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
557 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
558 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
559 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
560
561 #define CONFIG_SYS_DPAA_FMAN
562 #define CONFIG_SYS_DPAA_PME
563 #define CONFIG_SYS_PMAN
564 #define CONFIG_SYS_DPAA_DCE
565 #define CONFIG_SYS_DPAA_RMAN
566 #define CONFIG_SYS_INTERLAKEN
567
568 /* Default address of microcode for the Linux Fman driver */
569 #if defined(CONFIG_SPIFLASH)
570 /*
571  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
572  * env, so we got 0x110000.
573  */
574 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
575 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
576 #elif defined(CONFIG_SDCARD)
577 /*
578  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
579  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
580  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
581  */
582 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
583 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
584 #elif defined(CONFIG_NAND)
585 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
586 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
587 #else
588 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
589 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
590 #endif
591 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
592 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
593 #endif /* CONFIG_NOBQFMAN */
594
595 #ifdef CONFIG_SYS_DPAA_FMAN
596 #define CONFIG_FMAN_ENET
597 #define CONFIG_PHYLIB_10G
598 #define CONFIG_PHY_VITESSE
599 #define CONFIG_PHY_CORTINA
600 #define CONFIG_CORTINA_FW_ADDR          0xefe00000
601 #define CONFIG_CORTINA_FW_LENGTH        0x40000
602 #define CONFIG_PHY_TERANETICS
603 #define SGMII_PHY_ADDR1 0x0
604 #define SGMII_PHY_ADDR2 0x1
605 #define SGMII_PHY_ADDR3 0x2
606 #define SGMII_PHY_ADDR4 0x3
607 #define SGMII_PHY_ADDR5 0x4
608 #define SGMII_PHY_ADDR6 0x5
609 #define SGMII_PHY_ADDR7 0x6
610 #define SGMII_PHY_ADDR8 0x7
611 #define FM1_10GEC1_PHY_ADDR     0x10
612 #define FM1_10GEC2_PHY_ADDR     0x11
613 #define FM2_10GEC1_PHY_ADDR     0x12
614 #define FM2_10GEC2_PHY_ADDR     0x13
615 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
616 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
617 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
618 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
619 #endif
620
621
622 /* SATA */
623 #ifdef CONFIG_FSL_SATA_V2
624 #define CONFIG_LIBATA
625 #define CONFIG_FSL_SATA
626
627 #define CONFIG_SYS_SATA_MAX_DEVICE      2
628 #define CONFIG_SATA1
629 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
630 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
631 #define CONFIG_SATA2
632 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
633 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
634
635 #define CONFIG_LBA48
636 #define CONFIG_CMD_SATA
637 #define CONFIG_DOS_PARTITION
638 #define CONFIG_CMD_EXT2
639 #endif
640
641 #ifdef CONFIG_FMAN_ENET
642 #define CONFIG_MII              /* MII PHY management */
643 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
644 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
645 #endif
646
647 /*
648 * USB
649 */
650 #define CONFIG_CMD_USB
651 #define CONFIG_USB_STORAGE
652 #define CONFIG_USB_EHCI
653 #define CONFIG_USB_EHCI_FSL
654 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
655 #define CONFIG_CMD_EXT2
656 #define CONFIG_HAS_FSL_DR_USB
657
658 #define CONFIG_MMC
659
660 #ifdef CONFIG_MMC
661 #define CONFIG_FSL_ESDHC
662 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
663 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
664 #define CONFIG_CMD_MMC
665 #define CONFIG_GENERIC_MMC
666 #define CONFIG_CMD_EXT2
667 #define CONFIG_CMD_FAT
668 #define CONFIG_DOS_PARTITION
669 #endif
670
671 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
672
673 #define __USB_PHY_TYPE  utmi
674
675 /*
676  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
677  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
678  * interleaving. It can be cacheline, page, bank, superbank.
679  * See doc/README.fsl-ddr for details.
680  */
681 #define CTRL_INTLV_PREFERED 3way_4KB
682
683 #define CONFIG_EXTRA_ENV_SETTINGS                               \
684         "hwconfig=fsl_ddr:"                                     \
685         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
686         "bank_intlv=auto;"                                      \
687         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
688         "netdev=eth0\0"                                         \
689         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
690         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
691         "tftpflash=tftpboot $loadaddr $uboot && "               \
692         "protect off $ubootaddr +$filesize && "                 \
693         "erase $ubootaddr +$filesize && "                       \
694         "cp.b $loadaddr $ubootaddr $filesize && "               \
695         "protect on $ubootaddr +$filesize && "                  \
696         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
697         "consoledev=ttyS0\0"                                    \
698         "ramdiskaddr=2000000\0"                                 \
699         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
700         "fdtaddr=c00000\0"                                      \
701         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
702         "bdev=sda3\0"
703
704 #define CONFIG_HVBOOT                                   \
705         "setenv bootargs config-addr=0x60000000; "      \
706         "bootm 0x01000000 - 0x00f00000"
707
708 #define CONFIG_LINUX                                    \
709         "setenv bootargs root=/dev/ram rw "             \
710         "console=$consoledev,$baudrate $othbootargs;"   \
711         "setenv ramdiskaddr 0x02000000;"                \
712         "setenv fdtaddr 0x00c00000;"                    \
713         "setenv loadaddr 0x1000000;"                    \
714         "bootm $loadaddr $ramdiskaddr $fdtaddr"
715
716 #define CONFIG_HDBOOT                                   \
717         "setenv bootargs root=/dev/$bdev rw "           \
718         "console=$consoledev,$baudrate $othbootargs;"   \
719         "tftp $loadaddr $bootfile;"                     \
720         "tftp $fdtaddr $fdtfile;"                       \
721         "bootm $loadaddr - $fdtaddr"
722
723 #define CONFIG_NFSBOOTCOMMAND                   \
724         "setenv bootargs root=/dev/nfs rw "     \
725         "nfsroot=$serverip:$rootpath "          \
726         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
727         "console=$consoledev,$baudrate $othbootargs;"   \
728         "tftp $loadaddr $bootfile;"             \
729         "tftp $fdtaddr $fdtfile;"               \
730         "bootm $loadaddr - $fdtaddr"
731
732 #define CONFIG_RAMBOOTCOMMAND                           \
733         "setenv bootargs root=/dev/ram rw "             \
734         "console=$consoledev,$baudrate $othbootargs;"   \
735         "tftp $ramdiskaddr $ramdiskfile;"               \
736         "tftp $loadaddr $bootfile;"                     \
737         "tftp $fdtaddr $fdtfile;"                       \
738         "bootm $loadaddr $ramdiskaddr $fdtaddr"
739
740 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
741
742 #include <asm/fsl_secure_boot.h>
743
744 #ifdef CONFIG_SECURE_BOOT
745 /* Secure Boot target was not getting build for T4240 because of
746  * increased binary size. So the size is being reduced by removing USB
747  * which is anyways not used in Secure Environment.
748  */
749 #undef CONFIG_CMD_USB
750 #endif
751
752 #endif  /* __CONFIG_H */