Merge tag 'xilinx-for-v2022.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u...
[platform/kernel/u-boot.git] / include / configs / T4240RDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  * Copyright 2020-2021 NXP
5  */
6
7 /*
8  * T4240 RDB board configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #include <linux/stringify.h>
14
15 #define CONFIG_FSL_SATA_V2
16 #define CONFIG_PCIE4
17
18 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
19
20 #ifdef CONFIG_RAMBOOT_PBL
21 #ifndef CONFIG_SDCARD
22 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
23 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
24 #else
25 #define CONFIG_SPL_FLUSH_IMAGE
26 #define CONFIG_SPL_PAD_TO               0x40000
27 #define CONFIG_SPL_MAX_SIZE             0x28000
28 #define RESET_VECTOR_OFFSET             0x27FFC
29 #define BOOT_PAGE_OFFSET                0x27000
30
31 #ifdef  CONFIG_SDCARD
32 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
33 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
34 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
35 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
36 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
37 #ifndef CONFIG_SPL_BUILD
38 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
39 #endif
40 #endif
41
42 #ifdef CONFIG_SPL_BUILD
43 #define CONFIG_SPL_SKIP_RELOCATE
44 #define CONFIG_SPL_COMMON_INIT_DDR
45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
46 #endif
47
48 #endif
49 #endif /* CONFIG_RAMBOOT_PBL */
50
51 /* High Level Configuration Options */
52 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
53
54 #ifndef CONFIG_RESET_VECTOR_ADDRESS
55 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
56 #endif
57
58 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
59 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
60 #define CONFIG_PCIE1                    /* PCIE controller 1 */
61 #define CONFIG_PCIE2                    /* PCIE controller 2 */
62 #define CONFIG_PCIE3                    /* PCIE controller 3 */
63
64 /*
65  * These can be toggled for performance analysis, otherwise use default.
66  */
67 #define CONFIG_SYS_CACHE_STASHING
68 #define CONFIG_BTB                      /* toggle branch predition */
69 #ifdef CONFIG_DDR_ECC
70 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
71 #endif
72
73 #define CONFIG_ENABLE_36BIT_PHYS
74
75 /*
76  *  Config the L3 Cache as L3 SRAM
77  */
78 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
79 #define CONFIG_SYS_L3_SIZE              (512 << 10)
80 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
81 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
82 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
83 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
84 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
85
86 #define CONFIG_SYS_DCSRBAR              0xf0000000
87 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
88
89 /*
90  * DDR Setup
91  */
92 #define CONFIG_VERY_BIG_RAM
93 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
94 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
95
96 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
97 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
98
99 /*
100  * IFC Definitions
101  */
102 #define CONFIG_SYS_FLASH_BASE   0xe0000000
103 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
104
105 #ifdef CONFIG_SPL_BUILD
106 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
107 #else
108 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
109 #endif
110
111 #define CONFIG_HWCONFIG
112
113 /* define to use L1 as initial stack */
114 #define CONFIG_L1_INIT_RAM
115 #define CONFIG_SYS_INIT_RAM_LOCK
116 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
117 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
118 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
119 /* The assembler doesn't like typecast */
120 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
121         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
122           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
123 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
124
125 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
126                                         GENERATED_GBL_DATA_SIZE)
127 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
128
129 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
130
131 /* Serial Port - controlled on board with jumper J8
132  * open - index 2
133  * shorted - index 1
134  */
135 #define CONFIG_SYS_NS16550_SERIAL
136 #define CONFIG_SYS_NS16550_REG_SIZE     1
137 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
138
139 #define CONFIG_SYS_BAUDRATE_TABLE       \
140         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
141
142 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
143 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
144 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
145 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
146
147 /* I2C */
148
149 /*
150  * General PCI
151  * Memory space is mapped 1-1, but I/O space must start from 0.
152  */
153
154 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
155 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
156 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
157 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
158 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
159
160 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
161 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
162 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
163 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
164 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
165
166 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
167 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
168 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
169 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
170 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
171
172 /* controller 4, Base address 203000 */
173 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
174 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
175 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
176
177 #ifdef CONFIG_PCI
178 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
179 #endif  /* CONFIG_PCI */
180
181 /* SATA */
182 #ifdef CONFIG_FSL_SATA_V2
183 #define CONFIG_SATA1
184 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
185 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
186 #define CONFIG_SATA2
187 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
188 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
189
190 #define CONFIG_LBA48
191 #endif
192
193 #ifdef CONFIG_FMAN_ENET
194 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
195 #endif
196
197 /*
198  * Environment
199  */
200 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
201 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
202
203 /*
204  * Miscellaneous configurable options
205  */
206
207 /*
208  * For booting Linux, the board info and command line data
209  * have to be in the first 64 MB of memory, since this is
210  * the maximum mapped by the Linux kernel during initialization.
211  */
212 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
213 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
214
215 /*
216  * Environment Configuration
217  */
218 #define CONFIG_ROOTPATH         "/opt/nfsroot"
219 #define CONFIG_BOOTFILE         "uImage"
220 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
221
222 #define HVBOOT                                  \
223         "setenv bootargs config-addr=0x60000000; "      \
224         "bootm 0x01000000 - 0x00f00000"
225
226 /*
227  * DDR Setup
228  */
229 #define CONFIG_SYS_SPD_BUS_NUM  0
230 #define SPD_EEPROM_ADDRESS1     0x52
231 #define SPD_EEPROM_ADDRESS2     0x54
232 #define SPD_EEPROM_ADDRESS3     0x56
233 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
234 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
235
236 /*
237  * IFC Definitions
238  */
239 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
240 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
241                                 + 0x8000000) | \
242                                 CSPR_PORT_SIZE_16 | \
243                                 CSPR_MSEL_NOR | \
244                                 CSPR_V)
245 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
246 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
247                                 CSPR_PORT_SIZE_16 | \
248                                 CSPR_MSEL_NOR | \
249                                 CSPR_V)
250 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
251 /* NOR Flash Timing Params */
252 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
253
254 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
255                                 FTIM0_NOR_TEADC(0x5) | \
256                                 FTIM0_NOR_TEAHC(0x5))
257 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
258                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
259                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
260 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
261                                 FTIM2_NOR_TCH(0x4) | \
262                                 FTIM2_NOR_TWPH(0x0E) | \
263                                 FTIM2_NOR_TWP(0x1c))
264 #define CONFIG_SYS_NOR_FTIM3    0x0
265
266 #define CONFIG_SYS_FLASH_QUIET_TEST
267 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
268
269 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
270 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
271 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
272
273 #define CONFIG_SYS_FLASH_EMPTY_INFO
274 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
275                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
276
277 /* NAND Flash on IFC */
278 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
279 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
280 #define CONFIG_SYS_NAND_BASE            0xff800000
281 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
282
283 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
284 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
285                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
286                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
287                                 | CSPR_V)
288 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
289
290 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
291                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
292                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
293                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
294                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
295                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
296                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
297
298 /* ONFI NAND Flash mode0 Timing Params */
299 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
300                                         FTIM0_NAND_TWP(0x18)   | \
301                                         FTIM0_NAND_TWCHT(0x07) | \
302                                         FTIM0_NAND_TWH(0x0a))
303 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
304                                         FTIM1_NAND_TWBE(0x39)  | \
305                                         FTIM1_NAND_TRR(0x0e)   | \
306                                         FTIM1_NAND_TRP(0x18))
307 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
308                                         FTIM2_NAND_TREH(0x0a) | \
309                                         FTIM2_NAND_TWHRE(0x1e))
310 #define CONFIG_SYS_NAND_FTIM3           0x0
311
312 #define CONFIG_SYS_NAND_DDR_LAW         11
313 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
314 #define CONFIG_SYS_MAX_NAND_DEVICE      1
315
316 #if defined(CONFIG_MTD_RAW_NAND)
317 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
318 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
319 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
320 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
321 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
322 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
323 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
324 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
325 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
326 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
327 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
328 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
329 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
330 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
331 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
332 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
333 #else
334 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
335 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
336 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
337 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
338 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
339 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
340 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
341 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
342 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
343 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
344 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
345 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
346 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
347 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
348 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
349 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
350 #endif
351 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
352 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
353 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
354 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
355 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
356 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
357 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
358 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
359
360 /* CPLD on IFC */
361 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
362 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
363 #define CONFIG_SYS_CSPR3_EXT    (0xf)
364 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
365                                 | CSPR_PORT_SIZE_8 \
366                                 | CSPR_MSEL_GPCM \
367                                 | CSPR_V)
368
369 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
370 #define CONFIG_SYS_CSOR3        0x0
371
372 /* CPLD Timing parameters for IFC CS3 */
373 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
374                                         FTIM0_GPCM_TEADC(0x0e) | \
375                                         FTIM0_GPCM_TEAHC(0x0e))
376 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
377                                         FTIM1_GPCM_TRAD(0x1f))
378 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
379                                         FTIM2_GPCM_TCH(0x8) | \
380                                         FTIM2_GPCM_TWP(0x1f))
381 #define CONFIG_SYS_CS3_FTIM3            0x0
382
383 #if defined(CONFIG_RAMBOOT_PBL)
384 #define CONFIG_SYS_RAMBOOT
385 #endif
386
387 /* I2C */
388 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
389 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
390
391 #define I2C_MUX_CH_DEFAULT      0x8
392 #define I2C_MUX_CH_VOL_MONITOR  0xa
393 #define I2C_MUX_CH_VSC3316_FS   0xc
394 #define I2C_MUX_CH_VSC3316_BS   0xd
395
396 /* Voltage monitor on channel 2*/
397 #define I2C_VOL_MONITOR_ADDR            0x40
398 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
399 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
400 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
401
402 /* The lowest and highest voltage allowed for T4240RDB */
403 #define VDD_MV_MIN                      819
404 #define VDD_MV_MAX                      1212
405
406 /*
407  * eSPI - Enhanced SPI
408  */
409
410 /* Qman/Bman */
411 #ifndef CONFIG_NOBQFMAN
412 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
413 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
414 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
415 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
416 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
417 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
418 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
419 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
420 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
421                                         CONFIG_SYS_BMAN_CENA_SIZE)
422 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
423 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
424 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
425 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
426 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
427 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
428 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
429 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
430 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
431 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
432 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
433                                         CONFIG_SYS_QMAN_CENA_SIZE)
434 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
435 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
436
437 #define CONFIG_SYS_DPAA_FMAN
438 #define CONFIG_SYS_DPAA_PME
439 #define CONFIG_SYS_PMAN
440 #define CONFIG_SYS_DPAA_DCE
441 #define CONFIG_SYS_DPAA_RMAN
442 #define CONFIG_SYS_INTERLAKEN
443
444 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
445 #endif /* CONFIG_NOBQFMAN */
446
447 #ifdef CONFIG_SYS_DPAA_FMAN
448 #define SGMII_PHY_ADDR1 0x0
449 #define SGMII_PHY_ADDR2 0x1
450 #define SGMII_PHY_ADDR3 0x2
451 #define SGMII_PHY_ADDR4 0x3
452 #define SGMII_PHY_ADDR5 0x4
453 #define SGMII_PHY_ADDR6 0x5
454 #define SGMII_PHY_ADDR7 0x6
455 #define SGMII_PHY_ADDR8 0x7
456 #define FM1_10GEC1_PHY_ADDR     0x10
457 #define FM1_10GEC2_PHY_ADDR     0x11
458 #define FM2_10GEC1_PHY_ADDR     0x12
459 #define FM2_10GEC2_PHY_ADDR     0x13
460 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
461 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
462 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
463 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
464 #endif
465
466 /* SATA */
467 #ifdef CONFIG_FSL_SATA_V2
468 #define CONFIG_SATA1
469 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
470 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
471 #define CONFIG_SATA2
472 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
473 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
474
475 #define CONFIG_LBA48
476 #endif
477
478 #ifdef CONFIG_FMAN_ENET
479 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
480 #endif
481
482 /*
483 * USB
484 */
485 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
486 #define CONFIG_HAS_FSL_DR_USB
487
488 #ifdef CONFIG_MMC
489 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
490 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
491 #endif
492
493
494 #define __USB_PHY_TYPE  utmi
495
496 /*
497  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
498  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
499  * interleaving. It can be cacheline, page, bank, superbank.
500  * See doc/README.fsl-ddr for details.
501  */
502 #ifdef CONFIG_ARCH_T4240
503 #define CTRL_INTLV_PREFERED 3way_4KB
504 #else
505 #define CTRL_INTLV_PREFERED cacheline
506 #endif
507
508 #define CONFIG_EXTRA_ENV_SETTINGS                               \
509         "hwconfig=fsl_ddr:"                                     \
510         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
511         "bank_intlv=auto;"                                      \
512         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
513         "netdev=eth0\0"                                         \
514         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
515         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
516         "tftpflash=tftpboot $loadaddr $uboot && "               \
517         "protect off $ubootaddr +$filesize && "                 \
518         "erase $ubootaddr +$filesize && "                       \
519         "cp.b $loadaddr $ubootaddr $filesize && "               \
520         "protect on $ubootaddr +$filesize && "                  \
521         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
522         "consoledev=ttyS0\0"                                    \
523         "ramdiskaddr=2000000\0"                                 \
524         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
525         "fdtaddr=1e00000\0"                                     \
526         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
527         "bdev=sda3\0"
528
529 #define HVBOOT                                  \
530         "setenv bootargs config-addr=0x60000000; "      \
531         "bootm 0x01000000 - 0x00f00000"
532
533 #include <asm/fsl_secure_boot.h>
534
535 #endif  /* __CONFIG_H */