1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
7 * T4240 RDB board configuration file
12 #define CONFIG_FSL_SATA_V2
15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
20 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
21 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
23 #define CONFIG_SPL_FLUSH_IMAGE
24 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
25 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
26 #define CONFIG_SPL_PAD_TO 0x40000
27 #define CONFIG_SPL_MAX_SIZE 0x28000
28 #define RESET_VECTOR_OFFSET 0x27FFC
29 #define BOOT_PAGE_OFFSET 0x27000
32 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
33 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
34 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
35 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
36 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
37 #ifndef CONFIG_SPL_BUILD
38 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
40 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
41 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
42 #define CONFIG_SPL_MMC_BOOT
45 #ifdef CONFIG_SPL_BUILD
46 #define CONFIG_SPL_SKIP_RELOCATE
47 #define CONFIG_SPL_COMMON_INIT_DDR
48 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
52 #endif /* CONFIG_RAMBOOT_PBL */
54 #define CONFIG_DDR_ECC
56 /* High Level Configuration Options */
57 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
60 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
63 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
64 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
65 #define CONFIG_PCIE1 /* PCIE controller 1 */
66 #define CONFIG_PCIE2 /* PCIE controller 2 */
67 #define CONFIG_PCIE3 /* PCIE controller 3 */
68 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
69 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
71 #define CONFIG_ENV_OVERWRITE
74 * These can be toggled for performance analysis, otherwise use default.
76 #define CONFIG_SYS_CACHE_STASHING
77 #define CONFIG_BTB /* toggle branch predition */
79 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
80 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
83 #define CONFIG_ENABLE_36BIT_PHYS
85 #define CONFIG_ADDR_MAP
86 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
88 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
89 #define CONFIG_SYS_MEMTEST_END 0x00400000
92 * Config the L3 Cache as L3 SRAM
94 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
95 #define CONFIG_SYS_L3_SIZE (512 << 10)
96 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
97 #ifdef CONFIG_RAMBOOT_PBL
98 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
100 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
101 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
102 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
103 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
105 #define CONFIG_SYS_DCSRBAR 0xf0000000
106 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
111 #define CONFIG_VERY_BIG_RAM
112 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
113 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
115 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
116 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
117 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
119 #define CONFIG_DDR_SPD
124 #define CONFIG_SYS_FLASH_BASE 0xe0000000
125 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
127 #ifdef CONFIG_SPL_BUILD
128 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
133 #define CONFIG_MISC_INIT_R
135 #define CONFIG_HWCONFIG
137 /* define to use L1 as initial stack */
138 #define CONFIG_L1_INIT_RAM
139 #define CONFIG_SYS_INIT_RAM_LOCK
140 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
141 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
142 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
143 /* The assembler doesn't like typecast */
144 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
145 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
146 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
147 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
149 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
150 GENERATED_GBL_DATA_SIZE)
151 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
153 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
154 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
156 /* Serial Port - controlled on board with jumper J8
160 #define CONFIG_SYS_NS16550_SERIAL
161 #define CONFIG_SYS_NS16550_REG_SIZE 1
162 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
164 #define CONFIG_SYS_BAUDRATE_TABLE \
165 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
167 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
168 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
169 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
170 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
173 #define CONFIG_SYS_I2C
174 #define CONFIG_SYS_I2C_FSL
175 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
176 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
177 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
178 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
182 * Memory space is mapped 1-1, but I/O space must start from 0.
185 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
186 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
187 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
188 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
189 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
190 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
191 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
192 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
193 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
195 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
196 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
197 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
198 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
199 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
200 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
201 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
202 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
203 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
205 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
206 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
207 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
208 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
209 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
210 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
211 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
212 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
213 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
215 /* controller 4, Base address 203000 */
216 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
217 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
218 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
219 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
220 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
221 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
224 #define CONFIG_PCI_INDIRECT_BRIDGE
226 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
227 #endif /* CONFIG_PCI */
230 #ifdef CONFIG_FSL_SATA_V2
231 #define CONFIG_SYS_SATA_MAX_DEVICE 2
233 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
234 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
236 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
237 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
242 #ifdef CONFIG_FMAN_ENET
243 #define CONFIG_MII /* MII PHY management */
244 #define CONFIG_ETHPRIME "FM1@DTSEC1"
250 #define CONFIG_LOADS_ECHO /* echo on for serial download */
251 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
254 * Command line configuration.
258 * Miscellaneous configurable options
260 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
263 * For booting Linux, the board info and command line data
264 * have to be in the first 64 MB of memory, since this is
265 * the maximum mapped by the Linux kernel during initialization.
267 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
268 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
270 #ifdef CONFIG_CMD_KGDB
271 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
275 * Environment Configuration
277 #define CONFIG_ROOTPATH "/opt/nfsroot"
278 #define CONFIG_BOOTFILE "uImage"
279 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
281 /* default location for tftp and bootm */
282 #define CONFIG_LOADADDR 1000000
284 #define CONFIG_HVBOOT \
285 "setenv bootargs config-addr=0x60000000; " \
286 "bootm 0x01000000 - 0x00f00000"
288 #ifndef CONFIG_MTD_NOR_FLASH
290 #define CONFIG_FLASH_CFI_DRIVER
291 #define CONFIG_SYS_FLASH_CFI
292 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
295 #if defined(CONFIG_SPIFLASH)
296 #define CONFIG_SYS_EXTRA_ENV_RELOC
297 #define CONFIG_ENV_SPI_BUS 0
298 #define CONFIG_ENV_SPI_CS 0
299 #define CONFIG_ENV_SPI_MAX_HZ 10000000
300 #define CONFIG_ENV_SPI_MODE 0
301 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
302 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
303 #define CONFIG_ENV_SECT_SIZE 0x10000
304 #elif defined(CONFIG_SDCARD)
305 #define CONFIG_SYS_EXTRA_ENV_RELOC
306 #define CONFIG_SYS_MMC_ENV_DEV 0
307 #define CONFIG_ENV_SIZE 0x2000
308 #define CONFIG_ENV_OFFSET (512 * 0x800)
309 #elif defined(CONFIG_NAND)
310 #define CONFIG_SYS_EXTRA_ENV_RELOC
311 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
312 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
313 #elif defined(CONFIG_ENV_IS_NOWHERE)
314 #define CONFIG_ENV_SIZE 0x2000
316 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
317 #define CONFIG_ENV_SIZE 0x2000
318 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
321 #define CONFIG_SYS_CLK_FREQ 66666666
322 #define CONFIG_DDR_CLK_FREQ 133333333
325 unsigned long get_board_sys_clk(void);
326 unsigned long get_board_ddr_clk(void);
332 #define CONFIG_SYS_SPD_BUS_NUM 0
333 #define SPD_EEPROM_ADDRESS1 0x52
334 #define SPD_EEPROM_ADDRESS2 0x54
335 #define SPD_EEPROM_ADDRESS3 0x56
336 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
337 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
342 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
343 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
345 CSPR_PORT_SIZE_16 | \
348 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
349 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
350 CSPR_PORT_SIZE_16 | \
353 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
354 /* NOR Flash Timing Params */
355 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
357 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
358 FTIM0_NOR_TEADC(0x5) | \
359 FTIM0_NOR_TEAHC(0x5))
360 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
361 FTIM1_NOR_TRAD_NOR(0x1A) |\
362 FTIM1_NOR_TSEQRAD_NOR(0x13))
363 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
364 FTIM2_NOR_TCH(0x4) | \
365 FTIM2_NOR_TWPH(0x0E) | \
367 #define CONFIG_SYS_NOR_FTIM3 0x0
369 #define CONFIG_SYS_FLASH_QUIET_TEST
370 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
372 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
373 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
374 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
375 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
377 #define CONFIG_SYS_FLASH_EMPTY_INFO
378 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
379 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
381 /* NAND Flash on IFC */
382 #define CONFIG_NAND_FSL_IFC
383 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
384 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
385 #define CONFIG_SYS_NAND_BASE 0xff800000
386 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
388 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
389 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
390 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
391 | CSPR_MSEL_NAND /* MSEL = NAND */ \
393 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
395 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
396 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
397 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
398 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
399 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
400 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
401 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
403 #define CONFIG_SYS_NAND_ONFI_DETECTION
405 /* ONFI NAND Flash mode0 Timing Params */
406 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
407 FTIM0_NAND_TWP(0x18) | \
408 FTIM0_NAND_TWCHT(0x07) | \
409 FTIM0_NAND_TWH(0x0a))
410 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
411 FTIM1_NAND_TWBE(0x39) | \
412 FTIM1_NAND_TRR(0x0e) | \
413 FTIM1_NAND_TRP(0x18))
414 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
415 FTIM2_NAND_TREH(0x0a) | \
416 FTIM2_NAND_TWHRE(0x1e))
417 #define CONFIG_SYS_NAND_FTIM3 0x0
419 #define CONFIG_SYS_NAND_DDR_LAW 11
420 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
421 #define CONFIG_SYS_MAX_NAND_DEVICE 1
423 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
425 #if defined(CONFIG_NAND)
426 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
427 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
428 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
429 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
430 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
431 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
432 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
433 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
434 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
435 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
436 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
437 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
438 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
439 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
440 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
441 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
443 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
444 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
445 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
446 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
447 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
448 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
449 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
450 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
451 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
452 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
453 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
454 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
455 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
456 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
457 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
458 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
460 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
461 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
462 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
463 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
464 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
465 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
466 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
467 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
470 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
471 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
472 #define CONFIG_SYS_CSPR3_EXT (0xf)
473 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
478 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
479 #define CONFIG_SYS_CSOR3 0x0
481 /* CPLD Timing parameters for IFC CS3 */
482 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
483 FTIM0_GPCM_TEADC(0x0e) | \
484 FTIM0_GPCM_TEAHC(0x0e))
485 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
486 FTIM1_GPCM_TRAD(0x1f))
487 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
488 FTIM2_GPCM_TCH(0x8) | \
489 FTIM2_GPCM_TWP(0x1f))
490 #define CONFIG_SYS_CS3_FTIM3 0x0
492 #if defined(CONFIG_RAMBOOT_PBL)
493 #define CONFIG_SYS_RAMBOOT
497 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
498 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
499 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
500 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
502 #define I2C_MUX_CH_DEFAULT 0x8
503 #define I2C_MUX_CH_VOL_MONITOR 0xa
504 #define I2C_MUX_CH_VSC3316_FS 0xc
505 #define I2C_MUX_CH_VSC3316_BS 0xd
507 /* Voltage monitor on channel 2*/
508 #define I2C_VOL_MONITOR_ADDR 0x40
509 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
510 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
511 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
513 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
514 #ifndef CONFIG_SPL_BUILD
517 #define CONFIG_VOL_MONITOR_IR36021_SET
518 #define CONFIG_VOL_MONITOR_IR36021_READ
519 /* The lowest and highest voltage allowed for T4240RDB */
520 #define VDD_MV_MIN 819
521 #define VDD_MV_MAX 1212
524 * eSPI - Enhanced SPI
526 #define CONFIG_SF_DEFAULT_SPEED 10000000
527 #define CONFIG_SF_DEFAULT_MODE 0
530 #ifndef CONFIG_NOBQFMAN
531 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
532 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
533 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
534 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
535 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
536 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
537 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
538 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
539 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
540 CONFIG_SYS_BMAN_CENA_SIZE)
541 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
542 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
543 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
544 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
545 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
546 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
547 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
548 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
549 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
550 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
551 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
552 CONFIG_SYS_QMAN_CENA_SIZE)
553 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
554 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
556 #define CONFIG_SYS_DPAA_FMAN
557 #define CONFIG_SYS_DPAA_PME
558 #define CONFIG_SYS_PMAN
559 #define CONFIG_SYS_DPAA_DCE
560 #define CONFIG_SYS_DPAA_RMAN
561 #define CONFIG_SYS_INTERLAKEN
563 /* Default address of microcode for the Linux Fman driver */
564 #if defined(CONFIG_SPIFLASH)
566 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
567 * env, so we got 0x110000.
569 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
570 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
571 #elif defined(CONFIG_SDCARD)
573 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
574 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
575 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
577 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
578 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
579 #elif defined(CONFIG_NAND)
580 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
581 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
583 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
584 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
586 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
587 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
588 #endif /* CONFIG_NOBQFMAN */
590 #ifdef CONFIG_SYS_DPAA_FMAN
591 #define CONFIG_FMAN_ENET
592 #define CONFIG_PHYLIB_10G
593 #define CONFIG_PHY_VITESSE
594 #define CONFIG_PHY_CORTINA
595 #define CONFIG_SYS_CORTINA_FW_IN_NOR
596 #define CONFIG_CORTINA_FW_ADDR 0xefe00000
597 #define CONFIG_CORTINA_FW_LENGTH 0x40000
598 #define CONFIG_PHY_TERANETICS
599 #define SGMII_PHY_ADDR1 0x0
600 #define SGMII_PHY_ADDR2 0x1
601 #define SGMII_PHY_ADDR3 0x2
602 #define SGMII_PHY_ADDR4 0x3
603 #define SGMII_PHY_ADDR5 0x4
604 #define SGMII_PHY_ADDR6 0x5
605 #define SGMII_PHY_ADDR7 0x6
606 #define SGMII_PHY_ADDR8 0x7
607 #define FM1_10GEC1_PHY_ADDR 0x10
608 #define FM1_10GEC2_PHY_ADDR 0x11
609 #define FM2_10GEC1_PHY_ADDR 0x12
610 #define FM2_10GEC2_PHY_ADDR 0x13
611 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
612 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
613 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
614 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
618 #ifdef CONFIG_FSL_SATA_V2
619 #define CONFIG_SYS_SATA_MAX_DEVICE 2
621 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
622 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
624 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
625 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
630 #ifdef CONFIG_FMAN_ENET
631 #define CONFIG_MII /* MII PHY management */
632 #define CONFIG_ETHPRIME "FM1@DTSEC1"
638 #define CONFIG_USB_EHCI_FSL
639 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
640 #define CONFIG_HAS_FSL_DR_USB
643 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
644 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
645 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
649 #define __USB_PHY_TYPE utmi
652 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
653 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
654 * interleaving. It can be cacheline, page, bank, superbank.
655 * See doc/README.fsl-ddr for details.
657 #ifdef CONFIG_ARCH_T4240
658 #define CTRL_INTLV_PREFERED 3way_4KB
660 #define CTRL_INTLV_PREFERED cacheline
663 #define CONFIG_EXTRA_ENV_SETTINGS \
664 "hwconfig=fsl_ddr:" \
665 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
667 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
669 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
670 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
671 "tftpflash=tftpboot $loadaddr $uboot && " \
672 "protect off $ubootaddr +$filesize && " \
673 "erase $ubootaddr +$filesize && " \
674 "cp.b $loadaddr $ubootaddr $filesize && " \
675 "protect on $ubootaddr +$filesize && " \
676 "cmp.b $loadaddr $ubootaddr $filesize\0" \
677 "consoledev=ttyS0\0" \
678 "ramdiskaddr=2000000\0" \
679 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
680 "fdtaddr=1e00000\0" \
681 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
684 #define CONFIG_HVBOOT \
685 "setenv bootargs config-addr=0x60000000; " \
686 "bootm 0x01000000 - 0x00f00000"
688 #define CONFIG_LINUX \
689 "setenv bootargs root=/dev/ram rw " \
690 "console=$consoledev,$baudrate $othbootargs;" \
691 "setenv ramdiskaddr 0x02000000;" \
692 "setenv fdtaddr 0x00c00000;" \
693 "setenv loadaddr 0x1000000;" \
694 "bootm $loadaddr $ramdiskaddr $fdtaddr"
696 #define CONFIG_HDBOOT \
697 "setenv bootargs root=/dev/$bdev rw " \
698 "console=$consoledev,$baudrate $othbootargs;" \
699 "tftp $loadaddr $bootfile;" \
700 "tftp $fdtaddr $fdtfile;" \
701 "bootm $loadaddr - $fdtaddr"
703 #define CONFIG_NFSBOOTCOMMAND \
704 "setenv bootargs root=/dev/nfs rw " \
705 "nfsroot=$serverip:$rootpath " \
706 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
707 "console=$consoledev,$baudrate $othbootargs;" \
708 "tftp $loadaddr $bootfile;" \
709 "tftp $fdtaddr $fdtfile;" \
710 "bootm $loadaddr - $fdtaddr"
712 #define CONFIG_RAMBOOTCOMMAND \
713 "setenv bootargs root=/dev/ram rw " \
714 "console=$consoledev,$baudrate $othbootargs;" \
715 "tftp $ramdiskaddr $ramdiskfile;" \
716 "tftp $loadaddr $bootfile;" \
717 "tftp $fdtaddr $fdtfile;" \
718 "bootm $loadaddr $ramdiskaddr $fdtaddr"
720 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
722 #include <asm/fsl_secure_boot.h>
724 #endif /* __CONFIG_H */