include/configs/T4240RDB.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_FSL_SATA_V2
  14 #define CONFIG_PCIE4
  15
  16 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  17
  18 #ifdef CONFIG_RAMBOOT_PBL
  19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  20 #ifndef CONFIG_SDCARD
  21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23 #else
  24 #define CONFIG_SPL_FLUSH_IMAGE
  25 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  26 #define CONFIG_SYS_TEXT_BASE            0x00201000
  27 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  28 #define CONFIG_SPL_PAD_TO               0x40000
  29 #define CONFIG_SPL_MAX_SIZE             0x28000
  30 #define RESET_VECTOR_OFFSET             0x27FFC
  31 #define BOOT_PAGE_OFFSET                0x27000
  32
  33 #ifdef  CONFIG_SDCARD
  34 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  35 #define CONFIG_SPL_MMC_MINIMAL
  36 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  37 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  38 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  39 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  40 #ifndef CONFIG_SPL_BUILD
  41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  42 #endif
  43 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  45 #define CONFIG_SPL_MMC_BOOT
  46 #endif
  47
  48 #ifdef CONFIG_SPL_BUILD
  49 #define CONFIG_SPL_SKIP_RELOCATE
  50 #define CONFIG_SPL_COMMON_INIT_DDR
  51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  52 #define CONFIG_SYS_NO_FLASH
  53 #endif
  54
  55 #endif
  56 #endif /* CONFIG_RAMBOOT_PBL */
  57
  58 #define CONFIG_DDR_ECC
  59
  60 #define CONFIG_CMD_REGINFO
  61
  62 /* High Level Configuration Options */
  63 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  64 #define CONFIG_MP                       /* support multiple processors */
  65
  66 #ifndef CONFIG_SYS_TEXT_BASE
  67 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  68 #endif
  69
  70 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  71 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  72 #endif
  73
  74 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  75 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  76 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  77 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  78 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  79 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  80 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  81 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  82 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  83
  84 #define CONFIG_ENV_OVERWRITE
  85
  86 /*
  87  * These can be toggled for performance analysis, otherwise use default.
  88  */
  89 #define CONFIG_SYS_CACHE_STASHING
  90 #define CONFIG_BTB                      /* toggle branch predition */
  91 #ifdef CONFIG_DDR_ECC
  92 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  93 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  94 #endif
  95
  96 #define CONFIG_ENABLE_36BIT_PHYS
  97
  98 #define CONFIG_ADDR_MAP
  99 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 100
 101 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 102 #define CONFIG_SYS_MEMTEST_END          0x00400000
 103 #define CONFIG_SYS_ALT_MEMTEST
 104 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 105
 106 /*
 107  *  Config the L3 Cache as L3 SRAM
 108  */
 109 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 110 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 111 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 112 #ifdef CONFIG_RAMBOOT_PBL
 113 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 114 #endif
 115 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 116 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 117 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 118 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 119
 120 #define CONFIG_SYS_DCSRBAR              0xf0000000
 121 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 122
 123 /*
 124  * DDR Setup
 125  */
 126 #define CONFIG_VERY_BIG_RAM
 127 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 128 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 129
 130 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 131 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 132 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 133
 134 #define CONFIG_DDR_SPD
 135
 136 /*
 137  * IFC Definitions
 138  */
 139 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 140 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 141
 142 #ifdef CONFIG_SPL_BUILD
 143 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 144 #else
 145 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 146 #endif
 147
 148 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 149 #define CONFIG_MISC_INIT_R
 150
 151 #define CONFIG_HWCONFIG
 152
 153 /* define to use L1 as initial stack */
 154 #define CONFIG_L1_INIT_RAM
 155 #define CONFIG_SYS_INIT_RAM_LOCK
 156 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 157 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 158 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 159 /* The assembler doesn't like typecast */
 160 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 161         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 162           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 163 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 164
 165 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 166                                         GENERATED_GBL_DATA_SIZE)
 167 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 168
 169 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 170 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 171
 172 /* Serial Port - controlled on board with jumper J8
 173  * open - index 2
 174  * shorted - index 1
 175  */
 176 #define CONFIG_CONS_INDEX       1
 177 #define CONFIG_SYS_NS16550_SERIAL
 178 #define CONFIG_SYS_NS16550_REG_SIZE     1
 179 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 180
 181 #define CONFIG_SYS_BAUDRATE_TABLE       \
 182         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 183
 184 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 185 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 186 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 187 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 188
 189 /* I2C */
 190 #define CONFIG_SYS_I2C
 191 #define CONFIG_SYS_I2C_FSL
 192 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 193 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 194 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 195 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 196
 197 /*
 198  * General PCI
 199  * Memory space is mapped 1-1, but I/O space must start from 0.
 200  */
 201
 202 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 203 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 204 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 205 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 206 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 207 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 208 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 209 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 210 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 211
 212 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 213 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 214 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 215 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 216 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 217 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 218 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 219 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 220 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 221
 222 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 223 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 224 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 225 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 226 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 227 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 228 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 229 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 230 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 231
 232 /* controller 4, Base address 203000 */
 233 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 234 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 235 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 236 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 237 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 238 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 239
 240 #ifdef CONFIG_PCI
 241 #define CONFIG_PCI_INDIRECT_BRIDGE
 242
 243 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 244 #endif  /* CONFIG_PCI */
 245
 246 /* SATA */
 247 #ifdef CONFIG_FSL_SATA_V2
 248 #define CONFIG_LIBATA
 249 #define CONFIG_FSL_SATA
 250
 251 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 252 #define CONFIG_SATA1
 253 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 254 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 255 #define CONFIG_SATA2
 256 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 257 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 258
 259 #define CONFIG_LBA48
 260 #define CONFIG_CMD_SATA
 261 #endif
 262
 263 #ifdef CONFIG_FMAN_ENET
 264 #define CONFIG_MII              /* MII PHY management */
 265 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 266 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 267 #endif
 268
 269 /*
 270  * Environment
 271  */
 272 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 273 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 274
 275 /*
 276  * Command line configuration.
 277  */
 278 #define CONFIG_CMD_ERRATA
 279 #define CONFIG_CMD_IRQ
 280
 281 #ifdef CONFIG_PCI
 282 #define CONFIG_CMD_PCI
 283 #endif
 284
 285 /*
 286  * Miscellaneous configurable options
 287  */
 288 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 289 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 290 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 291 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 292 #ifdef CONFIG_CMD_KGDB
 293 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 294 #else
 295 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 296 #endif
 297 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 298 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 299 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 300
 301 /*
 302  * For booting Linux, the board info and command line data
 303  * have to be in the first 64 MB of memory, since this is
 304  * the maximum mapped by the Linux kernel during initialization.
 305  */
 306 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 307 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 308
 309 #ifdef CONFIG_CMD_KGDB
 310 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 311 #endif
 312
 313 /*
 314  * Environment Configuration
 315  */
 316 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 317 #define CONFIG_BOOTFILE         "uImage"
 318 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 319
 320 /* default location for tftp and bootm */
 321 #define CONFIG_LOADADDR         1000000
 322
 323 #define CONFIG_BAUDRATE 115200
 324
 325 #define CONFIG_HVBOOT                                   \
 326         "setenv bootargs config-addr=0x60000000; "      \
 327         "bootm 0x01000000 - 0x00f00000"
 328
 329 #ifdef CONFIG_SYS_NO_FLASH
 330 #ifndef CONFIG_RAMBOOT_PBL
 331 #define CONFIG_ENV_IS_NOWHERE
 332 #endif
 333 #else
 334 #define CONFIG_FLASH_CFI_DRIVER
 335 #define CONFIG_SYS_FLASH_CFI
 336 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 337 #endif
 338
 339 #if defined(CONFIG_SPIFLASH)
 340 #define CONFIG_SYS_EXTRA_ENV_RELOC
 341 #define CONFIG_ENV_IS_IN_SPI_FLASH
 342 #define CONFIG_ENV_SPI_BUS              0
 343 #define CONFIG_ENV_SPI_CS               0
 344 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 345 #define CONFIG_ENV_SPI_MODE             0
 346 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 347 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 348 #define CONFIG_ENV_SECT_SIZE            0x10000
 349 #elif defined(CONFIG_SDCARD)
 350 #define CONFIG_SYS_EXTRA_ENV_RELOC
 351 #define CONFIG_ENV_IS_IN_MMC
 352 #define CONFIG_SYS_MMC_ENV_DEV          0
 353 #define CONFIG_ENV_SIZE                 0x2000
 354 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 355 #elif defined(CONFIG_NAND)
 356 #define CONFIG_SYS_EXTRA_ENV_RELOC
 357 #define CONFIG_ENV_IS_IN_NAND
 358 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 359 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 360 #elif defined(CONFIG_ENV_IS_NOWHERE)
 361 #define CONFIG_ENV_SIZE         0x2000
 362 #else
 363 #define CONFIG_ENV_IS_IN_FLASH
 364 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 365 #define CONFIG_ENV_SIZE         0x2000
 366 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 367 #endif
 368
 369 #define CONFIG_SYS_CLK_FREQ     66666666
 370 #define CONFIG_DDR_CLK_FREQ     133333333
 371
 372 #ifndef __ASSEMBLY__
 373 unsigned long get_board_sys_clk(void);
 374 unsigned long get_board_ddr_clk(void);
 375 #endif
 376
 377 /*
 378  * DDR Setup
 379  */
 380 #define CONFIG_SYS_SPD_BUS_NUM  0
 381 #define SPD_EEPROM_ADDRESS1     0x52
 382 #define SPD_EEPROM_ADDRESS2     0x54
 383 #define SPD_EEPROM_ADDRESS3     0x56
 384 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 385 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 386
 387 /*
 388  * IFC Definitions
 389  */
 390 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 391 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 392                                 + 0x8000000) | \
 393                                 CSPR_PORT_SIZE_16 | \
 394                                 CSPR_MSEL_NOR | \
 395                                 CSPR_V)
 396 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 397 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 398                                 CSPR_PORT_SIZE_16 | \
 399                                 CSPR_MSEL_NOR | \
 400                                 CSPR_V)
 401 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 402 /* NOR Flash Timing Params */
 403 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 404
 405 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 406                                 FTIM0_NOR_TEADC(0x5) | \
 407                                 FTIM0_NOR_TEAHC(0x5))
 408 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 409                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 410                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 411 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 412                                 FTIM2_NOR_TCH(0x4) | \
 413                                 FTIM2_NOR_TWPH(0x0E) | \
 414                                 FTIM2_NOR_TWP(0x1c))
 415 #define CONFIG_SYS_NOR_FTIM3    0x0
 416
 417 #define CONFIG_SYS_FLASH_QUIET_TEST
 418 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 419
 420 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 421 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 422 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 423 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 424
 425 #define CONFIG_SYS_FLASH_EMPTY_INFO
 426 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 427                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 428
 429 /* NAND Flash on IFC */
 430 #define CONFIG_NAND_FSL_IFC
 431 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 432 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 433 #define CONFIG_SYS_NAND_BASE            0xff800000
 434 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 435
 436 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 437 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 438                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 439                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 440                                 | CSPR_V)
 441 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 442
 443 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 444                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 445                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 446                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 447                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 448                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 449                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 450
 451 #define CONFIG_SYS_NAND_ONFI_DETECTION
 452
 453 /* ONFI NAND Flash mode0 Timing Params */
 454 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 455                                         FTIM0_NAND_TWP(0x18)   | \
 456                                         FTIM0_NAND_TWCHT(0x07) | \
 457                                         FTIM0_NAND_TWH(0x0a))
 458 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 459                                         FTIM1_NAND_TWBE(0x39)  | \
 460                                         FTIM1_NAND_TRR(0x0e)   | \
 461                                         FTIM1_NAND_TRP(0x18))
 462 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 463                                         FTIM2_NAND_TREH(0x0a) | \
 464                                         FTIM2_NAND_TWHRE(0x1e))
 465 #define CONFIG_SYS_NAND_FTIM3           0x0
 466
 467 #define CONFIG_SYS_NAND_DDR_LAW         11
 468 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 469 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 470 #define CONFIG_CMD_NAND
 471
 472 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 473
 474 #if defined(CONFIG_NAND)
 475 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 476 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 477 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 478 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 479 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 480 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 481 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 482 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 483 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 484 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 485 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 486 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 487 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 488 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 489 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 490 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 491 #else
 492 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 493 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 494 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 495 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 496 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 497 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 498 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 499 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 500 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 501 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 502 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 503 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 504 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 505 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 506 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 507 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 508 #endif
 509 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 510 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 511 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 512 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 513 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 514 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 515 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 516 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 517
 518 /* CPLD on IFC */
 519 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 520 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 521 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 522 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 523                                 | CSPR_PORT_SIZE_8 \
 524                                 | CSPR_MSEL_GPCM \
 525                                 | CSPR_V)
 526
 527 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 528 #define CONFIG_SYS_CSOR3        0x0
 529
 530 /* CPLD Timing parameters for IFC CS3 */
 531 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 532                                         FTIM0_GPCM_TEADC(0x0e) | \
 533                                         FTIM0_GPCM_TEAHC(0x0e))
 534 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 535                                         FTIM1_GPCM_TRAD(0x1f))
 536 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 537                                         FTIM2_GPCM_TCH(0x8) | \
 538                                         FTIM2_GPCM_TWP(0x1f))
 539 #define CONFIG_SYS_CS3_FTIM3            0x0
 540
 541 #if defined(CONFIG_RAMBOOT_PBL)
 542 #define CONFIG_SYS_RAMBOOT
 543 #endif
 544
 545 /* I2C */
 546 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 547 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 548 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 549 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 550
 551 #define I2C_MUX_CH_DEFAULT      0x8
 552 #define I2C_MUX_CH_VOL_MONITOR  0xa
 553 #define I2C_MUX_CH_VSC3316_FS   0xc
 554 #define I2C_MUX_CH_VSC3316_BS   0xd
 555
 556 /* Voltage monitor on channel 2*/
 557 #define I2C_VOL_MONITOR_ADDR            0x40
 558 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 559 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 560 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 561
 562 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
 563 #ifndef CONFIG_SPL_BUILD
 564 #define CONFIG_VID
 565 #endif
 566 #define CONFIG_VOL_MONITOR_IR36021_SET
 567 #define CONFIG_VOL_MONITOR_IR36021_READ
 568 /* The lowest and highest voltage allowed for T4240RDB */
 569 #define VDD_MV_MIN                      819
 570 #define VDD_MV_MAX                      1212
 571
 572 /*
 573  * eSPI - Enhanced SPI
 574  */
 575 #define CONFIG_SF_DEFAULT_SPEED         10000000
 576 #define CONFIG_SF_DEFAULT_MODE          0
 577
 578 /* Qman/Bman */
 579 #ifndef CONFIG_NOBQFMAN
 580 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 581 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 582 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 583 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 584 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 585 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 586 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 587 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 588 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 589 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 590                                         CONFIG_SYS_BMAN_CENA_SIZE)
 591 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 592 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 593 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 594 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 595 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 596 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 597 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 598 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 599 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 600 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 601 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 602                                         CONFIG_SYS_QMAN_CENA_SIZE)
 603 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 604 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 605
 606 #define CONFIG_SYS_DPAA_FMAN
 607 #define CONFIG_SYS_DPAA_PME
 608 #define CONFIG_SYS_PMAN
 609 #define CONFIG_SYS_DPAA_DCE
 610 #define CONFIG_SYS_DPAA_RMAN
 611 #define CONFIG_SYS_INTERLAKEN
 612
 613 /* Default address of microcode for the Linux Fman driver */
 614 #if defined(CONFIG_SPIFLASH)
 615 /*
 616  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 617  * env, so we got 0x110000.
 618  */
 619 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 620 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 621 #elif defined(CONFIG_SDCARD)
 622 /*
 623  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 624  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 625  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 626  */
 627 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 628 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 629 #elif defined(CONFIG_NAND)
 630 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 631 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 632 #else
 633 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 634 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 635 #endif
 636 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 637 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 638 #endif /* CONFIG_NOBQFMAN */
 639
 640 #ifdef CONFIG_SYS_DPAA_FMAN
 641 #define CONFIG_FMAN_ENET
 642 #define CONFIG_PHYLIB_10G
 643 #define CONFIG_PHY_VITESSE
 644 #define CONFIG_PHY_CORTINA
 645 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 646 #define CONFIG_CORTINA_FW_ADDR          0xefe00000
 647 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 648 #define CONFIG_PHY_TERANETICS
 649 #define SGMII_PHY_ADDR1 0x0
 650 #define SGMII_PHY_ADDR2 0x1
 651 #define SGMII_PHY_ADDR3 0x2
 652 #define SGMII_PHY_ADDR4 0x3
 653 #define SGMII_PHY_ADDR5 0x4
 654 #define SGMII_PHY_ADDR6 0x5
 655 #define SGMII_PHY_ADDR7 0x6
 656 #define SGMII_PHY_ADDR8 0x7
 657 #define FM1_10GEC1_PHY_ADDR     0x10
 658 #define FM1_10GEC2_PHY_ADDR     0x11
 659 #define FM2_10GEC1_PHY_ADDR     0x12
 660 #define FM2_10GEC2_PHY_ADDR     0x13
 661 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 662 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 663 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 664 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 665 #endif
 666
 667 /* SATA */
 668 #ifdef CONFIG_FSL_SATA_V2
 669 #define CONFIG_LIBATA
 670 #define CONFIG_FSL_SATA
 671
 672 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 673 #define CONFIG_SATA1
 674 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 675 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 676 #define CONFIG_SATA2
 677 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 678 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 679
 680 #define CONFIG_LBA48
 681 #define CONFIG_CMD_SATA
 682 #endif
 683
 684 #ifdef CONFIG_FMAN_ENET
 685 #define CONFIG_MII              /* MII PHY management */
 686 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 687 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 688 #endif
 689
 690 /*
 691 * USB
 692 */
 693 #define CONFIG_USB_EHCI
 694 #define CONFIG_USB_EHCI_FSL
 695 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 696 #define CONFIG_HAS_FSL_DR_USB
 697
 698 #ifdef CONFIG_MMC
 699 #define CONFIG_FSL_ESDHC
 700 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 701 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 702 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 703 #endif
 704
 705 /* Hash command with SHA acceleration supported in hardware */
 706 #ifdef CONFIG_FSL_CAAM
 707 #define CONFIG_CMD_HASH
 708 #define CONFIG_SHA_HW_ACCEL
 709 #endif
 710
 711
 712 #define __USB_PHY_TYPE  utmi
 713
 714 /*
 715  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 716  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 717  * interleaving. It can be cacheline, page, bank, superbank.
 718  * See doc/README.fsl-ddr for details.
 719  */
 720 #ifdef CONFIG_ARCH_T4240
 721 #define CTRL_INTLV_PREFERED 3way_4KB
 722 #else
 723 #define CTRL_INTLV_PREFERED cacheline
 724 #endif
 725
 726 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 727         "hwconfig=fsl_ddr:"                                     \
 728         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 729         "bank_intlv=auto;"                                      \
 730         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 731         "netdev=eth0\0"                                         \
 732         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 733         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 734         "tftpflash=tftpboot $loadaddr $uboot && "               \
 735         "protect off $ubootaddr +$filesize && "                 \
 736         "erase $ubootaddr +$filesize && "                       \
 737         "cp.b $loadaddr $ubootaddr $filesize && "               \
 738         "protect on $ubootaddr +$filesize && "                  \
 739         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 740         "consoledev=ttyS0\0"                                    \
 741         "ramdiskaddr=2000000\0"                                 \
 742         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 743         "fdtaddr=1e00000\0"                                     \
 744         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 745         "bdev=sda3\0"
 746
 747 #define CONFIG_HVBOOT                                   \
 748         "setenv bootargs config-addr=0x60000000; "      \
 749         "bootm 0x01000000 - 0x00f00000"
 750
 751 #define CONFIG_LINUX                                    \
 752         "setenv bootargs root=/dev/ram rw "             \
 753         "console=$consoledev,$baudrate $othbootargs;"   \
 754         "setenv ramdiskaddr 0x02000000;"                \
 755         "setenv fdtaddr 0x00c00000;"                    \
 756         "setenv loadaddr 0x1000000;"                    \
 757         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 758
 759 #define CONFIG_HDBOOT                                   \
 760         "setenv bootargs root=/dev/$bdev rw "           \
 761         "console=$consoledev,$baudrate $othbootargs;"   \
 762         "tftp $loadaddr $bootfile;"                     \
 763         "tftp $fdtaddr $fdtfile;"                       \
 764         "bootm $loadaddr - $fdtaddr"
 765
 766 #define CONFIG_NFSBOOTCOMMAND                   \
 767         "setenv bootargs root=/dev/nfs rw "     \
 768         "nfsroot=$serverip:$rootpath "          \
 769         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 770         "console=$consoledev,$baudrate $othbootargs;"   \
 771         "tftp $loadaddr $bootfile;"             \
 772         "tftp $fdtaddr $fdtfile;"               \
 773         "bootm $loadaddr - $fdtaddr"
 774
 775 #define CONFIG_RAMBOOTCOMMAND                           \
 776         "setenv bootargs root=/dev/ram rw "             \
 777         "console=$consoledev,$baudrate $othbootargs;"   \
 778         "tftp $ramdiskaddr $ramdiskfile;"               \
 779         "tftp $loadaddr $bootfile;"                     \
 780         "tftp $fdtaddr $fdtfile;"                       \
 781         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 782
 783 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 784
 785 #include <asm/fsl_secure_boot.h>
 786
 787 #endif  /* __CONFIG_H */