include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T4240 RDB board configuration file
   8  */
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_FSL_SATA_V2
  13 #define CONFIG_PCIE4
  14
  15 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  19 #ifndef CONFIG_SDCARD
  20 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  21 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  22 #else
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  25 #define CONFIG_SPL_PAD_TO               0x40000
  26 #define CONFIG_SPL_MAX_SIZE             0x28000
  27 #define RESET_VECTOR_OFFSET             0x27FFC
  28 #define BOOT_PAGE_OFFSET                0x27000
  29
  30 #ifdef  CONFIG_SDCARD
  31 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  32 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  33 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  34 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  35 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  36 #ifndef CONFIG_SPL_BUILD
  37 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  38 #endif
  39 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  40 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  41 #define CONFIG_SPL_MMC_BOOT
  42 #endif
  43
  44 #ifdef CONFIG_SPL_BUILD
  45 #define CONFIG_SPL_SKIP_RELOCATE
  46 #define CONFIG_SPL_COMMON_INIT_DDR
  47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  48 #endif
  49
  50 #endif
  51 #endif /* CONFIG_RAMBOOT_PBL */
  52
  53 #define CONFIG_DDR_ECC
  54
  55 /* High Level Configuration Options */
  56 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  57
  58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  59 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  60 #endif
  61
  62 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  63 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  64 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  65 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  66 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  67 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  68 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  69
  70 #define CONFIG_ENV_OVERWRITE
  71
  72 /*
  73  * These can be toggled for performance analysis, otherwise use default.
  74  */
  75 #define CONFIG_SYS_CACHE_STASHING
  76 #define CONFIG_BTB                      /* toggle branch predition */
  77 #ifdef CONFIG_DDR_ECC
  78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  79 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  80 #endif
  81
  82 #define CONFIG_ENABLE_36BIT_PHYS
  83
  84 #define CONFIG_ADDR_MAP
  85 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  86
  87 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  88 #define CONFIG_SYS_MEMTEST_END          0x00400000
  89
  90 /*
  91  *  Config the L3 Cache as L3 SRAM
  92  */
  93 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  94 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  95 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  96 #ifdef CONFIG_RAMBOOT_PBL
  97 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
  98 #endif
  99 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 100 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 101 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 102
 103 #define CONFIG_SYS_DCSRBAR              0xf0000000
 104 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 105
 106 /*
 107  * DDR Setup
 108  */
 109 #define CONFIG_VERY_BIG_RAM
 110 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 111 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 112
 113 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 114 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 115 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 116
 117 #define CONFIG_DDR_SPD
 118
 119 /*
 120  * IFC Definitions
 121  */
 122 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 123 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 124
 125 #ifdef CONFIG_SPL_BUILD
 126 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 127 #else
 128 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 129 #endif
 130
 131 #define CONFIG_HWCONFIG
 132
 133 /* define to use L1 as initial stack */
 134 #define CONFIG_L1_INIT_RAM
 135 #define CONFIG_SYS_INIT_RAM_LOCK
 136 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 137 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 138 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 139 /* The assembler doesn't like typecast */
 140 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 141         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 142           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 143 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 144
 145 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 146                                         GENERATED_GBL_DATA_SIZE)
 147 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 148
 149 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 150 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 151
 152 /* Serial Port - controlled on board with jumper J8
 153  * open - index 2
 154  * shorted - index 1
 155  */
 156 #define CONFIG_SYS_NS16550_SERIAL
 157 #define CONFIG_SYS_NS16550_REG_SIZE     1
 158 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 159
 160 #define CONFIG_SYS_BAUDRATE_TABLE       \
 161         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 162
 163 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 164 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 165 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 166 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 167
 168 /* I2C */
 169 #define CONFIG_SYS_I2C
 170 #define CONFIG_SYS_I2C_FSL
 171 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 172 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 173 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 174 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 175
 176 /*
 177  * General PCI
 178  * Memory space is mapped 1-1, but I/O space must start from 0.
 179  */
 180
 181 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 182 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 183 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 184 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 185 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 186 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 187 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 188 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 189 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 190
 191 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 192 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 193 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 194 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 195 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 196 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 197 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 198 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 199 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 200
 201 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 202 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 203 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 204 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 205 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 206 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 207 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 208 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 209 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 210
 211 /* controller 4, Base address 203000 */
 212 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 213 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 214 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 215 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 216 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 217 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 218
 219 #ifdef CONFIG_PCI
 220 #define CONFIG_PCI_INDIRECT_BRIDGE
 221
 222 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 223 #endif  /* CONFIG_PCI */
 224
 225 /* SATA */
 226 #ifdef CONFIG_FSL_SATA_V2
 227 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 228 #define CONFIG_SATA1
 229 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 230 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 231 #define CONFIG_SATA2
 232 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 233 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 234
 235 #define CONFIG_LBA48
 236 #endif
 237
 238 #ifdef CONFIG_FMAN_ENET
 239 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 240 #endif
 241
 242 /*
 243  * Environment
 244  */
 245 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 246 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 247
 248 /*
 249  * Command line configuration.
 250  */
 251
 252 /*
 253  * Miscellaneous configurable options
 254  */
 255 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 256
 257 /*
 258  * For booting Linux, the board info and command line data
 259  * have to be in the first 64 MB of memory, since this is
 260  * the maximum mapped by the Linux kernel during initialization.
 261  */
 262 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 263 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 264
 265 #ifdef CONFIG_CMD_KGDB
 266 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 267 #endif
 268
 269 /*
 270  * Environment Configuration
 271  */
 272 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 273 #define CONFIG_BOOTFILE         "uImage"
 274 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 275
 276 /* default location for tftp and bootm */
 277 #define CONFIG_LOADADDR         1000000
 278
 279 #define CONFIG_HVBOOT                                   \
 280         "setenv bootargs config-addr=0x60000000; "      \
 281         "bootm 0x01000000 - 0x00f00000"
 282
 283 #if defined(CONFIG_SPIFLASH)
 284 #define CONFIG_ENV_SPI_BUS              0
 285 #define CONFIG_ENV_SPI_CS               0
 286 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 287 #define CONFIG_ENV_SPI_MODE             0
 288 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 289 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 290 #define CONFIG_ENV_SECT_SIZE            0x10000
 291 #elif defined(CONFIG_SDCARD)
 292 #define CONFIG_SYS_MMC_ENV_DEV          0
 293 #define CONFIG_ENV_SIZE                 0x2000
 294 #define CONFIG_ENV_OFFSET               (512 * 0x800)
 295 #elif defined(CONFIG_NAND)
 296 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 297 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 298 #elif defined(CONFIG_ENV_IS_NOWHERE)
 299 #define CONFIG_ENV_SIZE         0x2000
 300 #else
 301 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 302 #define CONFIG_ENV_SIZE         0x2000
 303 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 304 #endif
 305
 306 #define CONFIG_SYS_CLK_FREQ     66666666
 307 #define CONFIG_DDR_CLK_FREQ     133333333
 308
 309 #ifndef __ASSEMBLY__
 310 unsigned long get_board_sys_clk(void);
 311 unsigned long get_board_ddr_clk(void);
 312 #endif
 313
 314 /*
 315  * DDR Setup
 316  */
 317 #define CONFIG_SYS_SPD_BUS_NUM  0
 318 #define SPD_EEPROM_ADDRESS1     0x52
 319 #define SPD_EEPROM_ADDRESS2     0x54
 320 #define SPD_EEPROM_ADDRESS3     0x56
 321 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 322 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 323
 324 /*
 325  * IFC Definitions
 326  */
 327 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 328 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 329                                 + 0x8000000) | \
 330                                 CSPR_PORT_SIZE_16 | \
 331                                 CSPR_MSEL_NOR | \
 332                                 CSPR_V)
 333 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 334 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 335                                 CSPR_PORT_SIZE_16 | \
 336                                 CSPR_MSEL_NOR | \
 337                                 CSPR_V)
 338 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 339 /* NOR Flash Timing Params */
 340 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 341
 342 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 343                                 FTIM0_NOR_TEADC(0x5) | \
 344                                 FTIM0_NOR_TEAHC(0x5))
 345 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 346                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 347                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 348 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 349                                 FTIM2_NOR_TCH(0x4) | \
 350                                 FTIM2_NOR_TWPH(0x0E) | \
 351                                 FTIM2_NOR_TWP(0x1c))
 352 #define CONFIG_SYS_NOR_FTIM3    0x0
 353
 354 #define CONFIG_SYS_FLASH_QUIET_TEST
 355 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 356
 357 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 358 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 359 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 360 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 361
 362 #define CONFIG_SYS_FLASH_EMPTY_INFO
 363 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 364                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 365
 366 /* NAND Flash on IFC */
 367 #define CONFIG_NAND_FSL_IFC
 368 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 369 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 370 #define CONFIG_SYS_NAND_BASE            0xff800000
 371 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 372
 373 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 374 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 375                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 376                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 377                                 | CSPR_V)
 378 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 379
 380 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 381                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 382                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 383                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 384                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 385                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 386                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 387
 388 #define CONFIG_SYS_NAND_ONFI_DETECTION
 389
 390 /* ONFI NAND Flash mode0 Timing Params */
 391 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 392                                         FTIM0_NAND_TWP(0x18)   | \
 393                                         FTIM0_NAND_TWCHT(0x07) | \
 394                                         FTIM0_NAND_TWH(0x0a))
 395 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 396                                         FTIM1_NAND_TWBE(0x39)  | \
 397                                         FTIM1_NAND_TRR(0x0e)   | \
 398                                         FTIM1_NAND_TRP(0x18))
 399 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 400                                         FTIM2_NAND_TREH(0x0a) | \
 401                                         FTIM2_NAND_TWHRE(0x1e))
 402 #define CONFIG_SYS_NAND_FTIM3           0x0
 403
 404 #define CONFIG_SYS_NAND_DDR_LAW         11
 405 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 406 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 407
 408 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 409
 410 #if defined(CONFIG_NAND)
 411 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 412 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 413 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 414 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 415 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 416 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 417 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 418 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 419 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 420 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 421 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 422 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 423 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 424 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 425 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 426 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 427 #else
 428 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 429 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 430 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 431 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 432 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 433 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 434 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 435 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 436 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 437 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 438 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 439 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 440 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 441 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 442 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 443 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 444 #endif
 445 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 446 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 447 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 448 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 449 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 450 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 451 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 452 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 453
 454 /* CPLD on IFC */
 455 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 456 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 457 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 458 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 459                                 | CSPR_PORT_SIZE_8 \
 460                                 | CSPR_MSEL_GPCM \
 461                                 | CSPR_V)
 462
 463 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 464 #define CONFIG_SYS_CSOR3        0x0
 465
 466 /* CPLD Timing parameters for IFC CS3 */
 467 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 468                                         FTIM0_GPCM_TEADC(0x0e) | \
 469                                         FTIM0_GPCM_TEAHC(0x0e))
 470 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 471                                         FTIM1_GPCM_TRAD(0x1f))
 472 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 473                                         FTIM2_GPCM_TCH(0x8) | \
 474                                         FTIM2_GPCM_TWP(0x1f))
 475 #define CONFIG_SYS_CS3_FTIM3            0x0
 476
 477 #if defined(CONFIG_RAMBOOT_PBL)
 478 #define CONFIG_SYS_RAMBOOT
 479 #endif
 480
 481 /* I2C */
 482 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 483 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 484 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 485 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 486
 487 #define I2C_MUX_CH_DEFAULT      0x8
 488 #define I2C_MUX_CH_VOL_MONITOR  0xa
 489 #define I2C_MUX_CH_VSC3316_FS   0xc
 490 #define I2C_MUX_CH_VSC3316_BS   0xd
 491
 492 /* Voltage monitor on channel 2*/
 493 #define I2C_VOL_MONITOR_ADDR            0x40
 494 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 495 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 496 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 497
 498 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
 499 #ifndef CONFIG_SPL_BUILD
 500 #define CONFIG_VID
 501 #endif
 502 #define CONFIG_VOL_MONITOR_IR36021_SET
 503 #define CONFIG_VOL_MONITOR_IR36021_READ
 504 /* The lowest and highest voltage allowed for T4240RDB */
 505 #define VDD_MV_MIN                      819
 506 #define VDD_MV_MAX                      1212
 507
 508 /*
 509  * eSPI - Enhanced SPI
 510  */
 511 #define CONFIG_SF_DEFAULT_SPEED         10000000
 512 #define CONFIG_SF_DEFAULT_MODE          0
 513
 514 /* Qman/Bman */
 515 #ifndef CONFIG_NOBQFMAN
 516 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 517 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 518 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 519 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 520 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 521 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 522 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 523 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 524 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 525                                         CONFIG_SYS_BMAN_CENA_SIZE)
 526 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 527 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 528 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 529 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 530 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 531 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 532 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 533 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 534 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 535 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 536 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 537                                         CONFIG_SYS_QMAN_CENA_SIZE)
 538 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 539 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 540
 541 #define CONFIG_SYS_DPAA_FMAN
 542 #define CONFIG_SYS_DPAA_PME
 543 #define CONFIG_SYS_PMAN
 544 #define CONFIG_SYS_DPAA_DCE
 545 #define CONFIG_SYS_DPAA_RMAN
 546 #define CONFIG_SYS_INTERLAKEN
 547
 548 /* Default address of microcode for the Linux Fman driver */
 549 #if defined(CONFIG_SPIFLASH)
 550 /*
 551  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 552  * env, so we got 0x110000.
 553  */
 554 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 555 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 556 #elif defined(CONFIG_SDCARD)
 557 /*
 558  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 559  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 560  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 561  */
 562 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 563 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 564 #elif defined(CONFIG_NAND)
 565 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 566 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 567 #else
 568 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 569 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 570 #endif
 571 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 572 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 573 #endif /* CONFIG_NOBQFMAN */
 574
 575 #ifdef CONFIG_SYS_DPAA_FMAN
 576 #define CONFIG_FMAN_ENET
 577 #define CONFIG_PHYLIB_10G
 578 #define CONFIG_PHY_VITESSE
 579 #define CONFIG_PHY_CORTINA
 580 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 581 #define CONFIG_CORTINA_FW_ADDR          0xefe00000
 582 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 583 #define CONFIG_PHY_TERANETICS
 584 #define SGMII_PHY_ADDR1 0x0
 585 #define SGMII_PHY_ADDR2 0x1
 586 #define SGMII_PHY_ADDR3 0x2
 587 #define SGMII_PHY_ADDR4 0x3
 588 #define SGMII_PHY_ADDR5 0x4
 589 #define SGMII_PHY_ADDR6 0x5
 590 #define SGMII_PHY_ADDR7 0x6
 591 #define SGMII_PHY_ADDR8 0x7
 592 #define FM1_10GEC1_PHY_ADDR     0x10
 593 #define FM1_10GEC2_PHY_ADDR     0x11
 594 #define FM2_10GEC1_PHY_ADDR     0x12
 595 #define FM2_10GEC2_PHY_ADDR     0x13
 596 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 597 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 598 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 599 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 600 #endif
 601
 602 /* SATA */
 603 #ifdef CONFIG_FSL_SATA_V2
 604 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 605 #define CONFIG_SATA1
 606 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 607 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 608 #define CONFIG_SATA2
 609 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 610 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 611
 612 #define CONFIG_LBA48
 613 #endif
 614
 615 #ifdef CONFIG_FMAN_ENET
 616 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 617 #endif
 618
 619 /*
 620 * USB
 621 */
 622 #define CONFIG_USB_EHCI_FSL
 623 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 624 #define CONFIG_HAS_FSL_DR_USB
 625
 626 #ifdef CONFIG_MMC
 627 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 628 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 629 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 630 #endif
 631
 632
 633 #define __USB_PHY_TYPE  utmi
 634
 635 /*
 636  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 637  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 638  * interleaving. It can be cacheline, page, bank, superbank.
 639  * See doc/README.fsl-ddr for details.
 640  */
 641 #ifdef CONFIG_ARCH_T4240
 642 #define CTRL_INTLV_PREFERED 3way_4KB
 643 #else
 644 #define CTRL_INTLV_PREFERED cacheline
 645 #endif
 646
 647 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 648         "hwconfig=fsl_ddr:"                                     \
 649         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 650         "bank_intlv=auto;"                                      \
 651         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 652         "netdev=eth0\0"                                         \
 653         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 654         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 655         "tftpflash=tftpboot $loadaddr $uboot && "               \
 656         "protect off $ubootaddr +$filesize && "                 \
 657         "erase $ubootaddr +$filesize && "                       \
 658         "cp.b $loadaddr $ubootaddr $filesize && "               \
 659         "protect on $ubootaddr +$filesize && "                  \
 660         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 661         "consoledev=ttyS0\0"                                    \
 662         "ramdiskaddr=2000000\0"                                 \
 663         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 664         "fdtaddr=1e00000\0"                                     \
 665         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 666         "bdev=sda3\0"
 667
 668 #define CONFIG_HVBOOT                                   \
 669         "setenv bootargs config-addr=0x60000000; "      \
 670         "bootm 0x01000000 - 0x00f00000"
 671
 672 #define CONFIG_LINUX                                    \
 673         "setenv bootargs root=/dev/ram rw "             \
 674         "console=$consoledev,$baudrate $othbootargs;"   \
 675         "setenv ramdiskaddr 0x02000000;"                \
 676         "setenv fdtaddr 0x00c00000;"                    \
 677         "setenv loadaddr 0x1000000;"                    \
 678         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 679
 680 #define CONFIG_HDBOOT                                   \
 681         "setenv bootargs root=/dev/$bdev rw "           \
 682         "console=$consoledev,$baudrate $othbootargs;"   \
 683         "tftp $loadaddr $bootfile;"                     \
 684         "tftp $fdtaddr $fdtfile;"                       \
 685         "bootm $loadaddr - $fdtaddr"
 686
 687 #define CONFIG_NFSBOOTCOMMAND                   \
 688         "setenv bootargs root=/dev/nfs rw "     \
 689         "nfsroot=$serverip:$rootpath "          \
 690         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 691         "console=$consoledev,$baudrate $othbootargs;"   \
 692         "tftp $loadaddr $bootfile;"             \
 693         "tftp $fdtaddr $fdtfile;"               \
 694         "bootm $loadaddr - $fdtaddr"
 695
 696 #define CONFIG_RAMBOOTCOMMAND                           \
 697         "setenv bootargs root=/dev/ram rw "             \
 698         "console=$consoledev,$baudrate $othbootargs;"   \
 699         "tftp $ramdiskaddr $ramdiskfile;"               \
 700         "tftp $loadaddr $bootfile;"                     \
 701         "tftp $fdtaddr $fdtfile;"                       \
 702         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 703
 704 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 705
 706 #include <asm/fsl_secure_boot.h>
 707
 708 #endif  /* __CONFIG_H */