1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
8 * T4240 RDB board configuration file
13 #define CONFIG_FSL_SATA_V2
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
18 #ifdef CONFIG_RAMBOOT_PBL
19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_PAD_TO 0x40000
26 #define CONFIG_SPL_MAX_SIZE 0x28000
27 #define RESET_VECTOR_OFFSET 0x27FFC
28 #define BOOT_PAGE_OFFSET 0x27000
31 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
32 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
33 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
34 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
35 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
36 #ifndef CONFIG_SPL_BUILD
37 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
39 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
42 #ifdef CONFIG_SPL_BUILD
43 #define CONFIG_SPL_SKIP_RELOCATE
44 #define CONFIG_SPL_COMMON_INIT_DDR
45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
49 #endif /* CONFIG_RAMBOOT_PBL */
51 #define CONFIG_DDR_ECC
53 /* High Level Configuration Options */
54 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
56 #ifndef CONFIG_RESET_VECTOR_ADDRESS
57 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
60 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
61 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
62 #define CONFIG_PCIE1 /* PCIE controller 1 */
63 #define CONFIG_PCIE2 /* PCIE controller 2 */
64 #define CONFIG_PCIE3 /* PCIE controller 3 */
65 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
67 #define CONFIG_ENV_OVERWRITE
70 * These can be toggled for performance analysis, otherwise use default.
72 #define CONFIG_SYS_CACHE_STASHING
73 #define CONFIG_BTB /* toggle branch predition */
75 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
76 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
79 #define CONFIG_ENABLE_36BIT_PHYS
81 #define CONFIG_ADDR_MAP
82 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
84 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
85 #define CONFIG_SYS_MEMTEST_END 0x00400000
88 * Config the L3 Cache as L3 SRAM
90 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
91 #define CONFIG_SYS_L3_SIZE (512 << 10)
92 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
93 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
94 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
95 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
96 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
98 #define CONFIG_SYS_DCSRBAR 0xf0000000
99 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
104 #define CONFIG_VERY_BIG_RAM
105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
109 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
111 #define CONFIG_DDR_SPD
116 #define CONFIG_SYS_FLASH_BASE 0xe0000000
117 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
119 #ifdef CONFIG_SPL_BUILD
120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
125 #define CONFIG_HWCONFIG
127 /* define to use L1 as initial stack */
128 #define CONFIG_L1_INIT_RAM
129 #define CONFIG_SYS_INIT_RAM_LOCK
130 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
131 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
132 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
133 /* The assembler doesn't like typecast */
134 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
135 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
136 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
137 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
139 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
140 GENERATED_GBL_DATA_SIZE)
141 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
143 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
144 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
146 /* Serial Port - controlled on board with jumper J8
150 #define CONFIG_SYS_NS16550_SERIAL
151 #define CONFIG_SYS_NS16550_REG_SIZE 1
152 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
154 #define CONFIG_SYS_BAUDRATE_TABLE \
155 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
157 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
158 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
159 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
160 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
163 #ifndef CONFIG_DM_I2C
164 #define CONFIG_SYS_I2C
165 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
166 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
167 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
168 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
170 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
171 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
174 #define CONFIG_SYS_I2C_FSL
178 * Memory space is mapped 1-1, but I/O space must start from 0.
181 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
182 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
183 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
184 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
185 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
187 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
188 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
189 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
190 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
191 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
193 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
194 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
195 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
196 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
197 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
199 /* controller 4, Base address 203000 */
200 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
201 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
202 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
205 #if !defined(CONFIG_DM_PCI)
206 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
207 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
208 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
209 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
210 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
211 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
212 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
213 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
214 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
215 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
216 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
217 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
218 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
219 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
220 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
221 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
222 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
223 #define CONFIG_PCI_INDIRECT_BRIDGE
226 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
227 #endif /* CONFIG_PCI */
230 #ifdef CONFIG_FSL_SATA_V2
231 #define CONFIG_SYS_SATA_MAX_DEVICE 2
233 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
234 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
236 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
237 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
242 #ifdef CONFIG_FMAN_ENET
243 #define CONFIG_ETHPRIME "FM1@DTSEC1"
249 #define CONFIG_LOADS_ECHO /* echo on for serial download */
250 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
253 * Command line configuration.
257 * Miscellaneous configurable options
259 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
262 * For booting Linux, the board info and command line data
263 * have to be in the first 64 MB of memory, since this is
264 * the maximum mapped by the Linux kernel during initialization.
266 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
267 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
269 #ifdef CONFIG_CMD_KGDB
270 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
274 * Environment Configuration
276 #define CONFIG_ROOTPATH "/opt/nfsroot"
277 #define CONFIG_BOOTFILE "uImage"
278 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
280 /* default location for tftp and bootm */
281 #define CONFIG_LOADADDR 1000000
283 #define CONFIG_HVBOOT \
284 "setenv bootargs config-addr=0x60000000; " \
285 "bootm 0x01000000 - 0x00f00000"
287 #if defined(CONFIG_SPIFLASH)
288 #elif defined(CONFIG_SDCARD)
289 #define CONFIG_SYS_MMC_ENV_DEV 0
292 #define CONFIG_SYS_CLK_FREQ 66666666
293 #define CONFIG_DDR_CLK_FREQ 133333333
296 unsigned long get_board_sys_clk(void);
297 unsigned long get_board_ddr_clk(void);
303 #define CONFIG_SYS_SPD_BUS_NUM 0
304 #define SPD_EEPROM_ADDRESS1 0x52
305 #define SPD_EEPROM_ADDRESS2 0x54
306 #define SPD_EEPROM_ADDRESS3 0x56
307 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
308 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
313 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
314 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
316 CSPR_PORT_SIZE_16 | \
319 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
320 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
321 CSPR_PORT_SIZE_16 | \
324 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
325 /* NOR Flash Timing Params */
326 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
328 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
329 FTIM0_NOR_TEADC(0x5) | \
330 FTIM0_NOR_TEAHC(0x5))
331 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
332 FTIM1_NOR_TRAD_NOR(0x1A) |\
333 FTIM1_NOR_TSEQRAD_NOR(0x13))
334 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
335 FTIM2_NOR_TCH(0x4) | \
336 FTIM2_NOR_TWPH(0x0E) | \
338 #define CONFIG_SYS_NOR_FTIM3 0x0
340 #define CONFIG_SYS_FLASH_QUIET_TEST
341 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
343 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
344 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
345 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
346 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
348 #define CONFIG_SYS_FLASH_EMPTY_INFO
349 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
350 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
352 /* NAND Flash on IFC */
353 #define CONFIG_NAND_FSL_IFC
354 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
355 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
356 #define CONFIG_SYS_NAND_BASE 0xff800000
357 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
359 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
360 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
361 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
362 | CSPR_MSEL_NAND /* MSEL = NAND */ \
364 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
366 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
367 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
368 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
369 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
370 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
371 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
372 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
374 #define CONFIG_SYS_NAND_ONFI_DETECTION
376 /* ONFI NAND Flash mode0 Timing Params */
377 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
378 FTIM0_NAND_TWP(0x18) | \
379 FTIM0_NAND_TWCHT(0x07) | \
380 FTIM0_NAND_TWH(0x0a))
381 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
382 FTIM1_NAND_TWBE(0x39) | \
383 FTIM1_NAND_TRR(0x0e) | \
384 FTIM1_NAND_TRP(0x18))
385 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
386 FTIM2_NAND_TREH(0x0a) | \
387 FTIM2_NAND_TWHRE(0x1e))
388 #define CONFIG_SYS_NAND_FTIM3 0x0
390 #define CONFIG_SYS_NAND_DDR_LAW 11
391 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
392 #define CONFIG_SYS_MAX_NAND_DEVICE 1
394 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
396 #if defined(CONFIG_MTD_RAW_NAND)
397 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
398 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
399 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
400 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
401 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
402 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
403 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
404 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
405 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
406 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
407 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
408 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
409 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
410 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
411 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
412 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
414 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
415 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
416 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
417 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
418 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
419 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
420 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
421 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
422 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
423 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
424 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
425 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
426 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
427 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
428 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
429 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
431 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
432 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
433 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
434 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
435 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
436 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
437 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
438 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
441 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
442 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
443 #define CONFIG_SYS_CSPR3_EXT (0xf)
444 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
449 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
450 #define CONFIG_SYS_CSOR3 0x0
452 /* CPLD Timing parameters for IFC CS3 */
453 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
454 FTIM0_GPCM_TEADC(0x0e) | \
455 FTIM0_GPCM_TEAHC(0x0e))
456 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
457 FTIM1_GPCM_TRAD(0x1f))
458 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
459 FTIM2_GPCM_TCH(0x8) | \
460 FTIM2_GPCM_TWP(0x1f))
461 #define CONFIG_SYS_CS3_FTIM3 0x0
463 #if defined(CONFIG_RAMBOOT_PBL)
464 #define CONFIG_SYS_RAMBOOT
468 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
469 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
470 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
471 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
473 #define I2C_MUX_CH_DEFAULT 0x8
474 #define I2C_MUX_CH_VOL_MONITOR 0xa
475 #define I2C_MUX_CH_VSC3316_FS 0xc
476 #define I2C_MUX_CH_VSC3316_BS 0xd
478 /* Voltage monitor on channel 2*/
479 #define I2C_VOL_MONITOR_ADDR 0x40
480 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
481 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
482 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
484 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
485 #ifndef CONFIG_SPL_BUILD
488 #define CONFIG_VOL_MONITOR_IR36021_SET
489 #define CONFIG_VOL_MONITOR_IR36021_READ
490 /* The lowest and highest voltage allowed for T4240RDB */
491 #define VDD_MV_MIN 819
492 #define VDD_MV_MAX 1212
495 * eSPI - Enhanced SPI
499 #ifndef CONFIG_NOBQFMAN
500 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
501 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
502 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
503 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
504 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
505 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
506 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
507 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
508 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
509 CONFIG_SYS_BMAN_CENA_SIZE)
510 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
511 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
512 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
513 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
514 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
515 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
516 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
517 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
518 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
519 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
520 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
521 CONFIG_SYS_QMAN_CENA_SIZE)
522 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
523 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
525 #define CONFIG_SYS_DPAA_FMAN
526 #define CONFIG_SYS_DPAA_PME
527 #define CONFIG_SYS_PMAN
528 #define CONFIG_SYS_DPAA_DCE
529 #define CONFIG_SYS_DPAA_RMAN
530 #define CONFIG_SYS_INTERLAKEN
532 /* Default address of microcode for the Linux Fman driver */
533 #if defined(CONFIG_SPIFLASH)
535 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
536 * env, so we got 0x110000.
538 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
539 #elif defined(CONFIG_SDCARD)
541 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
542 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
543 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
545 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
546 #elif defined(CONFIG_MTD_RAW_NAND)
547 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
549 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
551 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
552 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
553 #endif /* CONFIG_NOBQFMAN */
555 #ifdef CONFIG_SYS_DPAA_FMAN
556 #define CONFIG_CORTINA_FW_ADDR 0xefe00000
557 #define CONFIG_CORTINA_FW_LENGTH 0x40000
558 #define SGMII_PHY_ADDR1 0x0
559 #define SGMII_PHY_ADDR2 0x1
560 #define SGMII_PHY_ADDR3 0x2
561 #define SGMII_PHY_ADDR4 0x3
562 #define SGMII_PHY_ADDR5 0x4
563 #define SGMII_PHY_ADDR6 0x5
564 #define SGMII_PHY_ADDR7 0x6
565 #define SGMII_PHY_ADDR8 0x7
566 #define FM1_10GEC1_PHY_ADDR 0x10
567 #define FM1_10GEC2_PHY_ADDR 0x11
568 #define FM2_10GEC1_PHY_ADDR 0x12
569 #define FM2_10GEC2_PHY_ADDR 0x13
570 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
571 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
572 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
573 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
577 #ifdef CONFIG_FSL_SATA_V2
578 #define CONFIG_SYS_SATA_MAX_DEVICE 2
580 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
581 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
583 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
584 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
589 #ifdef CONFIG_FMAN_ENET
590 #define CONFIG_ETHPRIME "FM1@DTSEC1"
596 #define CONFIG_USB_EHCI_FSL
597 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
598 #define CONFIG_HAS_FSL_DR_USB
601 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
602 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
603 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
607 #define __USB_PHY_TYPE utmi
610 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
611 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
612 * interleaving. It can be cacheline, page, bank, superbank.
613 * See doc/README.fsl-ddr for details.
615 #ifdef CONFIG_ARCH_T4240
616 #define CTRL_INTLV_PREFERED 3way_4KB
618 #define CTRL_INTLV_PREFERED cacheline
621 #define CONFIG_EXTRA_ENV_SETTINGS \
622 "hwconfig=fsl_ddr:" \
623 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
625 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
627 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
628 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
629 "tftpflash=tftpboot $loadaddr $uboot && " \
630 "protect off $ubootaddr +$filesize && " \
631 "erase $ubootaddr +$filesize && " \
632 "cp.b $loadaddr $ubootaddr $filesize && " \
633 "protect on $ubootaddr +$filesize && " \
634 "cmp.b $loadaddr $ubootaddr $filesize\0" \
635 "consoledev=ttyS0\0" \
636 "ramdiskaddr=2000000\0" \
637 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
638 "fdtaddr=1e00000\0" \
639 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
642 #define CONFIG_HVBOOT \
643 "setenv bootargs config-addr=0x60000000; " \
644 "bootm 0x01000000 - 0x00f00000"
646 #define CONFIG_LINUX \
647 "setenv bootargs root=/dev/ram rw " \
648 "console=$consoledev,$baudrate $othbootargs;" \
649 "setenv ramdiskaddr 0x02000000;" \
650 "setenv fdtaddr 0x00c00000;" \
651 "setenv loadaddr 0x1000000;" \
652 "bootm $loadaddr $ramdiskaddr $fdtaddr"
654 #define CONFIG_HDBOOT \
655 "setenv bootargs root=/dev/$bdev rw " \
656 "console=$consoledev,$baudrate $othbootargs;" \
657 "tftp $loadaddr $bootfile;" \
658 "tftp $fdtaddr $fdtfile;" \
659 "bootm $loadaddr - $fdtaddr"
661 #define CONFIG_NFSBOOTCOMMAND \
662 "setenv bootargs root=/dev/nfs rw " \
663 "nfsroot=$serverip:$rootpath " \
664 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
665 "console=$consoledev,$baudrate $othbootargs;" \
666 "tftp $loadaddr $bootfile;" \
667 "tftp $fdtaddr $fdtfile;" \
668 "bootm $loadaddr - $fdtaddr"
670 #define CONFIG_RAMBOOTCOMMAND \
671 "setenv bootargs root=/dev/ram rw " \
672 "console=$consoledev,$baudrate $othbootargs;" \
673 "tftp $ramdiskaddr $ramdiskfile;" \
674 "tftp $loadaddr $bootfile;" \
675 "tftp $fdtaddr $fdtfile;" \
676 "bootm $loadaddr $ramdiskaddr $fdtaddr"
678 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
680 #include <asm/fsl_secure_boot.h>
682 #endif /* __CONFIG_H */