include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #define CONFIG_PCIE4
  16
  17 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  18
  19 #ifdef CONFIG_RAMBOOT_PBL
  20 #ifndef CONFIG_SDCARD
  21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23 #else
  24 #define RESET_VECTOR_OFFSET             0x27FFC
  25 #define BOOT_PAGE_OFFSET                0x27000
  26
  27 #ifdef  CONFIG_SDCARD
  28 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  29 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  30 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  31 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  32 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  33 #ifndef CONFIG_SPL_BUILD
  34 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  35 #endif
  36 #endif
  37
  38 #endif
  39 #endif /* CONFIG_RAMBOOT_PBL */
  40
  41 /* High Level Configuration Options */
  42 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  43
  44 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  45 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  46 #endif
  47
  48 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  49 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  50 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  51 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  52 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  53
  54 /*
  55  * These can be toggled for performance analysis, otherwise use default.
  56  */
  57 #define CONFIG_SYS_CACHE_STASHING
  58 #ifdef CONFIG_DDR_ECC
  59 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  60 #endif
  61
  62 #define CONFIG_ENABLE_36BIT_PHYS
  63
  64 /*
  65  *  Config the L3 Cache as L3 SRAM
  66  */
  67 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  68 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  69 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  70
  71 #define CONFIG_SYS_DCSRBAR              0xf0000000
  72 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  73
  74 /*
  75  * DDR Setup
  76  */
  77 #define CONFIG_VERY_BIG_RAM
  78 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  79 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  80
  81 /*
  82  * IFC Definitions
  83  */
  84 #define CONFIG_SYS_FLASH_BASE   0xe0000000
  85 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  86
  87 #define CONFIG_HWCONFIG
  88
  89 /* define to use L1 as initial stack */
  90 #define CONFIG_L1_INIT_RAM
  91 #define CONFIG_SYS_INIT_RAM_LOCK
  92 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
  93 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
  94 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
  95 /* The assembler doesn't like typecast */
  96 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  97         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  98           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  99 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 100
 101 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 102
 103 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 104
 105 /* Serial Port - controlled on board with jumper J8
 106  * open - index 2
 107  * shorted - index 1
 108  */
 109 #define CONFIG_SYS_NS16550_SERIAL
 110 #define CONFIG_SYS_NS16550_REG_SIZE     1
 111 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 112
 113 #define CONFIG_SYS_BAUDRATE_TABLE       \
 114         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 115
 116 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 117 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 118 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 119 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 120
 121 /* I2C */
 122
 123 /*
 124  * General PCI
 125  * Memory space is mapped 1-1, but I/O space must start from 0.
 126  */
 127
 128 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 129 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 130 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 131 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 132 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 133
 134 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 135 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 136 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 137 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 138 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 139
 140 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 141 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 142 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 143 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 144 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 145
 146 /* controller 4, Base address 203000 */
 147 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 148 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 149 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 150
 151 #ifdef CONFIG_PCI
 152 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 153 #endif  /* CONFIG_PCI */
 154
 155 /*
 156  * Environment
 157  */
 158 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 159 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 160
 161 /*
 162  * Miscellaneous configurable options
 163  */
 164
 165 /*
 166  * For booting Linux, the board info and command line data
 167  * have to be in the first 64 MB of memory, since this is
 168  * the maximum mapped by the Linux kernel during initialization.
 169  */
 170 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 171 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 172
 173 /*
 174  * Environment Configuration
 175  */
 176 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 177 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 178
 179 #define HVBOOT                                  \
 180         "setenv bootargs config-addr=0x60000000; "      \
 181         "bootm 0x01000000 - 0x00f00000"
 182
 183 /*
 184  * DDR Setup
 185  */
 186 #define CONFIG_SYS_SPD_BUS_NUM  0
 187 #define SPD_EEPROM_ADDRESS1     0x52
 188 #define SPD_EEPROM_ADDRESS2     0x54
 189 #define SPD_EEPROM_ADDRESS3     0x56
 190 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 191 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 192
 193 /*
 194  * IFC Definitions
 195  */
 196 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 197 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 198                                 + 0x8000000) | \
 199                                 CSPR_PORT_SIZE_16 | \
 200                                 CSPR_MSEL_NOR | \
 201                                 CSPR_V)
 202 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 203 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 204                                 CSPR_PORT_SIZE_16 | \
 205                                 CSPR_MSEL_NOR | \
 206                                 CSPR_V)
 207 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 208 /* NOR Flash Timing Params */
 209 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 210
 211 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 212                                 FTIM0_NOR_TEADC(0x5) | \
 213                                 FTIM0_NOR_TEAHC(0x5))
 214 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 215                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 216                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 217 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 218                                 FTIM2_NOR_TCH(0x4) | \
 219                                 FTIM2_NOR_TWPH(0x0E) | \
 220                                 FTIM2_NOR_TWP(0x1c))
 221 #define CONFIG_SYS_NOR_FTIM3    0x0
 222
 223 #define CONFIG_SYS_FLASH_QUIET_TEST
 224 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 225
 226 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 227 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 228 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 229
 230 #define CONFIG_SYS_FLASH_EMPTY_INFO
 231 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 232                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 233
 234 /* NAND Flash on IFC */
 235 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 236 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 237 #define CONFIG_SYS_NAND_BASE            0xff800000
 238 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 239
 240 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 241 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 242                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 243                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 244                                 | CSPR_V)
 245 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 246
 247 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 248                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 249                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 250                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 251                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 252                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 253                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 254
 255 /* ONFI NAND Flash mode0 Timing Params */
 256 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 257                                         FTIM0_NAND_TWP(0x18)   | \
 258                                         FTIM0_NAND_TWCHT(0x07) | \
 259                                         FTIM0_NAND_TWH(0x0a))
 260 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 261                                         FTIM1_NAND_TWBE(0x39)  | \
 262                                         FTIM1_NAND_TRR(0x0e)   | \
 263                                         FTIM1_NAND_TRP(0x18))
 264 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 265                                         FTIM2_NAND_TREH(0x0a) | \
 266                                         FTIM2_NAND_TWHRE(0x1e))
 267 #define CONFIG_SYS_NAND_FTIM3           0x0
 268
 269 #define CONFIG_SYS_NAND_DDR_LAW         11
 270 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 271 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 272
 273 #if defined(CONFIG_MTD_RAW_NAND)
 274 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 275 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 276 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 277 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 278 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 279 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 280 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 281 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 282 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 283 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 284 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 285 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 286 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 287 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 288 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 289 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 290 #else
 291 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 292 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 293 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 294 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 295 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 296 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 297 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 298 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 299 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 300 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 301 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 302 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 303 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 304 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 305 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 306 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 307 #endif
 308 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 309 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 310 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 311 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 312 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 313 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 314 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 315 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 316
 317 /* CPLD on IFC */
 318 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 319 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 320 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 321 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 322                                 | CSPR_PORT_SIZE_8 \
 323                                 | CSPR_MSEL_GPCM \
 324                                 | CSPR_V)
 325
 326 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 327 #define CONFIG_SYS_CSOR3        0x0
 328
 329 /* CPLD Timing parameters for IFC CS3 */
 330 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 331                                         FTIM0_GPCM_TEADC(0x0e) | \
 332                                         FTIM0_GPCM_TEAHC(0x0e))
 333 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 334                                         FTIM1_GPCM_TRAD(0x1f))
 335 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 336                                         FTIM2_GPCM_TCH(0x8) | \
 337                                         FTIM2_GPCM_TWP(0x1f))
 338 #define CONFIG_SYS_CS3_FTIM3            0x0
 339
 340 #if defined(CONFIG_RAMBOOT_PBL)
 341 #define CONFIG_SYS_RAMBOOT
 342 #endif
 343
 344 /* I2C */
 345 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 346 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 347
 348 #define I2C_MUX_CH_DEFAULT      0x8
 349 #define I2C_MUX_CH_VOL_MONITOR  0xa
 350 #define I2C_MUX_CH_VSC3316_FS   0xc
 351 #define I2C_MUX_CH_VSC3316_BS   0xd
 352
 353 /* Voltage monitor on channel 2*/
 354 #define I2C_VOL_MONITOR_ADDR            0x40
 355 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 356 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 357 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 358
 359 /* The lowest and highest voltage allowed for T4240RDB */
 360 #define VDD_MV_MIN                      819
 361 #define VDD_MV_MAX                      1212
 362
 363 /*
 364  * eSPI - Enhanced SPI
 365  */
 366
 367 /* Qman/Bman */
 368 #ifndef CONFIG_NOBQFMAN
 369 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 370 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 371 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 372 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 373 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 374 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 375 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 376 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 377 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 378                                         CONFIG_SYS_BMAN_CENA_SIZE)
 379 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 380 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 381 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 382 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 383 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 384 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 385 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 386 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 387 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 388 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 389 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 390                                         CONFIG_SYS_QMAN_CENA_SIZE)
 391 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 392 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 393
 394 #define CONFIG_SYS_DPAA_FMAN
 395 #define CONFIG_SYS_DPAA_PME
 396 #define CONFIG_SYS_PMAN
 397 #define CONFIG_SYS_DPAA_DCE
 398 #define CONFIG_SYS_DPAA_RMAN
 399 #define CONFIG_SYS_INTERLAKEN
 400
 401 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 402 #endif /* CONFIG_NOBQFMAN */
 403
 404 #ifdef CONFIG_SYS_DPAA_FMAN
 405 #define SGMII_PHY_ADDR1 0x0
 406 #define SGMII_PHY_ADDR2 0x1
 407 #define SGMII_PHY_ADDR3 0x2
 408 #define SGMII_PHY_ADDR4 0x3
 409 #define SGMII_PHY_ADDR5 0x4
 410 #define SGMII_PHY_ADDR6 0x5
 411 #define SGMII_PHY_ADDR7 0x6
 412 #define SGMII_PHY_ADDR8 0x7
 413 #define FM1_10GEC1_PHY_ADDR     0x10
 414 #define FM1_10GEC2_PHY_ADDR     0x11
 415 #define FM2_10GEC1_PHY_ADDR     0x12
 416 #define FM2_10GEC2_PHY_ADDR     0x13
 417 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 418 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 419 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 420 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 421 #endif
 422
 423 /*
 424 * USB
 425 */
 426
 427 #ifdef CONFIG_MMC
 428 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 429 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 430 #endif
 431
 432
 433 #define __USB_PHY_TYPE  utmi
 434
 435 /*
 436  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 437  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 438  * interleaving. It can be cacheline, page, bank, superbank.
 439  * See doc/README.fsl-ddr for details.
 440  */
 441 #ifdef CONFIG_ARCH_T4240
 442 #define CTRL_INTLV_PREFERED 3way_4KB
 443 #else
 444 #define CTRL_INTLV_PREFERED cacheline
 445 #endif
 446
 447 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 448         "hwconfig=fsl_ddr:"                                     \
 449         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 450         "bank_intlv=auto;"                                      \
 451         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 452         "netdev=eth0\0"                                         \
 453         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 454         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 455         "tftpflash=tftpboot $loadaddr $uboot && "               \
 456         "protect off $ubootaddr +$filesize && "                 \
 457         "erase $ubootaddr +$filesize && "                       \
 458         "cp.b $loadaddr $ubootaddr $filesize && "               \
 459         "protect on $ubootaddr +$filesize && "                  \
 460         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 461         "consoledev=ttyS0\0"                                    \
 462         "ramdiskaddr=2000000\0"                                 \
 463         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 464         "fdtaddr=1e00000\0"                                     \
 465         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 466         "bdev=sda3\0"
 467
 468 #define HVBOOT                                  \
 469         "setenv bootargs config-addr=0x60000000; "      \
 470         "bootm 0x01000000 - 0x00f00000"
 471
 472 #include <asm/fsl_secure_boot.h>
 473
 474 #endif  /* __CONFIG_H */