include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T4240 RDB board configuration file
   8  */
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_FSL_SATA_V2
  13 #define CONFIG_PCIE4
  14
  15 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  19 #ifndef CONFIG_SDCARD
  20 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  21 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  22 #else
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_PAD_TO               0x40000
  25 #define CONFIG_SPL_MAX_SIZE             0x28000
  26 #define RESET_VECTOR_OFFSET             0x27FFC
  27 #define BOOT_PAGE_OFFSET                0x27000
  28
  29 #ifdef  CONFIG_SDCARD
  30 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  31 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  32 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  33 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  34 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  35 #ifndef CONFIG_SPL_BUILD
  36 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  37 #endif
  38 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  39 #endif
  40
  41 #ifdef CONFIG_SPL_BUILD
  42 #define CONFIG_SPL_SKIP_RELOCATE
  43 #define CONFIG_SPL_COMMON_INIT_DDR
  44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  45 #endif
  46
  47 #endif
  48 #endif /* CONFIG_RAMBOOT_PBL */
  49
  50 #define CONFIG_DDR_ECC
  51
  52 /* High Level Configuration Options */
  53 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  54
  55 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  56 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  57 #endif
  58
  59 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  60 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  61 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  62 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  63 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  64 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  65
  66 #define CONFIG_ENV_OVERWRITE
  67
  68 /*
  69  * These can be toggled for performance analysis, otherwise use default.
  70  */
  71 #define CONFIG_SYS_CACHE_STASHING
  72 #define CONFIG_BTB                      /* toggle branch predition */
  73 #ifdef CONFIG_DDR_ECC
  74 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  75 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  76 #endif
  77
  78 #define CONFIG_ENABLE_36BIT_PHYS
  79
  80 #define CONFIG_ADDR_MAP
  81 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  82
  83 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  84 #define CONFIG_SYS_MEMTEST_END          0x00400000
  85
  86 /*
  87  *  Config the L3 Cache as L3 SRAM
  88  */
  89 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  90 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  91 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  92 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  93 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
  94 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
  95 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
  96
  97 #define CONFIG_SYS_DCSRBAR              0xf0000000
  98 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  99
 100 /*
 101  * DDR Setup
 102  */
 103 #define CONFIG_VERY_BIG_RAM
 104 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 105 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 106
 107 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 108 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 109
 110 #define CONFIG_DDR_SPD
 111
 112 /*
 113  * IFC Definitions
 114  */
 115 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 116 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 117
 118 #ifdef CONFIG_SPL_BUILD
 119 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 120 #else
 121 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 122 #endif
 123
 124 #define CONFIG_HWCONFIG
 125
 126 /* define to use L1 as initial stack */
 127 #define CONFIG_L1_INIT_RAM
 128 #define CONFIG_SYS_INIT_RAM_LOCK
 129 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 130 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 131 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 132 /* The assembler doesn't like typecast */
 133 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 134         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 135           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 136 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 137
 138 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 139                                         GENERATED_GBL_DATA_SIZE)
 140 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 141
 142 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 143 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 144
 145 /* Serial Port - controlled on board with jumper J8
 146  * open - index 2
 147  * shorted - index 1
 148  */
 149 #define CONFIG_SYS_NS16550_SERIAL
 150 #define CONFIG_SYS_NS16550_REG_SIZE     1
 151 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 152
 153 #define CONFIG_SYS_BAUDRATE_TABLE       \
 154         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 155
 156 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 157 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 158 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 159 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 160
 161 /* I2C */
 162 #define CONFIG_SYS_I2C
 163 #define CONFIG_SYS_I2C_FSL
 164 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 165 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 166 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 167 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 168
 169 /*
 170  * General PCI
 171  * Memory space is mapped 1-1, but I/O space must start from 0.
 172  */
 173
 174 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 175 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 176 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 177 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 178 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 179
 180 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 181 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 182 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 183 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 184 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 185
 186 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 187 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 188 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 189 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 190 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 191
 192 /* controller 4, Base address 203000 */
 193 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 194 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 195 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 196
 197 #ifdef CONFIG_PCI
 198 #if !defined(CONFIG_DM_PCI)
 199 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 200 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 201 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 202 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 203 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 204 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 205 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 206 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 207 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 208 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 209 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 210 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 211 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 212 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 213 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 214 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 215 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 216 #define CONFIG_PCI_INDIRECT_BRIDGE
 217 #endif
 218
 219 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 220 #endif  /* CONFIG_PCI */
 221
 222 /* SATA */
 223 #ifdef CONFIG_FSL_SATA_V2
 224 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 225 #define CONFIG_SATA1
 226 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 227 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 228 #define CONFIG_SATA2
 229 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 230 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 231
 232 #define CONFIG_LBA48
 233 #endif
 234
 235 #ifdef CONFIG_FMAN_ENET
 236 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 237 #endif
 238
 239 /*
 240  * Environment
 241  */
 242 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 243 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 244
 245 /*
 246  * Command line configuration.
 247  */
 248
 249 /*
 250  * Miscellaneous configurable options
 251  */
 252 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 253
 254 /*
 255  * For booting Linux, the board info and command line data
 256  * have to be in the first 64 MB of memory, since this is
 257  * the maximum mapped by the Linux kernel during initialization.
 258  */
 259 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 260 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 261
 262 #ifdef CONFIG_CMD_KGDB
 263 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 264 #endif
 265
 266 /*
 267  * Environment Configuration
 268  */
 269 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 270 #define CONFIG_BOOTFILE         "uImage"
 271 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 272
 273 /* default location for tftp and bootm */
 274 #define CONFIG_LOADADDR         1000000
 275
 276 #define CONFIG_HVBOOT                                   \
 277         "setenv bootargs config-addr=0x60000000; "      \
 278         "bootm 0x01000000 - 0x00f00000"
 279
 280 #if defined(CONFIG_SPIFLASH)
 281 #elif defined(CONFIG_SDCARD)
 282 #define CONFIG_SYS_MMC_ENV_DEV          0
 283 #endif
 284
 285 #define CONFIG_SYS_CLK_FREQ     66666666
 286 #define CONFIG_DDR_CLK_FREQ     133333333
 287
 288 #ifndef __ASSEMBLY__
 289 unsigned long get_board_sys_clk(void);
 290 unsigned long get_board_ddr_clk(void);
 291 #endif
 292
 293 /*
 294  * DDR Setup
 295  */
 296 #define CONFIG_SYS_SPD_BUS_NUM  0
 297 #define SPD_EEPROM_ADDRESS1     0x52
 298 #define SPD_EEPROM_ADDRESS2     0x54
 299 #define SPD_EEPROM_ADDRESS3     0x56
 300 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 301 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 302
 303 /*
 304  * IFC Definitions
 305  */
 306 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 307 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 308                                 + 0x8000000) | \
 309                                 CSPR_PORT_SIZE_16 | \
 310                                 CSPR_MSEL_NOR | \
 311                                 CSPR_V)
 312 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 313 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 314                                 CSPR_PORT_SIZE_16 | \
 315                                 CSPR_MSEL_NOR | \
 316                                 CSPR_V)
 317 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 318 /* NOR Flash Timing Params */
 319 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 320
 321 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 322                                 FTIM0_NOR_TEADC(0x5) | \
 323                                 FTIM0_NOR_TEAHC(0x5))
 324 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 325                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 326                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 327 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 328                                 FTIM2_NOR_TCH(0x4) | \
 329                                 FTIM2_NOR_TWPH(0x0E) | \
 330                                 FTIM2_NOR_TWP(0x1c))
 331 #define CONFIG_SYS_NOR_FTIM3    0x0
 332
 333 #define CONFIG_SYS_FLASH_QUIET_TEST
 334 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 335
 336 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 337 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 338 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 339 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 340
 341 #define CONFIG_SYS_FLASH_EMPTY_INFO
 342 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 343                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 344
 345 /* NAND Flash on IFC */
 346 #define CONFIG_NAND_FSL_IFC
 347 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 348 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 349 #define CONFIG_SYS_NAND_BASE            0xff800000
 350 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 351
 352 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 353 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 354                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 355                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 356                                 | CSPR_V)
 357 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 358
 359 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 360                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 361                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 362                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 363                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 364                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 365                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 366
 367 #define CONFIG_SYS_NAND_ONFI_DETECTION
 368
 369 /* ONFI NAND Flash mode0 Timing Params */
 370 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 371                                         FTIM0_NAND_TWP(0x18)   | \
 372                                         FTIM0_NAND_TWCHT(0x07) | \
 373                                         FTIM0_NAND_TWH(0x0a))
 374 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 375                                         FTIM1_NAND_TWBE(0x39)  | \
 376                                         FTIM1_NAND_TRR(0x0e)   | \
 377                                         FTIM1_NAND_TRP(0x18))
 378 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 379                                         FTIM2_NAND_TREH(0x0a) | \
 380                                         FTIM2_NAND_TWHRE(0x1e))
 381 #define CONFIG_SYS_NAND_FTIM3           0x0
 382
 383 #define CONFIG_SYS_NAND_DDR_LAW         11
 384 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 385 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 386
 387 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 388
 389 #if defined(CONFIG_NAND)
 390 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 391 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 392 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 393 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 394 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 395 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 396 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 397 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 398 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 399 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 400 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 401 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 402 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 403 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 404 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 405 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 406 #else
 407 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 408 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 409 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 410 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 411 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 412 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 413 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 414 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 415 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 416 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 417 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 418 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 419 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 420 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 421 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 422 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 423 #endif
 424 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 425 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 426 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 427 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 428 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 429 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 430 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 431 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 432
 433 /* CPLD on IFC */
 434 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 435 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 436 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 437 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 438                                 | CSPR_PORT_SIZE_8 \
 439                                 | CSPR_MSEL_GPCM \
 440                                 | CSPR_V)
 441
 442 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 443 #define CONFIG_SYS_CSOR3        0x0
 444
 445 /* CPLD Timing parameters for IFC CS3 */
 446 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 447                                         FTIM0_GPCM_TEADC(0x0e) | \
 448                                         FTIM0_GPCM_TEAHC(0x0e))
 449 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 450                                         FTIM1_GPCM_TRAD(0x1f))
 451 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 452                                         FTIM2_GPCM_TCH(0x8) | \
 453                                         FTIM2_GPCM_TWP(0x1f))
 454 #define CONFIG_SYS_CS3_FTIM3            0x0
 455
 456 #if defined(CONFIG_RAMBOOT_PBL)
 457 #define CONFIG_SYS_RAMBOOT
 458 #endif
 459
 460 /* I2C */
 461 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 462 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 463 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 464 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 465
 466 #define I2C_MUX_CH_DEFAULT      0x8
 467 #define I2C_MUX_CH_VOL_MONITOR  0xa
 468 #define I2C_MUX_CH_VSC3316_FS   0xc
 469 #define I2C_MUX_CH_VSC3316_BS   0xd
 470
 471 /* Voltage monitor on channel 2*/
 472 #define I2C_VOL_MONITOR_ADDR            0x40
 473 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 474 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 475 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 476
 477 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
 478 #ifndef CONFIG_SPL_BUILD
 479 #define CONFIG_VID
 480 #endif
 481 #define CONFIG_VOL_MONITOR_IR36021_SET
 482 #define CONFIG_VOL_MONITOR_IR36021_READ
 483 /* The lowest and highest voltage allowed for T4240RDB */
 484 #define VDD_MV_MIN                      819
 485 #define VDD_MV_MAX                      1212
 486
 487 /*
 488  * eSPI - Enhanced SPI
 489  */
 490
 491 /* Qman/Bman */
 492 #ifndef CONFIG_NOBQFMAN
 493 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 494 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 495 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 496 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 497 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 498 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 499 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 500 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 501 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 502                                         CONFIG_SYS_BMAN_CENA_SIZE)
 503 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 504 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 505 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 506 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 507 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 508 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 509 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 510 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 511 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 512 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 513 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 514                                         CONFIG_SYS_QMAN_CENA_SIZE)
 515 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 516 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 517
 518 #define CONFIG_SYS_DPAA_FMAN
 519 #define CONFIG_SYS_DPAA_PME
 520 #define CONFIG_SYS_PMAN
 521 #define CONFIG_SYS_DPAA_DCE
 522 #define CONFIG_SYS_DPAA_RMAN
 523 #define CONFIG_SYS_INTERLAKEN
 524
 525 /* Default address of microcode for the Linux Fman driver */
 526 #if defined(CONFIG_SPIFLASH)
 527 /*
 528  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 529  * env, so we got 0x110000.
 530  */
 531 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 532 #elif defined(CONFIG_SDCARD)
 533 /*
 534  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 535  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 536  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 537  */
 538 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 539 #elif defined(CONFIG_NAND)
 540 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 541 #else
 542 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 543 #endif
 544 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 545 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 546 #endif /* CONFIG_NOBQFMAN */
 547
 548 #ifdef CONFIG_SYS_DPAA_FMAN
 549 #define CONFIG_PHYLIB_10G
 550 #define CONFIG_PHY_VITESSE
 551 #define CONFIG_CORTINA_FW_ADDR          0xefe00000
 552 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 553 #define CONFIG_PHY_TERANETICS
 554 #define SGMII_PHY_ADDR1 0x0
 555 #define SGMII_PHY_ADDR2 0x1
 556 #define SGMII_PHY_ADDR3 0x2
 557 #define SGMII_PHY_ADDR4 0x3
 558 #define SGMII_PHY_ADDR5 0x4
 559 #define SGMII_PHY_ADDR6 0x5
 560 #define SGMII_PHY_ADDR7 0x6
 561 #define SGMII_PHY_ADDR8 0x7
 562 #define FM1_10GEC1_PHY_ADDR     0x10
 563 #define FM1_10GEC2_PHY_ADDR     0x11
 564 #define FM2_10GEC1_PHY_ADDR     0x12
 565 #define FM2_10GEC2_PHY_ADDR     0x13
 566 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 567 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 568 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 569 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 570 #endif
 571
 572 /* SATA */
 573 #ifdef CONFIG_FSL_SATA_V2
 574 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 575 #define CONFIG_SATA1
 576 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 577 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 578 #define CONFIG_SATA2
 579 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 580 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 581
 582 #define CONFIG_LBA48
 583 #endif
 584
 585 #ifdef CONFIG_FMAN_ENET
 586 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 587 #endif
 588
 589 /*
 590 * USB
 591 */
 592 #define CONFIG_USB_EHCI_FSL
 593 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 594 #define CONFIG_HAS_FSL_DR_USB
 595
 596 #ifdef CONFIG_MMC
 597 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 598 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 599 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 600 #endif
 601
 602
 603 #define __USB_PHY_TYPE  utmi
 604
 605 /*
 606  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 607  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 608  * interleaving. It can be cacheline, page, bank, superbank.
 609  * See doc/README.fsl-ddr for details.
 610  */
 611 #ifdef CONFIG_ARCH_T4240
 612 #define CTRL_INTLV_PREFERED 3way_4KB
 613 #else
 614 #define CTRL_INTLV_PREFERED cacheline
 615 #endif
 616
 617 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 618         "hwconfig=fsl_ddr:"                                     \
 619         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 620         "bank_intlv=auto;"                                      \
 621         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 622         "netdev=eth0\0"                                         \
 623         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 624         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 625         "tftpflash=tftpboot $loadaddr $uboot && "               \
 626         "protect off $ubootaddr +$filesize && "                 \
 627         "erase $ubootaddr +$filesize && "                       \
 628         "cp.b $loadaddr $ubootaddr $filesize && "               \
 629         "protect on $ubootaddr +$filesize && "                  \
 630         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 631         "consoledev=ttyS0\0"                                    \
 632         "ramdiskaddr=2000000\0"                                 \
 633         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 634         "fdtaddr=1e00000\0"                                     \
 635         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 636         "bdev=sda3\0"
 637
 638 #define CONFIG_HVBOOT                                   \
 639         "setenv bootargs config-addr=0x60000000; "      \
 640         "bootm 0x01000000 - 0x00f00000"
 641
 642 #define CONFIG_LINUX                                    \
 643         "setenv bootargs root=/dev/ram rw "             \
 644         "console=$consoledev,$baudrate $othbootargs;"   \
 645         "setenv ramdiskaddr 0x02000000;"                \
 646         "setenv fdtaddr 0x00c00000;"                    \
 647         "setenv loadaddr 0x1000000;"                    \
 648         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 649
 650 #define CONFIG_HDBOOT                                   \
 651         "setenv bootargs root=/dev/$bdev rw "           \
 652         "console=$consoledev,$baudrate $othbootargs;"   \
 653         "tftp $loadaddr $bootfile;"                     \
 654         "tftp $fdtaddr $fdtfile;"                       \
 655         "bootm $loadaddr - $fdtaddr"
 656
 657 #define CONFIG_NFSBOOTCOMMAND                   \
 658         "setenv bootargs root=/dev/nfs rw "     \
 659         "nfsroot=$serverip:$rootpath "          \
 660         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 661         "console=$consoledev,$baudrate $othbootargs;"   \
 662         "tftp $loadaddr $bootfile;"             \
 663         "tftp $fdtaddr $fdtfile;"               \
 664         "bootm $loadaddr - $fdtaddr"
 665
 666 #define CONFIG_RAMBOOTCOMMAND                           \
 667         "setenv bootargs root=/dev/ram rw "             \
 668         "console=$consoledev,$baudrate $othbootargs;"   \
 669         "tftp $ramdiskaddr $ramdiskfile;"               \
 670         "tftp $loadaddr $bootfile;"                     \
 671         "tftp $fdtaddr $fdtfile;"                       \
 672         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 673
 674 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 675
 676 #include <asm/fsl_secure_boot.h>
 677
 678 #endif  /* __CONFIG_H */