include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #define CONFIG_PCIE4
  16
  17 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  18
  19 #ifdef CONFIG_RAMBOOT_PBL
  20 #ifndef CONFIG_SDCARD
  21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23 #else
  24 #define RESET_VECTOR_OFFSET             0x27FFC
  25 #define BOOT_PAGE_OFFSET                0x27000
  26
  27 #ifdef  CONFIG_SDCARD
  28 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  29 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  30 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  31 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  32 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  33 #ifndef CONFIG_SPL_BUILD
  34 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  35 #endif
  36 #endif
  37
  38 #endif
  39 #endif /* CONFIG_RAMBOOT_PBL */
  40
  41 /* High Level Configuration Options */
  42 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  43
  44 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  45 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  46 #endif
  47
  48 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  49 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  50 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  51 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  52 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  53
  54 /*
  55  * These can be toggled for performance analysis, otherwise use default.
  56  */
  57 #define CONFIG_SYS_CACHE_STASHING
  58 #ifdef CONFIG_DDR_ECC
  59 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  60 #endif
  61
  62 #define CONFIG_ENABLE_36BIT_PHYS
  63
  64 /*
  65  *  Config the L3 Cache as L3 SRAM
  66  */
  67 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  68 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  69 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  70
  71 #define CONFIG_SYS_DCSRBAR              0xf0000000
  72 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  73
  74 /*
  75  * DDR Setup
  76  */
  77 #define CONFIG_VERY_BIG_RAM
  78 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  79 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  80
  81 /*
  82  * IFC Definitions
  83  */
  84 #define CONFIG_SYS_FLASH_BASE   0xe0000000
  85 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  86
  87 #define CONFIG_HWCONFIG
  88
  89 /* define to use L1 as initial stack */
  90 #define CONFIG_L1_INIT_RAM
  91 #define CONFIG_SYS_INIT_RAM_LOCK
  92 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
  93 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
  94 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
  95 /* The assembler doesn't like typecast */
  96 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  97         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  98           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  99 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 100
 101 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 102
 103 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 104
 105 /* Serial Port - controlled on board with jumper J8
 106  * open - index 2
 107  * shorted - index 1
 108  */
 109 #define CONFIG_SYS_NS16550_SERIAL
 110 #define CONFIG_SYS_NS16550_REG_SIZE     1
 111 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 112
 113 #define CONFIG_SYS_BAUDRATE_TABLE       \
 114         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 115
 116 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 117 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 118 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 119 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 120
 121 /* I2C */
 122
 123 /*
 124  * General PCI
 125  * Memory space is mapped 1-1, but I/O space must start from 0.
 126  */
 127
 128 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 129 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 130 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 131 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 132 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 133
 134 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 135 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 136 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 137 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 138 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 139
 140 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 141 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 142 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 143 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 144 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 145
 146 /* controller 4, Base address 203000 */
 147 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 148 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 149 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 150
 151 #ifdef CONFIG_PCI
 152 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 153 #endif  /* CONFIG_PCI */
 154
 155 /* SATA */
 156 #ifdef CONFIG_FSL_SATA_V2
 157 #define CONFIG_LBA48
 158 #endif
 159
 160 /*
 161  * Environment
 162  */
 163 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 164 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 165
 166 /*
 167  * Miscellaneous configurable options
 168  */
 169
 170 /*
 171  * For booting Linux, the board info and command line data
 172  * have to be in the first 64 MB of memory, since this is
 173  * the maximum mapped by the Linux kernel during initialization.
 174  */
 175 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 176 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 177
 178 /*
 179  * Environment Configuration
 180  */
 181 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 182 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 183
 184 #define HVBOOT                                  \
 185         "setenv bootargs config-addr=0x60000000; "      \
 186         "bootm 0x01000000 - 0x00f00000"
 187
 188 /*
 189  * DDR Setup
 190  */
 191 #define CONFIG_SYS_SPD_BUS_NUM  0
 192 #define SPD_EEPROM_ADDRESS1     0x52
 193 #define SPD_EEPROM_ADDRESS2     0x54
 194 #define SPD_EEPROM_ADDRESS3     0x56
 195 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 196 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 197
 198 /*
 199  * IFC Definitions
 200  */
 201 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 202 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 203                                 + 0x8000000) | \
 204                                 CSPR_PORT_SIZE_16 | \
 205                                 CSPR_MSEL_NOR | \
 206                                 CSPR_V)
 207 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 208 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 209                                 CSPR_PORT_SIZE_16 | \
 210                                 CSPR_MSEL_NOR | \
 211                                 CSPR_V)
 212 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 213 /* NOR Flash Timing Params */
 214 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 215
 216 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 217                                 FTIM0_NOR_TEADC(0x5) | \
 218                                 FTIM0_NOR_TEAHC(0x5))
 219 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 220                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 221                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 222 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 223                                 FTIM2_NOR_TCH(0x4) | \
 224                                 FTIM2_NOR_TWPH(0x0E) | \
 225                                 FTIM2_NOR_TWP(0x1c))
 226 #define CONFIG_SYS_NOR_FTIM3    0x0
 227
 228 #define CONFIG_SYS_FLASH_QUIET_TEST
 229 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 230
 231 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 232 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 233 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 234
 235 #define CONFIG_SYS_FLASH_EMPTY_INFO
 236 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 237                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 238
 239 /* NAND Flash on IFC */
 240 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 241 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 242 #define CONFIG_SYS_NAND_BASE            0xff800000
 243 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 244
 245 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 246 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 247                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 248                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 249                                 | CSPR_V)
 250 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 251
 252 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 253                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 254                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 255                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 256                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 257                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 258                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 259
 260 /* ONFI NAND Flash mode0 Timing Params */
 261 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 262                                         FTIM0_NAND_TWP(0x18)   | \
 263                                         FTIM0_NAND_TWCHT(0x07) | \
 264                                         FTIM0_NAND_TWH(0x0a))
 265 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 266                                         FTIM1_NAND_TWBE(0x39)  | \
 267                                         FTIM1_NAND_TRR(0x0e)   | \
 268                                         FTIM1_NAND_TRP(0x18))
 269 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 270                                         FTIM2_NAND_TREH(0x0a) | \
 271                                         FTIM2_NAND_TWHRE(0x1e))
 272 #define CONFIG_SYS_NAND_FTIM3           0x0
 273
 274 #define CONFIG_SYS_NAND_DDR_LAW         11
 275 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 276 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 277
 278 #if defined(CONFIG_MTD_RAW_NAND)
 279 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 280 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 281 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 282 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 283 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 284 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 285 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 286 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 287 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 288 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 289 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 290 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 291 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 292 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 293 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 294 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 295 #else
 296 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 297 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 298 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 299 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 300 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 301 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 302 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 303 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 304 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 305 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 306 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 307 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 308 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 309 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 310 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 311 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 312 #endif
 313 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 314 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 315 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 316 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 317 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 318 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 319 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 320 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 321
 322 /* CPLD on IFC */
 323 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 324 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 325 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 326 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 327                                 | CSPR_PORT_SIZE_8 \
 328                                 | CSPR_MSEL_GPCM \
 329                                 | CSPR_V)
 330
 331 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 332 #define CONFIG_SYS_CSOR3        0x0
 333
 334 /* CPLD Timing parameters for IFC CS3 */
 335 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 336                                         FTIM0_GPCM_TEADC(0x0e) | \
 337                                         FTIM0_GPCM_TEAHC(0x0e))
 338 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 339                                         FTIM1_GPCM_TRAD(0x1f))
 340 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 341                                         FTIM2_GPCM_TCH(0x8) | \
 342                                         FTIM2_GPCM_TWP(0x1f))
 343 #define CONFIG_SYS_CS3_FTIM3            0x0
 344
 345 #if defined(CONFIG_RAMBOOT_PBL)
 346 #define CONFIG_SYS_RAMBOOT
 347 #endif
 348
 349 /* I2C */
 350 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 351 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 352
 353 #define I2C_MUX_CH_DEFAULT      0x8
 354 #define I2C_MUX_CH_VOL_MONITOR  0xa
 355 #define I2C_MUX_CH_VSC3316_FS   0xc
 356 #define I2C_MUX_CH_VSC3316_BS   0xd
 357
 358 /* Voltage monitor on channel 2*/
 359 #define I2C_VOL_MONITOR_ADDR            0x40
 360 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 361 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 362 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 363
 364 /* The lowest and highest voltage allowed for T4240RDB */
 365 #define VDD_MV_MIN                      819
 366 #define VDD_MV_MAX                      1212
 367
 368 /*
 369  * eSPI - Enhanced SPI
 370  */
 371
 372 /* Qman/Bman */
 373 #ifndef CONFIG_NOBQFMAN
 374 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 375 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 376 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 377 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 378 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 379 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 380 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 381 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 382 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 383                                         CONFIG_SYS_BMAN_CENA_SIZE)
 384 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 385 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 386 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 387 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 388 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 389 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 390 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 391 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 392 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 393 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 394 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 395                                         CONFIG_SYS_QMAN_CENA_SIZE)
 396 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 397 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 398
 399 #define CONFIG_SYS_DPAA_FMAN
 400 #define CONFIG_SYS_DPAA_PME
 401 #define CONFIG_SYS_PMAN
 402 #define CONFIG_SYS_DPAA_DCE
 403 #define CONFIG_SYS_DPAA_RMAN
 404 #define CONFIG_SYS_INTERLAKEN
 405
 406 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 407 #endif /* CONFIG_NOBQFMAN */
 408
 409 #ifdef CONFIG_SYS_DPAA_FMAN
 410 #define SGMII_PHY_ADDR1 0x0
 411 #define SGMII_PHY_ADDR2 0x1
 412 #define SGMII_PHY_ADDR3 0x2
 413 #define SGMII_PHY_ADDR4 0x3
 414 #define SGMII_PHY_ADDR5 0x4
 415 #define SGMII_PHY_ADDR6 0x5
 416 #define SGMII_PHY_ADDR7 0x6
 417 #define SGMII_PHY_ADDR8 0x7
 418 #define FM1_10GEC1_PHY_ADDR     0x10
 419 #define FM1_10GEC2_PHY_ADDR     0x11
 420 #define FM2_10GEC1_PHY_ADDR     0x12
 421 #define FM2_10GEC2_PHY_ADDR     0x13
 422 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 423 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 424 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 425 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 426 #endif
 427
 428 /* SATA */
 429 #ifdef CONFIG_FSL_SATA_V2
 430 #define CONFIG_LBA48
 431 #endif
 432
 433 /*
 434 * USB
 435 */
 436
 437 #ifdef CONFIG_MMC
 438 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 439 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 440 #endif
 441
 442
 443 #define __USB_PHY_TYPE  utmi
 444
 445 /*
 446  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 447  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 448  * interleaving. It can be cacheline, page, bank, superbank.
 449  * See doc/README.fsl-ddr for details.
 450  */
 451 #ifdef CONFIG_ARCH_T4240
 452 #define CTRL_INTLV_PREFERED 3way_4KB
 453 #else
 454 #define CTRL_INTLV_PREFERED cacheline
 455 #endif
 456
 457 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 458         "hwconfig=fsl_ddr:"                                     \
 459         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 460         "bank_intlv=auto;"                                      \
 461         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 462         "netdev=eth0\0"                                         \
 463         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 464         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 465         "tftpflash=tftpboot $loadaddr $uboot && "               \
 466         "protect off $ubootaddr +$filesize && "                 \
 467         "erase $ubootaddr +$filesize && "                       \
 468         "cp.b $loadaddr $ubootaddr $filesize && "               \
 469         "protect on $ubootaddr +$filesize && "                  \
 470         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 471         "consoledev=ttyS0\0"                                    \
 472         "ramdiskaddr=2000000\0"                                 \
 473         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 474         "fdtaddr=1e00000\0"                                     \
 475         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 476         "bdev=sda3\0"
 477
 478 #define HVBOOT                                  \
 479         "setenv bootargs config-addr=0x60000000; "      \
 480         "bootm 0x01000000 - 0x00f00000"
 481
 482 #include <asm/fsl_secure_boot.h>
 483
 484 #endif  /* __CONFIG_H */