1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T4240 RDB board configuration file
13 #include <linux/stringify.h>
15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #ifdef CONFIG_RAMBOOT_PBL
19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
22 #define RESET_VECTOR_OFFSET 0x27FFC
23 #define BOOT_PAGE_OFFSET 0x27000
26 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
27 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
28 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
29 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
30 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
34 #endif /* CONFIG_RAMBOOT_PBL */
36 /* High Level Configuration Options */
38 #ifndef CONFIG_RESET_VECTOR_ADDRESS
39 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
42 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
45 * These can be toggled for performance analysis, otherwise use default.
48 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
52 * Config the L3 Cache as L3 SRAM
54 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
55 #define CONFIG_SYS_L3_SIZE (512 << 10)
56 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
58 #define CONFIG_SYS_DCSRBAR 0xf0000000
59 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
64 #define CONFIG_VERY_BIG_RAM
65 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
66 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
71 #define CONFIG_SYS_FLASH_BASE 0xe0000000
72 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
74 #define CONFIG_HWCONFIG
76 /* define to use L1 as initial stack */
77 #define CONFIG_L1_INIT_RAM
78 #define CONFIG_SYS_INIT_RAM_LOCK
79 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
80 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
81 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
82 /* The assembler doesn't like typecast */
83 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
84 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
85 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
86 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
88 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
90 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
92 /* Serial Port - controlled on board with jumper J8
96 #define CONFIG_SYS_NS16550_SERIAL
97 #define CONFIG_SYS_NS16550_REG_SIZE 1
98 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
100 #define CONFIG_SYS_BAUDRATE_TABLE \
101 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
103 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
104 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
105 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
106 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
112 * Memory space is mapped 1-1, but I/O space must start from 0.
115 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
116 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
117 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
118 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
119 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
121 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
122 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
123 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
124 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
125 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
127 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
128 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
129 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
130 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
131 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
133 /* controller 4, Base address 203000 */
134 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
135 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
136 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
141 #define CONFIG_LOADS_ECHO /* echo on for serial download */
142 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
145 * Miscellaneous configurable options
149 * For booting Linux, the board info and command line data
150 * have to be in the first 64 MB of memory, since this is
151 * the maximum mapped by the Linux kernel during initialization.
153 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
156 * Environment Configuration
158 #define CONFIG_ROOTPATH "/opt/nfsroot"
159 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
162 "setenv bootargs config-addr=0x60000000; " \
163 "bootm 0x01000000 - 0x00f00000"
168 #define SPD_EEPROM_ADDRESS1 0x52
169 #define SPD_EEPROM_ADDRESS2 0x54
170 #define SPD_EEPROM_ADDRESS3 0x56
171 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
172 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
177 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
178 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
180 CSPR_PORT_SIZE_16 | \
183 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
184 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
185 CSPR_PORT_SIZE_16 | \
188 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
189 /* NOR Flash Timing Params */
190 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
192 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
193 FTIM0_NOR_TEADC(0x5) | \
194 FTIM0_NOR_TEAHC(0x5))
195 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
196 FTIM1_NOR_TRAD_NOR(0x1A) |\
197 FTIM1_NOR_TSEQRAD_NOR(0x13))
198 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
199 FTIM2_NOR_TCH(0x4) | \
200 FTIM2_NOR_TWPH(0x0E) | \
202 #define CONFIG_SYS_NOR_FTIM3 0x0
204 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
206 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
207 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
209 /* NAND Flash on IFC */
210 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
211 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
212 #define CONFIG_SYS_NAND_BASE 0xff800000
213 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
215 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
216 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
217 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
218 | CSPR_MSEL_NAND /* MSEL = NAND */ \
220 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
222 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
223 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
224 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
225 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
226 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
227 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
228 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
230 /* ONFI NAND Flash mode0 Timing Params */
231 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
232 FTIM0_NAND_TWP(0x18) | \
233 FTIM0_NAND_TWCHT(0x07) | \
234 FTIM0_NAND_TWH(0x0a))
235 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
236 FTIM1_NAND_TWBE(0x39) | \
237 FTIM1_NAND_TRR(0x0e) | \
238 FTIM1_NAND_TRP(0x18))
239 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
240 FTIM2_NAND_TREH(0x0a) | \
241 FTIM2_NAND_TWHRE(0x1e))
242 #define CONFIG_SYS_NAND_FTIM3 0x0
244 #define CONFIG_SYS_NAND_DDR_LAW 11
245 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
246 #define CONFIG_SYS_MAX_NAND_DEVICE 1
248 #if defined(CONFIG_MTD_RAW_NAND)
249 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
250 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
251 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
252 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
253 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
254 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
255 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
256 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
257 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
258 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
259 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
260 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
261 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
262 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
263 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
264 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
266 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
267 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
268 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
269 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
270 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
271 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
272 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
273 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
274 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
275 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
276 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
277 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
278 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
279 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
280 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
281 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
283 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
284 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
285 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
286 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
287 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
288 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
289 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
290 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
293 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
294 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
295 #define CONFIG_SYS_CSPR3_EXT (0xf)
296 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
301 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
302 #define CONFIG_SYS_CSOR3 0x0
304 /* CPLD Timing parameters for IFC CS3 */
305 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
306 FTIM0_GPCM_TEADC(0x0e) | \
307 FTIM0_GPCM_TEAHC(0x0e))
308 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
309 FTIM1_GPCM_TRAD(0x1f))
310 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
311 FTIM2_GPCM_TCH(0x8) | \
312 FTIM2_GPCM_TWP(0x1f))
313 #define CONFIG_SYS_CS3_FTIM3 0x0
316 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
317 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
319 #define I2C_MUX_CH_DEFAULT 0x8
320 #define I2C_MUX_CH_VOL_MONITOR 0xa
321 #define I2C_MUX_CH_VSC3316_FS 0xc
322 #define I2C_MUX_CH_VSC3316_BS 0xd
324 /* Voltage monitor on channel 2*/
325 #define I2C_VOL_MONITOR_ADDR 0x40
326 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
327 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
328 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
330 /* The lowest and highest voltage allowed for T4240RDB */
331 #define VDD_MV_MIN 819
332 #define VDD_MV_MAX 1212
335 * eSPI - Enhanced SPI
339 #ifndef CONFIG_NOBQFMAN
340 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
341 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
342 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
343 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
344 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
345 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
346 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
347 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
348 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
349 CONFIG_SYS_BMAN_CENA_SIZE)
350 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
351 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
352 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
353 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
354 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
355 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
356 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
357 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
358 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
359 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
360 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
361 CONFIG_SYS_QMAN_CENA_SIZE)
362 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
363 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
365 #define CONFIG_SYS_DPAA_FMAN
366 #define CONFIG_SYS_DPAA_PME
367 #define CONFIG_SYS_PMAN
368 #define CONFIG_SYS_DPAA_DCE
369 #define CONFIG_SYS_DPAA_RMAN
370 #define CONFIG_SYS_INTERLAKEN
372 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
373 #endif /* CONFIG_NOBQFMAN */
375 #ifdef CONFIG_SYS_DPAA_FMAN
376 #define SGMII_PHY_ADDR1 0x0
377 #define SGMII_PHY_ADDR2 0x1
378 #define SGMII_PHY_ADDR3 0x2
379 #define SGMII_PHY_ADDR4 0x3
380 #define SGMII_PHY_ADDR5 0x4
381 #define SGMII_PHY_ADDR6 0x5
382 #define SGMII_PHY_ADDR7 0x6
383 #define SGMII_PHY_ADDR8 0x7
384 #define FM1_10GEC1_PHY_ADDR 0x10
385 #define FM1_10GEC2_PHY_ADDR 0x11
386 #define FM2_10GEC1_PHY_ADDR 0x12
387 #define FM2_10GEC2_PHY_ADDR 0x13
388 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
389 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
390 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
391 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
399 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
403 #define __USB_PHY_TYPE utmi
406 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
407 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
408 * interleaving. It can be cacheline, page, bank, superbank.
409 * See doc/README.fsl-ddr for details.
411 #ifdef CONFIG_ARCH_T4240
412 #define CTRL_INTLV_PREFERED 3way_4KB
414 #define CTRL_INTLV_PREFERED cacheline
417 #define CONFIG_EXTRA_ENV_SETTINGS \
418 "hwconfig=fsl_ddr:" \
419 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
421 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
423 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
424 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
425 "tftpflash=tftpboot $loadaddr $uboot && " \
426 "protect off $ubootaddr +$filesize && " \
427 "erase $ubootaddr +$filesize && " \
428 "cp.b $loadaddr $ubootaddr $filesize && " \
429 "protect on $ubootaddr +$filesize && " \
430 "cmp.b $loadaddr $ubootaddr $filesize\0" \
431 "consoledev=ttyS0\0" \
432 "ramdiskaddr=2000000\0" \
433 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
434 "fdtaddr=1e00000\0" \
435 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
439 "setenv bootargs config-addr=0x60000000; " \
440 "bootm 0x01000000 - 0x00f00000"
442 #include <asm/fsl_secure_boot.h>
444 #endif /* __CONFIG_H */