1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * T4240 RDB board configuration file
13 #include <linux/stringify.h>
15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #ifdef CONFIG_RAMBOOT_PBL
19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
22 #define RESET_VECTOR_OFFSET 0x27FFC
23 #define BOOT_PAGE_OFFSET 0x27000
26 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
27 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
28 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
29 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
30 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
34 #endif /* CONFIG_RAMBOOT_PBL */
36 /* High Level Configuration Options */
37 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
39 #ifndef CONFIG_RESET_VECTOR_ADDRESS
40 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
43 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
44 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
47 * These can be toggled for performance analysis, otherwise use default.
49 #define CONFIG_SYS_CACHE_STASHING
51 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
55 * Config the L3 Cache as L3 SRAM
57 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
58 #define CONFIG_SYS_L3_SIZE (512 << 10)
59 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
61 #define CONFIG_SYS_DCSRBAR 0xf0000000
62 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
67 #define CONFIG_VERY_BIG_RAM
68 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
69 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
74 #define CONFIG_SYS_FLASH_BASE 0xe0000000
75 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
77 #define CONFIG_HWCONFIG
79 /* define to use L1 as initial stack */
80 #define CONFIG_L1_INIT_RAM
81 #define CONFIG_SYS_INIT_RAM_LOCK
82 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
83 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
84 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
85 /* The assembler doesn't like typecast */
86 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
87 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
88 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
89 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
91 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
93 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
95 /* Serial Port - controlled on board with jumper J8
99 #define CONFIG_SYS_NS16550_SERIAL
100 #define CONFIG_SYS_NS16550_REG_SIZE 1
101 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
103 #define CONFIG_SYS_BAUDRATE_TABLE \
104 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
106 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
107 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
108 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
109 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
115 * Memory space is mapped 1-1, but I/O space must start from 0.
118 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
119 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
120 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
121 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
122 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
124 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
125 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
126 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
127 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
128 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
130 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
131 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
132 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
133 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
134 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
136 /* controller 4, Base address 203000 */
137 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
138 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
139 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
144 #define CONFIG_LOADS_ECHO /* echo on for serial download */
145 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
148 * Miscellaneous configurable options
152 * For booting Linux, the board info and command line data
153 * have to be in the first 64 MB of memory, since this is
154 * the maximum mapped by the Linux kernel during initialization.
156 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
157 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
160 * Environment Configuration
162 #define CONFIG_ROOTPATH "/opt/nfsroot"
163 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
166 "setenv bootargs config-addr=0x60000000; " \
167 "bootm 0x01000000 - 0x00f00000"
172 #define SPD_EEPROM_ADDRESS1 0x52
173 #define SPD_EEPROM_ADDRESS2 0x54
174 #define SPD_EEPROM_ADDRESS3 0x56
175 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
176 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
181 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
182 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
184 CSPR_PORT_SIZE_16 | \
187 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
188 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
189 CSPR_PORT_SIZE_16 | \
192 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
193 /* NOR Flash Timing Params */
194 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
196 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
197 FTIM0_NOR_TEADC(0x5) | \
198 FTIM0_NOR_TEAHC(0x5))
199 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
200 FTIM1_NOR_TRAD_NOR(0x1A) |\
201 FTIM1_NOR_TSEQRAD_NOR(0x13))
202 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
203 FTIM2_NOR_TCH(0x4) | \
204 FTIM2_NOR_TWPH(0x0E) | \
206 #define CONFIG_SYS_NOR_FTIM3 0x0
208 #define CONFIG_SYS_FLASH_QUIET_TEST
209 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
211 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
212 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
213 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
215 #define CONFIG_SYS_FLASH_EMPTY_INFO
216 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
217 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
219 /* NAND Flash on IFC */
220 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
221 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
222 #define CONFIG_SYS_NAND_BASE 0xff800000
223 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
225 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
226 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
227 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
228 | CSPR_MSEL_NAND /* MSEL = NAND */ \
230 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
232 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
233 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
234 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
235 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
236 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
237 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
238 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
240 /* ONFI NAND Flash mode0 Timing Params */
241 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
242 FTIM0_NAND_TWP(0x18) | \
243 FTIM0_NAND_TWCHT(0x07) | \
244 FTIM0_NAND_TWH(0x0a))
245 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
246 FTIM1_NAND_TWBE(0x39) | \
247 FTIM1_NAND_TRR(0x0e) | \
248 FTIM1_NAND_TRP(0x18))
249 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
250 FTIM2_NAND_TREH(0x0a) | \
251 FTIM2_NAND_TWHRE(0x1e))
252 #define CONFIG_SYS_NAND_FTIM3 0x0
254 #define CONFIG_SYS_NAND_DDR_LAW 11
255 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
256 #define CONFIG_SYS_MAX_NAND_DEVICE 1
258 #if defined(CONFIG_MTD_RAW_NAND)
259 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
260 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
261 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
262 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
263 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
264 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
265 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
266 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
267 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
268 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
269 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
270 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
271 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
272 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
273 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
274 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
276 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
277 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
278 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
279 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
280 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
281 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
282 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
283 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
284 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
285 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
286 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
287 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
288 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
289 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
290 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
291 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
293 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
294 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
295 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
296 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
297 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
298 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
299 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
300 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
303 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
304 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
305 #define CONFIG_SYS_CSPR3_EXT (0xf)
306 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
311 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
312 #define CONFIG_SYS_CSOR3 0x0
314 /* CPLD Timing parameters for IFC CS3 */
315 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
316 FTIM0_GPCM_TEADC(0x0e) | \
317 FTIM0_GPCM_TEAHC(0x0e))
318 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
319 FTIM1_GPCM_TRAD(0x1f))
320 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
321 FTIM2_GPCM_TCH(0x8) | \
322 FTIM2_GPCM_TWP(0x1f))
323 #define CONFIG_SYS_CS3_FTIM3 0x0
325 #if defined(CONFIG_RAMBOOT_PBL)
326 #define CONFIG_SYS_RAMBOOT
330 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
331 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
333 #define I2C_MUX_CH_DEFAULT 0x8
334 #define I2C_MUX_CH_VOL_MONITOR 0xa
335 #define I2C_MUX_CH_VSC3316_FS 0xc
336 #define I2C_MUX_CH_VSC3316_BS 0xd
338 /* Voltage monitor on channel 2*/
339 #define I2C_VOL_MONITOR_ADDR 0x40
340 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
341 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
342 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
344 /* The lowest and highest voltage allowed for T4240RDB */
345 #define VDD_MV_MIN 819
346 #define VDD_MV_MAX 1212
349 * eSPI - Enhanced SPI
353 #ifndef CONFIG_NOBQFMAN
354 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
355 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
356 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
357 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
358 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
359 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
360 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
361 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
362 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
363 CONFIG_SYS_BMAN_CENA_SIZE)
364 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
365 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
366 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
367 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
368 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
369 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
370 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
371 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
372 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
373 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
374 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
375 CONFIG_SYS_QMAN_CENA_SIZE)
376 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
377 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
379 #define CONFIG_SYS_DPAA_FMAN
380 #define CONFIG_SYS_DPAA_PME
381 #define CONFIG_SYS_PMAN
382 #define CONFIG_SYS_DPAA_DCE
383 #define CONFIG_SYS_DPAA_RMAN
384 #define CONFIG_SYS_INTERLAKEN
386 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
387 #endif /* CONFIG_NOBQFMAN */
389 #ifdef CONFIG_SYS_DPAA_FMAN
390 #define SGMII_PHY_ADDR1 0x0
391 #define SGMII_PHY_ADDR2 0x1
392 #define SGMII_PHY_ADDR3 0x2
393 #define SGMII_PHY_ADDR4 0x3
394 #define SGMII_PHY_ADDR5 0x4
395 #define SGMII_PHY_ADDR6 0x5
396 #define SGMII_PHY_ADDR7 0x6
397 #define SGMII_PHY_ADDR8 0x7
398 #define FM1_10GEC1_PHY_ADDR 0x10
399 #define FM1_10GEC2_PHY_ADDR 0x11
400 #define FM2_10GEC1_PHY_ADDR 0x12
401 #define FM2_10GEC2_PHY_ADDR 0x13
402 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
403 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
404 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
405 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
413 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
414 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
418 #define __USB_PHY_TYPE utmi
421 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
422 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
423 * interleaving. It can be cacheline, page, bank, superbank.
424 * See doc/README.fsl-ddr for details.
426 #ifdef CONFIG_ARCH_T4240
427 #define CTRL_INTLV_PREFERED 3way_4KB
429 #define CTRL_INTLV_PREFERED cacheline
432 #define CONFIG_EXTRA_ENV_SETTINGS \
433 "hwconfig=fsl_ddr:" \
434 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
436 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
438 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
439 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
440 "tftpflash=tftpboot $loadaddr $uboot && " \
441 "protect off $ubootaddr +$filesize && " \
442 "erase $ubootaddr +$filesize && " \
443 "cp.b $loadaddr $ubootaddr $filesize && " \
444 "protect on $ubootaddr +$filesize && " \
445 "cmp.b $loadaddr $ubootaddr $filesize\0" \
446 "consoledev=ttyS0\0" \
447 "ramdiskaddr=2000000\0" \
448 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
449 "fdtaddr=1e00000\0" \
450 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
454 "setenv bootargs config-addr=0x60000000; " \
455 "bootm 0x01000000 - 0x00f00000"
457 #include <asm/fsl_secure_boot.h>
459 #endif /* __CONFIG_H */