include/configs/T4240QDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T4240 QDS board configuration file
   8  */
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_FSL_SATA_V2
  13 #define CONFIG_PCIE4
  14
  15 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
  19 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
  20 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  21 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  22 #else
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_PAD_TO               0x40000
  25 #define CONFIG_SPL_MAX_SIZE             0x28000
  26 #define RESET_VECTOR_OFFSET             0x27FFC
  27 #define BOOT_PAGE_OFFSET                0x27000
  28
  29 #ifdef  CONFIG_NAND
  30 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  31 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  32 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  33 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  34 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
  36 #endif
  37
  38 #ifdef  CONFIG_SDCARD
  39 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  40 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  41 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  42 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  43 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  44 #ifndef CONFIG_SPL_BUILD
  45 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  46 #endif
  47 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  48 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
  49 #endif
  50
  51 #ifdef CONFIG_SPL_BUILD
  52 #define CONFIG_SPL_SKIP_RELOCATE
  53 #define CONFIG_SPL_COMMON_INIT_DDR
  54 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  55 #endif
  56
  57 #endif
  58 #endif /* CONFIG_RAMBOOT_PBL */
  59
  60 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  61 /* Set 1M boot space */
  62 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  63 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  64                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  65 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  66 #endif
  67
  68 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  69 #define CONFIG_DDR_ECC
  70
  71 #include "t4qds.h"
  72
  73 #if defined(CONFIG_SPIFLASH)
  74 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  75 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  76 #define CONFIG_ENV_SECT_SIZE            0x10000
  77 #elif defined(CONFIG_SDCARD)
  78 #define CONFIG_SYS_MMC_ENV_DEV          0
  79 #define CONFIG_ENV_SIZE                 0x2000
  80 #define CONFIG_ENV_OFFSET               (512 * 0x800)
  81 #elif defined(CONFIG_NAND)
  82 #define CONFIG_ENV_SIZE                 0x2000
  83 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  84 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  85 #define CONFIG_ENV_ADDR         0xffe20000
  86 #define CONFIG_ENV_SIZE         0x2000
  87 #elif defined(CONFIG_ENV_IS_NOWHERE)
  88 #define CONFIG_ENV_SIZE         0x2000
  89 #else
  90 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  91 #define CONFIG_ENV_SIZE         0x2000
  92 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  93 #endif
  94
  95 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
  96 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  97
  98 #ifndef __ASSEMBLY__
  99 unsigned long get_board_sys_clk(void);
 100 unsigned long get_board_ddr_clk(void);
 101 #endif
 102
 103 /* EEPROM */
 104 #define CONFIG_ID_EEPROM
 105 #define CONFIG_SYS_I2C_EEPROM_NXID
 106 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 107 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 108 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 109
 110 /*
 111  * DDR Setup
 112  */
 113 #define CONFIG_SYS_SPD_BUS_NUM  0
 114 #define SPD_EEPROM_ADDRESS1     0x51
 115 #define SPD_EEPROM_ADDRESS2     0x52
 116 #define SPD_EEPROM_ADDRESS3     0x53
 117 #define SPD_EEPROM_ADDRESS4     0x54
 118 #define SPD_EEPROM_ADDRESS5     0x55
 119 #define SPD_EEPROM_ADDRESS6     0x56
 120 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 121 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 122
 123 /*
 124  * IFC Definitions
 125  */
 126 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 127 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 128                                 + 0x8000000) | \
 129                                 CSPR_PORT_SIZE_16 | \
 130                                 CSPR_MSEL_NOR | \
 131                                 CSPR_V)
 132 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 133 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 134                                 CSPR_PORT_SIZE_16 | \
 135                                 CSPR_MSEL_NOR | \
 136                                 CSPR_V)
 137 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 138 /* NOR Flash Timing Params */
 139 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 140
 141 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 142                                 FTIM0_NOR_TEADC(0x5) | \
 143                                 FTIM0_NOR_TEAHC(0x5))
 144 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 145                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 146                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 147 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 148                                 FTIM2_NOR_TCH(0x4) | \
 149                                 FTIM2_NOR_TWPH(0x0E) | \
 150                                 FTIM2_NOR_TWP(0x1c))
 151 #define CONFIG_SYS_NOR_FTIM3    0x0
 152
 153 #define CONFIG_SYS_FLASH_QUIET_TEST
 154 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 155
 156 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 157 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 158 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 159 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 160
 161 #define CONFIG_SYS_FLASH_EMPTY_INFO
 162 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 163                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 164
 165 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 166 #define QIXIS_BASE                      0xffdf0000
 167 #define QIXIS_LBMAP_SWITCH              6
 168 #define QIXIS_LBMAP_MASK                0x0f
 169 #define QIXIS_LBMAP_SHIFT               0
 170 #define QIXIS_LBMAP_DFLTBANK            0x00
 171 #define QIXIS_LBMAP_ALTBANK             0x04
 172 #define QIXIS_RST_CTL_RESET             0x83
 173 #define QIXIS_RST_FORCE_MEM             0x1
 174 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 175 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 176 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 177 #define QIXIS_BRDCFG5                   0x55
 178 #define QIXIS_MUX_SDHC                  2
 179 #define QIXIS_MUX_SDHC_WIDTH8           1
 180 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 181
 182 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 183 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 184                                 | CSPR_PORT_SIZE_8 \
 185                                 | CSPR_MSEL_GPCM \
 186                                 | CSPR_V)
 187 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 188 #define CONFIG_SYS_CSOR3        0x0
 189 /* QIXIS Timing parameters for IFC CS3 */
 190 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 191                                         FTIM0_GPCM_TEADC(0x0e) | \
 192                                         FTIM0_GPCM_TEAHC(0x0e))
 193 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 194                                         FTIM1_GPCM_TRAD(0x3f))
 195 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 196                                         FTIM2_GPCM_TCH(0x8) | \
 197                                         FTIM2_GPCM_TWP(0x1f))
 198 #define CONFIG_SYS_CS3_FTIM3            0x0
 199
 200 /* NAND Flash on IFC */
 201 #define CONFIG_NAND_FSL_IFC
 202 #define CONFIG_SYS_NAND_BASE            0xff800000
 203 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 204
 205 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 206 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 207                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 208                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 209                                 | CSPR_V)
 210 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 211
 212 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 213                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 214                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 215                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 216                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 217                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 218                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 219
 220 #define CONFIG_SYS_NAND_ONFI_DETECTION
 221
 222 /* ONFI NAND Flash mode0 Timing Params */
 223 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 224                                         FTIM0_NAND_TWP(0x18)   | \
 225                                         FTIM0_NAND_TWCHT(0x07) | \
 226                                         FTIM0_NAND_TWH(0x0a))
 227 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 228                                         FTIM1_NAND_TWBE(0x39)  | \
 229                                         FTIM1_NAND_TRR(0x0e)   | \
 230                                         FTIM1_NAND_TRP(0x18))
 231 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 232                                         FTIM2_NAND_TREH(0x0a) | \
 233                                         FTIM2_NAND_TWHRE(0x1e))
 234 #define CONFIG_SYS_NAND_FTIM3           0x0
 235
 236 #define CONFIG_SYS_NAND_DDR_LAW         11
 237
 238 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 239 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 240
 241 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 242 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 243 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 244
 245 #if defined(CONFIG_NAND)
 246 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 247 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 248 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 249 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 250 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 251 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 252 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 253 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 254 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 255 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 256 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 257 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 258 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 259 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 260 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 261 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 262 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 263 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 264 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 265 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 266 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 267 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 268 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 269 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 270 #else
 271 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 272 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 273 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 274 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 275 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 276 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 277 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 278 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 279 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 280 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 281 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 282 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 283 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 284 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 285 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 286 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 287 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 288 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 289 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 290 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 291 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 292 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 293 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 294 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 295 #endif
 296
 297 #if defined(CONFIG_RAMBOOT_PBL)
 298 #define CONFIG_SYS_RAMBOOT
 299 #endif
 300
 301 /* I2C */
 302 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 303 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 304 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 305 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 306
 307 #define I2C_MUX_CH_DEFAULT      0x8
 308 #define I2C_MUX_CH_VOL_MONITOR  0xa
 309 #define I2C_MUX_CH_VSC3316_FS   0xc
 310 #define I2C_MUX_CH_VSC3316_BS   0xd
 311
 312 /* Voltage monitor on channel 2*/
 313 #define I2C_VOL_MONITOR_ADDR            0x40
 314 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 315 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 316 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 317
 318 /* VSC Crossbar switches */
 319 #define CONFIG_VSC_CROSSBAR
 320 #define VSC3316_FSM_TX_ADDR     0x70
 321 #define VSC3316_FSM_RX_ADDR     0x71
 322
 323 /*
 324  * RapidIO
 325  */
 326
 327 /*
 328  * for slave u-boot IMAGE instored in master memory space,
 329  * PHYS must be aligned based on the SIZE
 330  */
 331 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 332 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 333 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 334 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 335 /*
 336  * for slave UCODE and ENV instored in master memory space,
 337  * PHYS must be aligned based on the SIZE
 338  */
 339 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 340 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 341 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 342
 343 /* slave core release by master*/
 344 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 345 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 346
 347 /*
 348  * SRIO_PCIE_BOOT - SLAVE
 349  */
 350 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 351 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 352 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 353                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 354 #endif
 355 /*
 356  * eSPI - Enhanced SPI
 357  */
 358
 359 /* Qman/Bman */
 360 #ifndef CONFIG_NOBQFMAN
 361 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 362 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 363 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 364 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 365 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 366 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 367 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 368 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 369 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 370                                         CONFIG_SYS_BMAN_CENA_SIZE)
 371 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 372 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 373 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 374 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 375 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 376 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 377 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 378 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 379 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 380 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 381 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 382                                         CONFIG_SYS_QMAN_CENA_SIZE)
 383 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 384 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 385
 386 #define CONFIG_SYS_DPAA_FMAN
 387 #define CONFIG_SYS_DPAA_PME
 388 #define CONFIG_SYS_PMAN
 389 #define CONFIG_SYS_DPAA_DCE
 390 #define CONFIG_SYS_DPAA_RMAN
 391 #define CONFIG_SYS_INTERLAKEN
 392
 393 /* Default address of microcode for the Linux Fman driver */
 394 #if defined(CONFIG_SPIFLASH)
 395 /*
 396  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 397  * env, so we got 0x110000.
 398  */
 399 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 400 #elif defined(CONFIG_SDCARD)
 401 /*
 402  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 403  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 404  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 405  */
 406 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 407 #elif defined(CONFIG_NAND)
 408 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 409 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 410 /*
 411  * Slave has no ucode locally, it can fetch this from remote. When implementing
 412  * in two corenet boards, slave's ucode could be stored in master's memory
 413  * space, the address can be mapped from slave TLB->slave LAW->
 414  * slave SRIO or PCIE outbound window->master inbound window->
 415  * master LAW->the ucode address in master's memory space.
 416  */
 417 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 418 #else
 419 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 420 #endif
 421 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 422 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 423 #endif /* CONFIG_NOBQFMAN */
 424
 425 #ifdef CONFIG_SYS_DPAA_FMAN
 426 #define CONFIG_PHYLIB_10G
 427 #define CONFIG_PHY_VITESSE
 428 #define CONFIG_PHY_TERANETICS
 429 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 430 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 431 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 432 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 433 #define FM1_10GEC1_PHY_ADDR     0x0
 434 #define FM1_10GEC2_PHY_ADDR     0x1
 435 #define FM2_10GEC1_PHY_ADDR     0x2
 436 #define FM2_10GEC2_PHY_ADDR     0x3
 437 #endif
 438
 439 /* SATA */
 440 #ifdef CONFIG_FSL_SATA_V2
 441 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 442 #define CONFIG_SATA1
 443 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 444 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 445 #define CONFIG_SATA2
 446 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 447 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 448
 449 #define CONFIG_LBA48
 450 #endif
 451
 452 #ifdef CONFIG_FMAN_ENET
 453 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 454 #endif
 455
 456 /*
 457 * USB
 458 */
 459 #define CONFIG_USB_EHCI_FSL
 460 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 461 #define CONFIG_HAS_FSL_DR_USB
 462
 463 #ifdef CONFIG_MMC
 464 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 465 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 466 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 467 #define CONFIG_ESDHC_DETECT_QUIRK \
 468         (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
 469         IS_SVR_REV(get_svr(), 1, 0))
 470 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
 471         (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 472 #endif
 473
 474
 475 #define __USB_PHY_TYPE  utmi
 476
 477 /*
 478  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 479  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 480  * interleaving. It can be cacheline, page, bank, superbank.
 481  * See doc/README.fsl-ddr for details.
 482  */
 483 #ifdef CONFIG_ARCH_T4240
 484 #define CTRL_INTLV_PREFERED 3way_4KB
 485 #else
 486 #define CTRL_INTLV_PREFERED cacheline
 487 #endif
 488
 489 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 490         "hwconfig=fsl_ddr:"                                     \
 491         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 492         "bank_intlv=auto;"                                      \
 493         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 494         "netdev=eth0\0"                                         \
 495         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 496         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 497         "tftpflash=tftpboot $loadaddr $uboot && "               \
 498         "protect off $ubootaddr +$filesize && "                 \
 499         "erase $ubootaddr +$filesize && "                       \
 500         "cp.b $loadaddr $ubootaddr $filesize && "               \
 501         "protect on $ubootaddr +$filesize && "                  \
 502         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 503         "consoledev=ttyS0\0"                                    \
 504         "ramdiskaddr=2000000\0"                                 \
 505         "ramdiskfile=t4240qds/ramdisk.uboot\0"                  \
 506         "fdtaddr=1e00000\0"                                     \
 507         "fdtfile=t4240qds/t4240qds.dtb\0"                               \
 508         "bdev=sda3\0"
 509
 510 #define CONFIG_HVBOOT                           \
 511         "setenv bootargs config-addr=0x60000000; "      \
 512         "bootm 0x01000000 - 0x00f00000"
 513
 514 #define CONFIG_ALU                              \
 515         "setenv bootargs root=/dev/$bdev rw "           \
 516         "console=$consoledev,$baudrate $othbootargs;"   \
 517         "cpu 1 release 0x01000000 - - -;"               \
 518         "cpu 2 release 0x01000000 - - -;"               \
 519         "cpu 3 release 0x01000000 - - -;"               \
 520         "cpu 4 release 0x01000000 - - -;"               \
 521         "cpu 5 release 0x01000000 - - -;"               \
 522         "cpu 6 release 0x01000000 - - -;"               \
 523         "cpu 7 release 0x01000000 - - -;"               \
 524         "go 0x01000000"
 525
 526 #define CONFIG_LINUX                            \
 527         "setenv bootargs root=/dev/ram rw "             \
 528         "console=$consoledev,$baudrate $othbootargs;"   \
 529         "setenv ramdiskaddr 0x02000000;"                \
 530         "setenv fdtaddr 0x00c00000;"                    \
 531         "setenv loadaddr 0x1000000;"                    \
 532         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 533
 534 #define CONFIG_HDBOOT                                   \
 535         "setenv bootargs root=/dev/$bdev rw "           \
 536         "console=$consoledev,$baudrate $othbootargs;"   \
 537         "tftp $loadaddr $bootfile;"                     \
 538         "tftp $fdtaddr $fdtfile;"                       \
 539         "bootm $loadaddr - $fdtaddr"
 540
 541 #define CONFIG_NFSBOOTCOMMAND                   \
 542         "setenv bootargs root=/dev/nfs rw "     \
 543         "nfsroot=$serverip:$rootpath "          \
 544         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 545         "console=$consoledev,$baudrate $othbootargs;"   \
 546         "tftp $loadaddr $bootfile;"             \
 547         "tftp $fdtaddr $fdtfile;"               \
 548         "bootm $loadaddr - $fdtaddr"
 549
 550 #define CONFIG_RAMBOOTCOMMAND                           \
 551         "setenv bootargs root=/dev/ram rw "             \
 552         "console=$consoledev,$baudrate $othbootargs;"   \
 553         "tftp $ramdiskaddr $ramdiskfile;"               \
 554         "tftp $loadaddr $bootfile;"                     \
 555         "tftp $fdtaddr $fdtfile;"                       \
 556         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 557
 558 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 559
 560 #include <asm/fsl_secure_boot.h>
 561
 562 #endif  /* __CONFIG_H */