1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
7 * T4240 QDS board configuration file
12 #define CONFIG_FSL_SATA_V2
15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
19 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
20 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
21 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
23 #define CONFIG_SPL_FLUSH_IMAGE
24 #define CONFIG_SPL_PAD_TO 0x40000
25 #define CONFIG_SPL_MAX_SIZE 0x28000
26 #define RESET_VECTOR_OFFSET 0x27FFC
27 #define BOOT_PAGE_OFFSET 0x27000
30 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
31 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
32 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
33 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
34 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
39 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
40 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
41 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
42 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
43 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
44 #ifndef CONFIG_SPL_BUILD
45 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
47 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
50 #ifdef CONFIG_SPL_BUILD
51 #define CONFIG_SPL_SKIP_RELOCATE
52 #define CONFIG_SPL_COMMON_INIT_DDR
53 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
57 #endif /* CONFIG_RAMBOOT_PBL */
59 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
60 /* Set 1M boot space */
61 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
62 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
63 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
64 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
67 #define CONFIG_SRIO_PCIE_BOOT_MASTER
68 #define CONFIG_DDR_ECC
72 #if defined(CONFIG_SPIFLASH)
73 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
74 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
75 #define CONFIG_ENV_SECT_SIZE 0x10000
76 #elif defined(CONFIG_SDCARD)
77 #define CONFIG_SYS_MMC_ENV_DEV 0
78 #define CONFIG_ENV_SIZE 0x2000
79 #define CONFIG_ENV_OFFSET (512 * 0x800)
80 #elif defined(CONFIG_NAND)
81 #define CONFIG_ENV_SIZE 0x2000
82 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
83 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
84 #define CONFIG_ENV_ADDR 0xffe20000
85 #define CONFIG_ENV_SIZE 0x2000
86 #elif defined(CONFIG_ENV_IS_NOWHERE)
87 #define CONFIG_ENV_SIZE 0x2000
89 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
90 #define CONFIG_ENV_SIZE 0x2000
91 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
94 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
95 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
98 unsigned long get_board_sys_clk(void);
99 unsigned long get_board_ddr_clk(void);
103 #define CONFIG_ID_EEPROM
104 #define CONFIG_SYS_I2C_EEPROM_NXID
105 #define CONFIG_SYS_EEPROM_BUS_NUM 0
106 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
107 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
112 #define CONFIG_SYS_SPD_BUS_NUM 0
113 #define SPD_EEPROM_ADDRESS1 0x51
114 #define SPD_EEPROM_ADDRESS2 0x52
115 #define SPD_EEPROM_ADDRESS3 0x53
116 #define SPD_EEPROM_ADDRESS4 0x54
117 #define SPD_EEPROM_ADDRESS5 0x55
118 #define SPD_EEPROM_ADDRESS6 0x56
119 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
120 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
125 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
126 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
128 CSPR_PORT_SIZE_16 | \
131 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
132 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
133 CSPR_PORT_SIZE_16 | \
136 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
137 /* NOR Flash Timing Params */
138 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
140 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
141 FTIM0_NOR_TEADC(0x5) | \
142 FTIM0_NOR_TEAHC(0x5))
143 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
144 FTIM1_NOR_TRAD_NOR(0x1A) |\
145 FTIM1_NOR_TSEQRAD_NOR(0x13))
146 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
147 FTIM2_NOR_TCH(0x4) | \
148 FTIM2_NOR_TWPH(0x0E) | \
150 #define CONFIG_SYS_NOR_FTIM3 0x0
152 #define CONFIG_SYS_FLASH_QUIET_TEST
153 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
155 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
156 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
157 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
158 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
160 #define CONFIG_SYS_FLASH_EMPTY_INFO
161 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
162 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
164 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
165 #define QIXIS_BASE 0xffdf0000
166 #define QIXIS_LBMAP_SWITCH 6
167 #define QIXIS_LBMAP_MASK 0x0f
168 #define QIXIS_LBMAP_SHIFT 0
169 #define QIXIS_LBMAP_DFLTBANK 0x00
170 #define QIXIS_LBMAP_ALTBANK 0x04
171 #define QIXIS_RST_CTL_RESET 0x83
172 #define QIXIS_RST_FORCE_MEM 0x1
173 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
174 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
175 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
176 #define QIXIS_BRDCFG5 0x55
177 #define QIXIS_MUX_SDHC 2
178 #define QIXIS_MUX_SDHC_WIDTH8 1
179 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
181 #define CONFIG_SYS_CSPR3_EXT (0xf)
182 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
186 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
187 #define CONFIG_SYS_CSOR3 0x0
188 /* QIXIS Timing parameters for IFC CS3 */
189 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
190 FTIM0_GPCM_TEADC(0x0e) | \
191 FTIM0_GPCM_TEAHC(0x0e))
192 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
193 FTIM1_GPCM_TRAD(0x3f))
194 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
195 FTIM2_GPCM_TCH(0x8) | \
196 FTIM2_GPCM_TWP(0x1f))
197 #define CONFIG_SYS_CS3_FTIM3 0x0
199 /* NAND Flash on IFC */
200 #define CONFIG_NAND_FSL_IFC
201 #define CONFIG_SYS_NAND_BASE 0xff800000
202 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
204 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
205 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
206 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
207 | CSPR_MSEL_NAND /* MSEL = NAND */ \
209 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
211 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
212 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
213 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
214 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
215 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
216 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
217 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
219 #define CONFIG_SYS_NAND_ONFI_DETECTION
221 /* ONFI NAND Flash mode0 Timing Params */
222 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
223 FTIM0_NAND_TWP(0x18) | \
224 FTIM0_NAND_TWCHT(0x07) | \
225 FTIM0_NAND_TWH(0x0a))
226 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
227 FTIM1_NAND_TWBE(0x39) | \
228 FTIM1_NAND_TRR(0x0e) | \
229 FTIM1_NAND_TRP(0x18))
230 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
231 FTIM2_NAND_TREH(0x0a) | \
232 FTIM2_NAND_TWHRE(0x1e))
233 #define CONFIG_SYS_NAND_FTIM3 0x0
235 #define CONFIG_SYS_NAND_DDR_LAW 11
237 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
238 #define CONFIG_SYS_MAX_NAND_DEVICE 1
240 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
241 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
242 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
244 #if defined(CONFIG_NAND)
245 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
246 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
247 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
248 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
249 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
250 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
251 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
252 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
253 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
254 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
255 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
256 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
257 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
258 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
259 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
260 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
261 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
262 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
263 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
264 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
265 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
266 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
267 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
268 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
270 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
271 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
272 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
273 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
274 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
275 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
276 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
277 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
278 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
279 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
280 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
281 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
282 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
283 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
284 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
285 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
286 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
287 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
288 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
289 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
290 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
291 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
292 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
293 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
296 #if defined(CONFIG_RAMBOOT_PBL)
297 #define CONFIG_SYS_RAMBOOT
301 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
302 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
303 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
304 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
306 #define I2C_MUX_CH_DEFAULT 0x8
307 #define I2C_MUX_CH_VOL_MONITOR 0xa
308 #define I2C_MUX_CH_VSC3316_FS 0xc
309 #define I2C_MUX_CH_VSC3316_BS 0xd
311 /* Voltage monitor on channel 2*/
312 #define I2C_VOL_MONITOR_ADDR 0x40
313 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
314 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
315 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
317 /* VSC Crossbar switches */
318 #define CONFIG_VSC_CROSSBAR
319 #define VSC3316_FSM_TX_ADDR 0x70
320 #define VSC3316_FSM_RX_ADDR 0x71
327 * for slave u-boot IMAGE instored in master memory space,
328 * PHYS must be aligned based on the SIZE
330 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
331 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
332 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
333 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
335 * for slave UCODE and ENV instored in master memory space,
336 * PHYS must be aligned based on the SIZE
338 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
339 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
340 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
342 /* slave core release by master*/
343 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
344 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
347 * SRIO_PCIE_BOOT - SLAVE
349 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
350 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
351 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
352 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
355 * eSPI - Enhanced SPI
359 #ifndef CONFIG_NOBQFMAN
360 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
361 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
362 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
363 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
364 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
365 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
366 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
367 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
368 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
369 CONFIG_SYS_BMAN_CENA_SIZE)
370 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
371 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
372 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
373 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
374 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
375 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
376 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
377 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
378 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
379 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
380 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
381 CONFIG_SYS_QMAN_CENA_SIZE)
382 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
383 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
385 #define CONFIG_SYS_DPAA_FMAN
386 #define CONFIG_SYS_DPAA_PME
387 #define CONFIG_SYS_PMAN
388 #define CONFIG_SYS_DPAA_DCE
389 #define CONFIG_SYS_DPAA_RMAN
390 #define CONFIG_SYS_INTERLAKEN
392 /* Default address of microcode for the Linux Fman driver */
393 #if defined(CONFIG_SPIFLASH)
395 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
396 * env, so we got 0x110000.
398 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
399 #elif defined(CONFIG_SDCARD)
401 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
402 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
403 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
405 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
406 #elif defined(CONFIG_NAND)
407 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
408 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
410 * Slave has no ucode locally, it can fetch this from remote. When implementing
411 * in two corenet boards, slave's ucode could be stored in master's memory
412 * space, the address can be mapped from slave TLB->slave LAW->
413 * slave SRIO or PCIE outbound window->master inbound window->
414 * master LAW->the ucode address in master's memory space.
416 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
418 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
420 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
421 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
422 #endif /* CONFIG_NOBQFMAN */
424 #ifdef CONFIG_SYS_DPAA_FMAN
425 #define CONFIG_PHYLIB_10G
426 #define CONFIG_PHY_VITESSE
427 #define CONFIG_PHY_TERANETICS
428 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
429 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
430 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
431 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
432 #define FM1_10GEC1_PHY_ADDR 0x0
433 #define FM1_10GEC2_PHY_ADDR 0x1
434 #define FM2_10GEC1_PHY_ADDR 0x2
435 #define FM2_10GEC2_PHY_ADDR 0x3
439 #ifdef CONFIG_FSL_SATA_V2
440 #define CONFIG_SYS_SATA_MAX_DEVICE 2
442 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
443 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
445 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
446 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
451 #ifdef CONFIG_FMAN_ENET
452 #define CONFIG_ETHPRIME "FM1@DTSEC1"
458 #define CONFIG_USB_EHCI_FSL
459 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
460 #define CONFIG_HAS_FSL_DR_USB
463 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
464 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
465 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
466 #define CONFIG_ESDHC_DETECT_QUIRK \
467 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
468 IS_SVR_REV(get_svr(), 1, 0))
469 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
470 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
474 #define __USB_PHY_TYPE utmi
477 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
478 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
479 * interleaving. It can be cacheline, page, bank, superbank.
480 * See doc/README.fsl-ddr for details.
482 #ifdef CONFIG_ARCH_T4240
483 #define CTRL_INTLV_PREFERED 3way_4KB
485 #define CTRL_INTLV_PREFERED cacheline
488 #define CONFIG_EXTRA_ENV_SETTINGS \
489 "hwconfig=fsl_ddr:" \
490 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
492 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
494 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
495 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
496 "tftpflash=tftpboot $loadaddr $uboot && " \
497 "protect off $ubootaddr +$filesize && " \
498 "erase $ubootaddr +$filesize && " \
499 "cp.b $loadaddr $ubootaddr $filesize && " \
500 "protect on $ubootaddr +$filesize && " \
501 "cmp.b $loadaddr $ubootaddr $filesize\0" \
502 "consoledev=ttyS0\0" \
503 "ramdiskaddr=2000000\0" \
504 "ramdiskfile=t4240qds/ramdisk.uboot\0" \
505 "fdtaddr=1e00000\0" \
506 "fdtfile=t4240qds/t4240qds.dtb\0" \
509 #define CONFIG_HVBOOT \
510 "setenv bootargs config-addr=0x60000000; " \
511 "bootm 0x01000000 - 0x00f00000"
514 "setenv bootargs root=/dev/$bdev rw " \
515 "console=$consoledev,$baudrate $othbootargs;" \
516 "cpu 1 release 0x01000000 - - -;" \
517 "cpu 2 release 0x01000000 - - -;" \
518 "cpu 3 release 0x01000000 - - -;" \
519 "cpu 4 release 0x01000000 - - -;" \
520 "cpu 5 release 0x01000000 - - -;" \
521 "cpu 6 release 0x01000000 - - -;" \
522 "cpu 7 release 0x01000000 - - -;" \
525 #define CONFIG_LINUX \
526 "setenv bootargs root=/dev/ram rw " \
527 "console=$consoledev,$baudrate $othbootargs;" \
528 "setenv ramdiskaddr 0x02000000;" \
529 "setenv fdtaddr 0x00c00000;" \
530 "setenv loadaddr 0x1000000;" \
531 "bootm $loadaddr $ramdiskaddr $fdtaddr"
533 #define CONFIG_HDBOOT \
534 "setenv bootargs root=/dev/$bdev rw " \
535 "console=$consoledev,$baudrate $othbootargs;" \
536 "tftp $loadaddr $bootfile;" \
537 "tftp $fdtaddr $fdtfile;" \
538 "bootm $loadaddr - $fdtaddr"
540 #define CONFIG_NFSBOOTCOMMAND \
541 "setenv bootargs root=/dev/nfs rw " \
542 "nfsroot=$serverip:$rootpath " \
543 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
544 "console=$consoledev,$baudrate $othbootargs;" \
545 "tftp $loadaddr $bootfile;" \
546 "tftp $fdtaddr $fdtfile;" \
547 "bootm $loadaddr - $fdtaddr"
549 #define CONFIG_RAMBOOTCOMMAND \
550 "setenv bootargs root=/dev/ram rw " \
551 "console=$consoledev,$baudrate $othbootargs;" \
552 "tftp $ramdiskaddr $ramdiskfile;" \
553 "tftp $loadaddr $bootfile;" \
554 "tftp $fdtaddr $fdtfile;" \
555 "bootm $loadaddr $ramdiskaddr $fdtaddr"
557 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
559 #include <asm/fsl_secure_boot.h>
561 #endif /* __CONFIG_H */