2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T4240 QDS board configuration file
13 #define CONFIG_FSL_SATA_V2
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
18 #ifdef CONFIG_RAMBOOT_PBL
19 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
20 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
26 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
27 #define CONFIG_SPL_PAD_TO 0x40000
28 #define CONFIG_SPL_MAX_SIZE 0x28000
29 #define RESET_VECTOR_OFFSET 0x27FFC
30 #define BOOT_PAGE_OFFSET 0x27000
33 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
34 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
35 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
36 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
37 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
38 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
39 #define CONFIG_SPL_NAND_BOOT
43 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
44 #define CONFIG_SPL_MMC_MINIMAL
45 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
46 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
47 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
48 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
49 #ifndef CONFIG_SPL_BUILD
50 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
52 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
54 #define CONFIG_SPL_MMC_BOOT
57 #ifdef CONFIG_SPL_BUILD
58 #define CONFIG_SPL_SKIP_RELOCATE
59 #define CONFIG_SPL_COMMON_INIT_DDR
60 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
64 #endif /* CONFIG_RAMBOOT_PBL */
66 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
67 /* Set 1M boot space */
68 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
69 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
70 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
71 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
74 #define CONFIG_SRIO_PCIE_BOOT_MASTER
75 #define CONFIG_DDR_ECC
79 #ifndef CONFIG_MTD_NOR_FLASH
81 #define CONFIG_FLASH_CFI_DRIVER
82 #define CONFIG_SYS_FLASH_CFI
83 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
86 #if defined(CONFIG_SPIFLASH)
87 #define CONFIG_SYS_EXTRA_ENV_RELOC
88 #define CONFIG_ENV_SPI_BUS 0
89 #define CONFIG_ENV_SPI_CS 0
90 #define CONFIG_ENV_SPI_MAX_HZ 10000000
91 #define CONFIG_ENV_SPI_MODE 0
92 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
93 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
94 #define CONFIG_ENV_SECT_SIZE 0x10000
95 #elif defined(CONFIG_SDCARD)
96 #define CONFIG_SYS_EXTRA_ENV_RELOC
97 #define CONFIG_SYS_MMC_ENV_DEV 0
98 #define CONFIG_ENV_SIZE 0x2000
99 #define CONFIG_ENV_OFFSET (512 * 0x800)
100 #elif defined(CONFIG_NAND)
101 #define CONFIG_SYS_EXTRA_ENV_RELOC
102 #define CONFIG_ENV_SIZE 0x2000
103 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
104 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
105 #define CONFIG_ENV_ADDR 0xffe20000
106 #define CONFIG_ENV_SIZE 0x2000
107 #elif defined(CONFIG_ENV_IS_NOWHERE)
108 #define CONFIG_ENV_SIZE 0x2000
110 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
111 #define CONFIG_ENV_SIZE 0x2000
112 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
115 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
116 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
119 unsigned long get_board_sys_clk(void);
120 unsigned long get_board_ddr_clk(void);
124 #define CONFIG_ID_EEPROM
125 #define CONFIG_SYS_I2C_EEPROM_NXID
126 #define CONFIG_SYS_EEPROM_BUS_NUM 0
127 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
128 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
133 #define CONFIG_SYS_SPD_BUS_NUM 0
134 #define SPD_EEPROM_ADDRESS1 0x51
135 #define SPD_EEPROM_ADDRESS2 0x52
136 #define SPD_EEPROM_ADDRESS3 0x53
137 #define SPD_EEPROM_ADDRESS4 0x54
138 #define SPD_EEPROM_ADDRESS5 0x55
139 #define SPD_EEPROM_ADDRESS6 0x56
140 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
141 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
146 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
147 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
149 CSPR_PORT_SIZE_16 | \
152 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
153 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
154 CSPR_PORT_SIZE_16 | \
157 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
158 /* NOR Flash Timing Params */
159 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
161 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
162 FTIM0_NOR_TEADC(0x5) | \
163 FTIM0_NOR_TEAHC(0x5))
164 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
165 FTIM1_NOR_TRAD_NOR(0x1A) |\
166 FTIM1_NOR_TSEQRAD_NOR(0x13))
167 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
168 FTIM2_NOR_TCH(0x4) | \
169 FTIM2_NOR_TWPH(0x0E) | \
171 #define CONFIG_SYS_NOR_FTIM3 0x0
173 #define CONFIG_SYS_FLASH_QUIET_TEST
174 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
176 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
177 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
178 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
179 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
181 #define CONFIG_SYS_FLASH_EMPTY_INFO
182 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
183 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
185 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
186 #define QIXIS_BASE 0xffdf0000
187 #define QIXIS_LBMAP_SWITCH 6
188 #define QIXIS_LBMAP_MASK 0x0f
189 #define QIXIS_LBMAP_SHIFT 0
190 #define QIXIS_LBMAP_DFLTBANK 0x00
191 #define QIXIS_LBMAP_ALTBANK 0x04
192 #define QIXIS_RST_CTL_RESET 0x83
193 #define QIXIS_RST_FORCE_MEM 0x1
194 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
195 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
196 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
197 #define QIXIS_BRDCFG5 0x55
198 #define QIXIS_MUX_SDHC 2
199 #define QIXIS_MUX_SDHC_WIDTH8 1
200 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
202 #define CONFIG_SYS_CSPR3_EXT (0xf)
203 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
207 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
208 #define CONFIG_SYS_CSOR3 0x0
209 /* QIXIS Timing parameters for IFC CS3 */
210 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
211 FTIM0_GPCM_TEADC(0x0e) | \
212 FTIM0_GPCM_TEAHC(0x0e))
213 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
214 FTIM1_GPCM_TRAD(0x3f))
215 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
216 FTIM2_GPCM_TCH(0x8) | \
217 FTIM2_GPCM_TWP(0x1f))
218 #define CONFIG_SYS_CS3_FTIM3 0x0
220 /* NAND Flash on IFC */
221 #define CONFIG_NAND_FSL_IFC
222 #define CONFIG_SYS_NAND_BASE 0xff800000
223 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
225 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
226 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
227 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
228 | CSPR_MSEL_NAND /* MSEL = NAND */ \
230 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
232 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
233 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
234 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
235 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
236 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
237 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
238 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
240 #define CONFIG_SYS_NAND_ONFI_DETECTION
242 /* ONFI NAND Flash mode0 Timing Params */
243 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
244 FTIM0_NAND_TWP(0x18) | \
245 FTIM0_NAND_TWCHT(0x07) | \
246 FTIM0_NAND_TWH(0x0a))
247 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
248 FTIM1_NAND_TWBE(0x39) | \
249 FTIM1_NAND_TRR(0x0e) | \
250 FTIM1_NAND_TRP(0x18))
251 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
252 FTIM2_NAND_TREH(0x0a) | \
253 FTIM2_NAND_TWHRE(0x1e))
254 #define CONFIG_SYS_NAND_FTIM3 0x0
256 #define CONFIG_SYS_NAND_DDR_LAW 11
258 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
259 #define CONFIG_SYS_MAX_NAND_DEVICE 1
261 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
262 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
263 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
265 #if defined(CONFIG_NAND)
266 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
267 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
268 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
269 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
270 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
271 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
272 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
273 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
274 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
275 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
276 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
277 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
278 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
279 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
280 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
281 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
282 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
283 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
284 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
285 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
286 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
287 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
288 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
289 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
291 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
292 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
293 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
294 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
295 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
296 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
297 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
298 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
299 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
300 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
301 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
302 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
303 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
304 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
305 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
306 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
307 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
308 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
309 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
310 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
311 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
312 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
313 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
314 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
317 #if defined(CONFIG_RAMBOOT_PBL)
318 #define CONFIG_SYS_RAMBOOT
322 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
323 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
324 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
325 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
327 #define I2C_MUX_CH_DEFAULT 0x8
328 #define I2C_MUX_CH_VOL_MONITOR 0xa
329 #define I2C_MUX_CH_VSC3316_FS 0xc
330 #define I2C_MUX_CH_VSC3316_BS 0xd
332 /* Voltage monitor on channel 2*/
333 #define I2C_VOL_MONITOR_ADDR 0x40
334 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
335 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
336 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
338 /* VSC Crossbar switches */
339 #define CONFIG_VSC_CROSSBAR
340 #define VSC3316_FSM_TX_ADDR 0x70
341 #define VSC3316_FSM_RX_ADDR 0x71
348 * for slave u-boot IMAGE instored in master memory space,
349 * PHYS must be aligned based on the SIZE
351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
353 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
354 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
356 * for slave UCODE and ENV instored in master memory space,
357 * PHYS must be aligned based on the SIZE
359 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
360 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
361 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
363 /* slave core release by master*/
364 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
365 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
368 * SRIO_PCIE_BOOT - SLAVE
370 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
371 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
372 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
373 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
376 * eSPI - Enhanced SPI
378 #define CONFIG_SF_DEFAULT_SPEED 10000000
379 #define CONFIG_SF_DEFAULT_MODE 0
382 #ifndef CONFIG_NOBQFMAN
383 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
384 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
385 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
386 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
387 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
388 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
389 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
390 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
391 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
392 CONFIG_SYS_BMAN_CENA_SIZE)
393 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
394 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
395 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
396 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
397 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
398 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
399 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
400 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
401 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
402 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
403 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
404 CONFIG_SYS_QMAN_CENA_SIZE)
405 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
406 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
408 #define CONFIG_SYS_DPAA_FMAN
409 #define CONFIG_SYS_DPAA_PME
410 #define CONFIG_SYS_PMAN
411 #define CONFIG_SYS_DPAA_DCE
412 #define CONFIG_SYS_DPAA_RMAN
413 #define CONFIG_SYS_INTERLAKEN
415 /* Default address of microcode for the Linux Fman driver */
416 #if defined(CONFIG_SPIFLASH)
418 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
419 * env, so we got 0x110000.
421 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
422 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
423 #elif defined(CONFIG_SDCARD)
425 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
426 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
427 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
429 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
430 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
431 #elif defined(CONFIG_NAND)
432 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
433 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
434 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
436 * Slave has no ucode locally, it can fetch this from remote. When implementing
437 * in two corenet boards, slave's ucode could be stored in master's memory
438 * space, the address can be mapped from slave TLB->slave LAW->
439 * slave SRIO or PCIE outbound window->master inbound window->
440 * master LAW->the ucode address in master's memory space.
442 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
443 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
445 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
446 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
448 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
449 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
450 #endif /* CONFIG_NOBQFMAN */
452 #ifdef CONFIG_SYS_DPAA_FMAN
453 #define CONFIG_FMAN_ENET
454 #define CONFIG_PHYLIB_10G
455 #define CONFIG_PHY_VITESSE
456 #define CONFIG_PHY_TERANETICS
457 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
458 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
459 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
460 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
461 #define FM1_10GEC1_PHY_ADDR 0x0
462 #define FM1_10GEC2_PHY_ADDR 0x1
463 #define FM2_10GEC1_PHY_ADDR 0x2
464 #define FM2_10GEC2_PHY_ADDR 0x3
468 #ifdef CONFIG_FSL_SATA_V2
469 #define CONFIG_SYS_SATA_MAX_DEVICE 2
471 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
472 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
474 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
475 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
480 #ifdef CONFIG_FMAN_ENET
481 #define CONFIG_MII /* MII PHY management */
482 #define CONFIG_ETHPRIME "FM1@DTSEC1"
488 #define CONFIG_USB_EHCI_FSL
489 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
490 #define CONFIG_HAS_FSL_DR_USB
493 #define CONFIG_FSL_ESDHC
494 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
495 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
496 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
497 #define CONFIG_ESDHC_DETECT_QUIRK \
498 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
499 IS_SVR_REV(get_svr(), 1, 0))
500 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
501 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
505 #define __USB_PHY_TYPE utmi
508 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
509 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
510 * interleaving. It can be cacheline, page, bank, superbank.
511 * See doc/README.fsl-ddr for details.
513 #ifdef CONFIG_ARCH_T4240
514 #define CTRL_INTLV_PREFERED 3way_4KB
516 #define CTRL_INTLV_PREFERED cacheline
519 #define CONFIG_EXTRA_ENV_SETTINGS \
520 "hwconfig=fsl_ddr:" \
521 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
523 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
525 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
526 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
527 "tftpflash=tftpboot $loadaddr $uboot && " \
528 "protect off $ubootaddr +$filesize && " \
529 "erase $ubootaddr +$filesize && " \
530 "cp.b $loadaddr $ubootaddr $filesize && " \
531 "protect on $ubootaddr +$filesize && " \
532 "cmp.b $loadaddr $ubootaddr $filesize\0" \
533 "consoledev=ttyS0\0" \
534 "ramdiskaddr=2000000\0" \
535 "ramdiskfile=t4240qds/ramdisk.uboot\0" \
536 "fdtaddr=1e00000\0" \
537 "fdtfile=t4240qds/t4240qds.dtb\0" \
540 #define CONFIG_HVBOOT \
541 "setenv bootargs config-addr=0x60000000; " \
542 "bootm 0x01000000 - 0x00f00000"
545 "setenv bootargs root=/dev/$bdev rw " \
546 "console=$consoledev,$baudrate $othbootargs;" \
547 "cpu 1 release 0x01000000 - - -;" \
548 "cpu 2 release 0x01000000 - - -;" \
549 "cpu 3 release 0x01000000 - - -;" \
550 "cpu 4 release 0x01000000 - - -;" \
551 "cpu 5 release 0x01000000 - - -;" \
552 "cpu 6 release 0x01000000 - - -;" \
553 "cpu 7 release 0x01000000 - - -;" \
556 #define CONFIG_LINUX \
557 "setenv bootargs root=/dev/ram rw " \
558 "console=$consoledev,$baudrate $othbootargs;" \
559 "setenv ramdiskaddr 0x02000000;" \
560 "setenv fdtaddr 0x00c00000;" \
561 "setenv loadaddr 0x1000000;" \
562 "bootm $loadaddr $ramdiskaddr $fdtaddr"
564 #define CONFIG_HDBOOT \
565 "setenv bootargs root=/dev/$bdev rw " \
566 "console=$consoledev,$baudrate $othbootargs;" \
567 "tftp $loadaddr $bootfile;" \
568 "tftp $fdtaddr $fdtfile;" \
569 "bootm $loadaddr - $fdtaddr"
571 #define CONFIG_NFSBOOTCOMMAND \
572 "setenv bootargs root=/dev/nfs rw " \
573 "nfsroot=$serverip:$rootpath " \
574 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
575 "console=$consoledev,$baudrate $othbootargs;" \
576 "tftp $loadaddr $bootfile;" \
577 "tftp $fdtaddr $fdtfile;" \
578 "bootm $loadaddr - $fdtaddr"
580 #define CONFIG_RAMBOOTCOMMAND \
581 "setenv bootargs root=/dev/ram rw " \
582 "console=$consoledev,$baudrate $othbootargs;" \
583 "tftp $ramdiskaddr $ramdiskfile;" \
584 "tftp $loadaddr $bootfile;" \
585 "tftp $fdtaddr $fdtfile;" \
586 "bootm $loadaddr $ramdiskaddr $fdtaddr"
588 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
590 #include <asm/fsl_secure_boot.h>
592 #endif /* __CONFIG_H */