include/configs/T4240QDS.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T4240 QDS board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_T4240QDS
  14 #define CONFIG_PHYS_64BIT
  15
  16 #define CONFIG_FSL_SATA_V2
  17 #define CONFIG_PCIE4
  18
  19 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  20
  21 #ifdef CONFIG_RAMBOOT_PBL
  22 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  23 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  24 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
  25 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
  26 #endif
  27
  28 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  29 /* Set 1M boot space */
  30 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  31 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  32                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  34 #define CONFIG_SYS_NO_FLASH
  35 #endif
  36
  37 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  38 #define CONFIG_DDR_ECC
  39
  40 #include "t4qds.h"
  41
  42 #ifdef CONFIG_SYS_NO_FLASH
  43 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
  44 #define CONFIG_ENV_IS_NOWHERE
  45 #endif
  46 #else
  47 #define CONFIG_FLASH_CFI_DRIVER
  48 #define CONFIG_SYS_FLASH_CFI
  49 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  50 #endif
  51
  52 #if defined(CONFIG_SPIFLASH)
  53 #define CONFIG_SYS_EXTRA_ENV_RELOC
  54 #define CONFIG_ENV_IS_IN_SPI_FLASH
  55 #define CONFIG_ENV_SPI_BUS              0
  56 #define CONFIG_ENV_SPI_CS               0
  57 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  58 #define CONFIG_ENV_SPI_MODE             0
  59 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  60 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  61 #define CONFIG_ENV_SECT_SIZE            0x10000
  62 #elif defined(CONFIG_SDCARD)
  63 #define CONFIG_SYS_EXTRA_ENV_RELOC
  64 #define CONFIG_ENV_IS_IN_MMC
  65 #define CONFIG_SYS_MMC_ENV_DEV          0
  66 #define CONFIG_ENV_SIZE                 0x2000
  67 #define CONFIG_ENV_OFFSET               (512 * 1097)
  68 #elif defined(CONFIG_NAND)
  69 #define CONFIG_SYS_EXTRA_ENV_RELOC
  70 #define CONFIG_ENV_IS_IN_NAND
  71 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  72 #define CONFIG_ENV_OFFSET               (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
  73 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  74 #define CONFIG_ENV_IS_IN_REMOTE
  75 #define CONFIG_ENV_ADDR         0xffe20000
  76 #define CONFIG_ENV_SIZE         0x2000
  77 #elif defined(CONFIG_ENV_IS_NOWHERE)
  78 #define CONFIG_ENV_SIZE         0x2000
  79 #else
  80 #define CONFIG_ENV_IS_IN_FLASH
  81 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  82 #define CONFIG_ENV_SIZE         0x2000
  83 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  84 #endif
  85
  86 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
  87 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  88
  89 #ifndef __ASSEMBLY__
  90 unsigned long get_board_sys_clk(void);
  91 unsigned long get_board_ddr_clk(void);
  92 #endif
  93
  94 /* EEPROM */
  95 #define CONFIG_ID_EEPROM
  96 #define CONFIG_SYS_I2C_EEPROM_NXID
  97 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  98 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
  99 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 100
 101 /*
 102  * DDR Setup
 103  */
 104 #define CONFIG_SYS_SPD_BUS_NUM  0
 105 #define SPD_EEPROM_ADDRESS1     0x51
 106 #define SPD_EEPROM_ADDRESS2     0x52
 107 #define SPD_EEPROM_ADDRESS3     0x53
 108 #define SPD_EEPROM_ADDRESS4     0x54
 109 #define SPD_EEPROM_ADDRESS5     0x55
 110 #define SPD_EEPROM_ADDRESS6     0x56
 111 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 112 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 113
 114 /*
 115  * IFC Definitions
 116  */
 117 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 118 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 119                                 + 0x8000000) | \
 120                                 CSPR_PORT_SIZE_16 | \
 121                                 CSPR_MSEL_NOR | \
 122                                 CSPR_V)
 123 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 124 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 125                                 CSPR_PORT_SIZE_16 | \
 126                                 CSPR_MSEL_NOR | \
 127                                 CSPR_V)
 128 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 129 /* NOR Flash Timing Params */
 130 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 131
 132 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 133                                 FTIM0_NOR_TEADC(0x5) | \
 134                                 FTIM0_NOR_TEAHC(0x5))
 135 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 136                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 137                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 138 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 139                                 FTIM2_NOR_TCH(0x4) | \
 140                                 FTIM2_NOR_TWPH(0x0E) | \
 141                                 FTIM2_NOR_TWP(0x1c))
 142 #define CONFIG_SYS_NOR_FTIM3    0x0
 143
 144 #define CONFIG_SYS_FLASH_QUIET_TEST
 145 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 146
 147 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 148 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 149 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 150 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 151
 152 #define CONFIG_SYS_FLASH_EMPTY_INFO
 153 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 154                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 155
 156 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 157 #define QIXIS_BASE                      0xffdf0000
 158 #define QIXIS_LBMAP_SWITCH              6
 159 #define QIXIS_LBMAP_MASK                0x0f
 160 #define QIXIS_LBMAP_SHIFT               0
 161 #define QIXIS_LBMAP_DFLTBANK            0x00
 162 #define QIXIS_LBMAP_ALTBANK             0x04
 163 #define QIXIS_RST_CTL_RESET             0x83
 164 #define QIXIS_RST_FORCE_MEM             0x1
 165 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 166 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 167 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 168 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 169
 170 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 171 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 172                                 | CSPR_PORT_SIZE_8 \
 173                                 | CSPR_MSEL_GPCM \
 174                                 | CSPR_V)
 175 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 176 #define CONFIG_SYS_CSOR3        0x0
 177 /* QIXIS Timing parameters for IFC CS3 */
 178 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 179                                         FTIM0_GPCM_TEADC(0x0e) | \
 180                                         FTIM0_GPCM_TEAHC(0x0e))
 181 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 182                                         FTIM1_GPCM_TRAD(0x3f))
 183 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 184                                         FTIM2_GPCM_TCH(0x0) | \
 185                                         FTIM2_GPCM_TWP(0x1f))
 186 #define CONFIG_SYS_CS3_FTIM3            0x0
 187
 188 /* NAND Flash on IFC */
 189 #define CONFIG_NAND_FSL_IFC
 190 #define CONFIG_SYS_NAND_BASE            0xff800000
 191 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 192
 193 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 194 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 195                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 196                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 197                                 | CSPR_V)
 198 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 199
 200 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 201                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 202                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 203                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 204                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 205                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 206                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 207
 208 #define CONFIG_SYS_NAND_ONFI_DETECTION
 209
 210 /* ONFI NAND Flash mode0 Timing Params */
 211 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 212                                         FTIM0_NAND_TWP(0x18)   | \
 213                                         FTIM0_NAND_TWCHT(0x07) | \
 214                                         FTIM0_NAND_TWH(0x0a))
 215 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 216                                         FTIM1_NAND_TWBE(0x39)  | \
 217                                         FTIM1_NAND_TRR(0x0e)   | \
 218                                         FTIM1_NAND_TRP(0x18))
 219 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 220                                         FTIM2_NAND_TREH(0x0a) | \
 221                                         FTIM2_NAND_TWHRE(0x1e))
 222 #define CONFIG_SYS_NAND_FTIM3           0x0
 223
 224 #define CONFIG_SYS_NAND_DDR_LAW         11
 225
 226 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 227 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 228 #define CONFIG_MTD_NAND_VERIFY_WRITE
 229 #define CONFIG_CMD_NAND
 230
 231 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 232 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 233 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 234
 235 #if defined(CONFIG_NAND)
 236 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 237 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 238 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 239 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 240 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 241 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 242 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 243 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 244 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 245 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 246 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 247 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 248 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 249 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 250 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 251 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 252 #else
 253 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 254 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 255 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 256 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 257 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 258 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 259 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 260 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 261 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 262 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 263 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 264 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 265 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 266 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 267 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 268 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 269 #endif
 270 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 271 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 272 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 273 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 274 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 275 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 276 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 277 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 278
 279 #if defined(CONFIG_RAMBOOT_PBL)
 280 #define CONFIG_SYS_RAMBOOT
 281 #endif
 282
 283
 284 /* I2C */
 285 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 286 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 287 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 288 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 289
 290 #define I2C_MUX_CH_DEFAULT      0x8
 291 #define I2C_MUX_CH_VOL_MONITOR  0xa
 292 #define I2C_MUX_CH_VSC3316_FS   0xc
 293 #define I2C_MUX_CH_VSC3316_BS   0xd
 294
 295 /* Voltage monitor on channel 2*/
 296 #define I2C_VOL_MONITOR_ADDR            0x40
 297 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 298 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 299 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 300
 301 /* VSC Crossbar switches */
 302 #define CONFIG_VSC_CROSSBAR
 303 #define VSC3316_FSM_TX_ADDR     0x70
 304 #define VSC3316_FSM_RX_ADDR     0x71
 305
 306 /*
 307  * RapidIO
 308  */
 309
 310 /*
 311  * for slave u-boot IMAGE instored in master memory space,
 312  * PHYS must be aligned based on the SIZE
 313  */
 314 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
 315 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
 316 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000        /* 512K */
 317 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
 318 /*
 319  * for slave UCODE and ENV instored in master memory space,
 320  * PHYS must be aligned based on the SIZE
 321  */
 322 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
 323 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 324 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 325
 326 /* slave core release by master*/
 327 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 328 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 329
 330 /*
 331  * SRIO_PCIE_BOOT - SLAVE
 332  */
 333 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 334 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 335 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 336                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 337 #endif
 338 /*
 339  * eSPI - Enhanced SPI
 340  */
 341 #define CONFIG_FSL_ESPI
 342 #define CONFIG_SPI_FLASH
 343 #define CONFIG_SPI_FLASH_SST
 344 #define CONFIG_CMD_SF
 345 #define CONFIG_SF_DEFAULT_SPEED         10000000
 346 #define CONFIG_SF_DEFAULT_MODE          0
 347
 348
 349 /* Qman/Bman */
 350 #ifndef CONFIG_NOBQFMAN
 351 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 352 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 353 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 354 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 355 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 356 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 357 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 358 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 359 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 360
 361 #define CONFIG_SYS_DPAA_FMAN
 362 #define CONFIG_SYS_DPAA_PME
 363 #define CONFIG_SYS_PMAN
 364 #define CONFIG_SYS_DPAA_DCE
 365 #define CONFIG_SYS_DPAA_RMAN
 366 #define CONFIG_SYS_INTERLAKEN
 367
 368 /* Default address of microcode for the Linux Fman driver */
 369 #if defined(CONFIG_SPIFLASH)
 370 /*
 371  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 372  * env, so we got 0x110000.
 373  */
 374 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 375 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
 376 #elif defined(CONFIG_SDCARD)
 377 /*
 378  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 379  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 380  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 381  */
 382 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 383 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1130)
 384 #elif defined(CONFIG_NAND)
 385 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 386 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 387 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 388 /*
 389  * Slave has no ucode locally, it can fetch this from remote. When implementing
 390  * in two corenet boards, slave's ucode could be stored in master's memory
 391  * space, the address can be mapped from slave TLB->slave LAW->
 392  * slave SRIO or PCIE outbound window->master inbound window->
 393  * master LAW->the ucode address in master's memory space.
 394  */
 395 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 396 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xFFE00000
 397 #else
 398 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 399 #define CONFIG_SYS_QE_FMAN_FW_ADDR              0xEFF40000
 400 #endif
 401 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 402 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 403 #endif /* CONFIG_NOBQFMAN */
 404
 405 #ifdef CONFIG_SYS_DPAA_FMAN
 406 #define CONFIG_FMAN_ENET
 407 #define CONFIG_PHYLIB_10G
 408 #define CONFIG_PHY_VITESSE
 409 #define CONFIG_PHY_TERANETICS
 410 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 411 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 412 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 413 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 414 #define FM1_10GEC1_PHY_ADDR     0x0
 415 #define FM1_10GEC2_PHY_ADDR     0x1
 416 #define FM2_10GEC1_PHY_ADDR     0x2
 417 #define FM2_10GEC2_PHY_ADDR     0x3
 418 #endif
 419
 420
 421 /* SATA */
 422 #ifdef CONFIG_FSL_SATA_V2
 423 #define CONFIG_LIBATA
 424 #define CONFIG_FSL_SATA
 425
 426 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 427 #define CONFIG_SATA1
 428 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 429 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 430 #define CONFIG_SATA2
 431 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 432 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 433
 434 #define CONFIG_LBA48
 435 #define CONFIG_CMD_SATA
 436 #define CONFIG_DOS_PARTITION
 437 #define CONFIG_CMD_EXT2
 438 #endif
 439
 440 #ifdef CONFIG_FMAN_ENET
 441 #define CONFIG_MII              /* MII PHY management */
 442 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 443 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 444 #endif
 445
 446 /*
 447 * USB
 448 */
 449 #define CONFIG_CMD_USB
 450 #define CONFIG_USB_STORAGE
 451 #define CONFIG_USB_EHCI
 452 #define CONFIG_USB_EHCI_FSL
 453 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 454 #define CONFIG_CMD_EXT2
 455 #define CONFIG_HAS_FSL_DR_USB
 456
 457 #define CONFIG_MMC
 458
 459 #ifdef CONFIG_MMC
 460 #define CONFIG_FSL_ESDHC
 461 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 462 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 463 #define CONFIG_CMD_MMC
 464 #define CONFIG_GENERIC_MMC
 465 #define CONFIG_CMD_EXT2
 466 #define CONFIG_CMD_FAT
 467 #define CONFIG_DOS_PARTITION
 468 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 469 #endif
 470
 471 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 472
 473 #define __USB_PHY_TYPE  utmi
 474
 475 /*
 476  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 477  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 478  * interleaving. It can be cacheline, page, bank, superbank.
 479  * See doc/README.fsl-ddr for details.
 480  */
 481 #ifdef CONFIG_PPC_T4240
 482 #define CTRL_INTLV_PREFERED 3way_4KB
 483 #else
 484 #define CTRL_INTLV_PREFERED cacheline
 485 #endif
 486
 487 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 488         "hwconfig=fsl_ddr:"                                     \
 489         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 490         "bank_intlv=auto;"                                      \
 491         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 492         "netdev=eth0\0"                                         \
 493         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 494         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 495         "tftpflash=tftpboot $loadaddr $uboot && "               \
 496         "protect off $ubootaddr +$filesize && "                 \
 497         "erase $ubootaddr +$filesize && "                       \
 498         "cp.b $loadaddr $ubootaddr $filesize && "               \
 499         "protect on $ubootaddr +$filesize && "                  \
 500         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 501         "consoledev=ttyS0\0"                                    \
 502         "ramdiskaddr=2000000\0"                                 \
 503         "ramdiskfile=t4240qds/ramdisk.uboot\0"                  \
 504         "fdtaddr=c00000\0"                                      \
 505         "fdtfile=t4240qds/t4240qds.dtb\0"                               \
 506         "bdev=sda3\0"                                           \
 507         "c=ffe\0"
 508
 509 #define CONFIG_HVBOOT                           \
 510         "setenv bootargs config-addr=0x60000000; "      \
 511         "bootm 0x01000000 - 0x00f00000"
 512
 513 #define CONFIG_ALU                              \
 514         "setenv bootargs root=/dev/$bdev rw "           \
 515         "console=$consoledev,$baudrate $othbootargs;"   \
 516         "cpu 1 release 0x01000000 - - -;"               \
 517         "cpu 2 release 0x01000000 - - -;"               \
 518         "cpu 3 release 0x01000000 - - -;"               \
 519         "cpu 4 release 0x01000000 - - -;"               \
 520         "cpu 5 release 0x01000000 - - -;"               \
 521         "cpu 6 release 0x01000000 - - -;"               \
 522         "cpu 7 release 0x01000000 - - -;"               \
 523         "go 0x01000000"
 524
 525 #define CONFIG_LINUX                            \
 526         "setenv bootargs root=/dev/ram rw "             \
 527         "console=$consoledev,$baudrate $othbootargs;"   \
 528         "setenv ramdiskaddr 0x02000000;"                \
 529         "setenv fdtaddr 0x00c00000;"                    \
 530         "setenv loadaddr 0x1000000;"                    \
 531         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 532
 533 #define CONFIG_HDBOOT                                   \
 534         "setenv bootargs root=/dev/$bdev rw "           \
 535         "console=$consoledev,$baudrate $othbootargs;"   \
 536         "tftp $loadaddr $bootfile;"                     \
 537         "tftp $fdtaddr $fdtfile;"                       \
 538         "bootm $loadaddr - $fdtaddr"
 539
 540 #define CONFIG_NFSBOOTCOMMAND                   \
 541         "setenv bootargs root=/dev/nfs rw "     \
 542         "nfsroot=$serverip:$rootpath "          \
 543         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 544         "console=$consoledev,$baudrate $othbootargs;"   \
 545         "tftp $loadaddr $bootfile;"             \
 546         "tftp $fdtaddr $fdtfile;"               \
 547         "bootm $loadaddr - $fdtaddr"
 548
 549 #define CONFIG_RAMBOOTCOMMAND                           \
 550         "setenv bootargs root=/dev/ram rw "             \
 551         "console=$consoledev,$baudrate $othbootargs;"   \
 552         "tftp $ramdiskaddr $ramdiskfile;"               \
 553         "tftp $loadaddr $bootfile;"                     \
 554         "tftp $fdtaddr $fdtfile;"                       \
 555         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 556
 557 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 558
 559 #include <asm/fsl_secure_boot.h>
 560
 561 #endif  /* __CONFIG_H */