include/configs/T4240QDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T4240 QDS board configuration file
   8  */
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_FSL_SATA_V2
  13 #define CONFIG_PCIE4
  14
  15 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
  19 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
  20 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  21 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  22 #else
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  25 #define CONFIG_SPL_PAD_TO               0x40000
  26 #define CONFIG_SPL_MAX_SIZE             0x28000
  27 #define RESET_VECTOR_OFFSET             0x27FFC
  28 #define BOOT_PAGE_OFFSET                0x27000
  29
  30 #ifdef  CONFIG_NAND
  31 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  32 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  33 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  34 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  35 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
  37 #define CONFIG_SPL_NAND_BOOT
  38 #endif
  39
  40 #ifdef  CONFIG_SDCARD
  41 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  42 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  43 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  44 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  45 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  46 #ifndef CONFIG_SPL_BUILD
  47 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  48 #endif
  49 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
  51 #define CONFIG_SPL_MMC_BOOT
  52 #endif
  53
  54 #ifdef CONFIG_SPL_BUILD
  55 #define CONFIG_SPL_SKIP_RELOCATE
  56 #define CONFIG_SPL_COMMON_INIT_DDR
  57 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  58 #endif
  59
  60 #endif
  61 #endif /* CONFIG_RAMBOOT_PBL */
  62
  63 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  64 /* Set 1M boot space */
  65 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  66 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  67                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  68 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  69 #endif
  70
  71 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  72 #define CONFIG_DDR_ECC
  73
  74 #include "t4qds.h"
  75
  76 #if defined(CONFIG_SPIFLASH)
  77 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  78 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  79 #define CONFIG_ENV_SECT_SIZE            0x10000
  80 #elif defined(CONFIG_SDCARD)
  81 #define CONFIG_SYS_MMC_ENV_DEV          0
  82 #define CONFIG_ENV_SIZE                 0x2000
  83 #define CONFIG_ENV_OFFSET               (512 * 0x800)
  84 #elif defined(CONFIG_NAND)
  85 #define CONFIG_ENV_SIZE                 0x2000
  86 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  87 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  88 #define CONFIG_ENV_ADDR         0xffe20000
  89 #define CONFIG_ENV_SIZE         0x2000
  90 #elif defined(CONFIG_ENV_IS_NOWHERE)
  91 #define CONFIG_ENV_SIZE         0x2000
  92 #else
  93 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  94 #define CONFIG_ENV_SIZE         0x2000
  95 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  96 #endif
  97
  98 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
  99 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 100
 101 #ifndef __ASSEMBLY__
 102 unsigned long get_board_sys_clk(void);
 103 unsigned long get_board_ddr_clk(void);
 104 #endif
 105
 106 /* EEPROM */
 107 #define CONFIG_ID_EEPROM
 108 #define CONFIG_SYS_I2C_EEPROM_NXID
 109 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 110 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 111 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 112
 113 /*
 114  * DDR Setup
 115  */
 116 #define CONFIG_SYS_SPD_BUS_NUM  0
 117 #define SPD_EEPROM_ADDRESS1     0x51
 118 #define SPD_EEPROM_ADDRESS2     0x52
 119 #define SPD_EEPROM_ADDRESS3     0x53
 120 #define SPD_EEPROM_ADDRESS4     0x54
 121 #define SPD_EEPROM_ADDRESS5     0x55
 122 #define SPD_EEPROM_ADDRESS6     0x56
 123 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 124 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 125
 126 /*
 127  * IFC Definitions
 128  */
 129 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 130 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 131                                 + 0x8000000) | \
 132                                 CSPR_PORT_SIZE_16 | \
 133                                 CSPR_MSEL_NOR | \
 134                                 CSPR_V)
 135 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 136 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 137                                 CSPR_PORT_SIZE_16 | \
 138                                 CSPR_MSEL_NOR | \
 139                                 CSPR_V)
 140 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 141 /* NOR Flash Timing Params */
 142 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 143
 144 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 145                                 FTIM0_NOR_TEADC(0x5) | \
 146                                 FTIM0_NOR_TEAHC(0x5))
 147 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 148                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 149                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 150 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 151                                 FTIM2_NOR_TCH(0x4) | \
 152                                 FTIM2_NOR_TWPH(0x0E) | \
 153                                 FTIM2_NOR_TWP(0x1c))
 154 #define CONFIG_SYS_NOR_FTIM3    0x0
 155
 156 #define CONFIG_SYS_FLASH_QUIET_TEST
 157 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 158
 159 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 160 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 161 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 162 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 163
 164 #define CONFIG_SYS_FLASH_EMPTY_INFO
 165 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 166                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 167
 168 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 169 #define QIXIS_BASE                      0xffdf0000
 170 #define QIXIS_LBMAP_SWITCH              6
 171 #define QIXIS_LBMAP_MASK                0x0f
 172 #define QIXIS_LBMAP_SHIFT               0
 173 #define QIXIS_LBMAP_DFLTBANK            0x00
 174 #define QIXIS_LBMAP_ALTBANK             0x04
 175 #define QIXIS_RST_CTL_RESET             0x83
 176 #define QIXIS_RST_FORCE_MEM             0x1
 177 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 178 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 179 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 180 #define QIXIS_BRDCFG5                   0x55
 181 #define QIXIS_MUX_SDHC                  2
 182 #define QIXIS_MUX_SDHC_WIDTH8           1
 183 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 184
 185 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 186 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 187                                 | CSPR_PORT_SIZE_8 \
 188                                 | CSPR_MSEL_GPCM \
 189                                 | CSPR_V)
 190 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 191 #define CONFIG_SYS_CSOR3        0x0
 192 /* QIXIS Timing parameters for IFC CS3 */
 193 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 194                                         FTIM0_GPCM_TEADC(0x0e) | \
 195                                         FTIM0_GPCM_TEAHC(0x0e))
 196 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 197                                         FTIM1_GPCM_TRAD(0x3f))
 198 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 199                                         FTIM2_GPCM_TCH(0x8) | \
 200                                         FTIM2_GPCM_TWP(0x1f))
 201 #define CONFIG_SYS_CS3_FTIM3            0x0
 202
 203 /* NAND Flash on IFC */
 204 #define CONFIG_NAND_FSL_IFC
 205 #define CONFIG_SYS_NAND_BASE            0xff800000
 206 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 207
 208 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 209 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 210                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 211                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 212                                 | CSPR_V)
 213 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 214
 215 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 216                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 217                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 218                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 219                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 220                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 221                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 222
 223 #define CONFIG_SYS_NAND_ONFI_DETECTION
 224
 225 /* ONFI NAND Flash mode0 Timing Params */
 226 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 227                                         FTIM0_NAND_TWP(0x18)   | \
 228                                         FTIM0_NAND_TWCHT(0x07) | \
 229                                         FTIM0_NAND_TWH(0x0a))
 230 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 231                                         FTIM1_NAND_TWBE(0x39)  | \
 232                                         FTIM1_NAND_TRR(0x0e)   | \
 233                                         FTIM1_NAND_TRP(0x18))
 234 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 235                                         FTIM2_NAND_TREH(0x0a) | \
 236                                         FTIM2_NAND_TWHRE(0x1e))
 237 #define CONFIG_SYS_NAND_FTIM3           0x0
 238
 239 #define CONFIG_SYS_NAND_DDR_LAW         11
 240
 241 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 242 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 243
 244 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 245 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 246 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 247
 248 #if defined(CONFIG_NAND)
 249 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 250 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 251 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 252 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 253 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 254 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 255 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 256 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 257 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 258 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 259 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 260 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 261 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 262 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 263 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 264 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 265 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 266 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 267 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 268 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 269 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 270 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 271 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 272 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 273 #else
 274 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 275 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 276 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 277 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 278 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 279 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 280 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 281 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 282 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 283 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 284 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 285 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 286 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 287 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 288 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 289 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 290 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 291 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 292 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 293 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 294 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 295 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 296 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 297 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 298 #endif
 299
 300 #if defined(CONFIG_RAMBOOT_PBL)
 301 #define CONFIG_SYS_RAMBOOT
 302 #endif
 303
 304 /* I2C */
 305 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 306 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 307 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 308 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 309
 310 #define I2C_MUX_CH_DEFAULT      0x8
 311 #define I2C_MUX_CH_VOL_MONITOR  0xa
 312 #define I2C_MUX_CH_VSC3316_FS   0xc
 313 #define I2C_MUX_CH_VSC3316_BS   0xd
 314
 315 /* Voltage monitor on channel 2*/
 316 #define I2C_VOL_MONITOR_ADDR            0x40
 317 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 318 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 319 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 320
 321 /* VSC Crossbar switches */
 322 #define CONFIG_VSC_CROSSBAR
 323 #define VSC3316_FSM_TX_ADDR     0x70
 324 #define VSC3316_FSM_RX_ADDR     0x71
 325
 326 /*
 327  * RapidIO
 328  */
 329
 330 /*
 331  * for slave u-boot IMAGE instored in master memory space,
 332  * PHYS must be aligned based on the SIZE
 333  */
 334 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 335 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 336 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 337 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 338 /*
 339  * for slave UCODE and ENV instored in master memory space,
 340  * PHYS must be aligned based on the SIZE
 341  */
 342 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 343 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 344 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 345
 346 /* slave core release by master*/
 347 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 348 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 349
 350 /*
 351  * SRIO_PCIE_BOOT - SLAVE
 352  */
 353 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 354 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 355 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 356                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 357 #endif
 358 /*
 359  * eSPI - Enhanced SPI
 360  */
 361
 362 /* Qman/Bman */
 363 #ifndef CONFIG_NOBQFMAN
 364 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 365 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 366 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 367 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 368 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 369 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 370 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 371 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 372 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 373                                         CONFIG_SYS_BMAN_CENA_SIZE)
 374 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 375 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 376 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 377 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 378 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 379 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 380 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 381 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 382 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 383 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 384 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 385                                         CONFIG_SYS_QMAN_CENA_SIZE)
 386 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 387 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 388
 389 #define CONFIG_SYS_DPAA_FMAN
 390 #define CONFIG_SYS_DPAA_PME
 391 #define CONFIG_SYS_PMAN
 392 #define CONFIG_SYS_DPAA_DCE
 393 #define CONFIG_SYS_DPAA_RMAN
 394 #define CONFIG_SYS_INTERLAKEN
 395
 396 /* Default address of microcode for the Linux Fman driver */
 397 #if defined(CONFIG_SPIFLASH)
 398 /*
 399  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 400  * env, so we got 0x110000.
 401  */
 402 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 403 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 404 #elif defined(CONFIG_SDCARD)
 405 /*
 406  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 407  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 408  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 409  */
 410 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 411 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 412 #elif defined(CONFIG_NAND)
 413 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 414 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 415 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 416 /*
 417  * Slave has no ucode locally, it can fetch this from remote. When implementing
 418  * in two corenet boards, slave's ucode could be stored in master's memory
 419  * space, the address can be mapped from slave TLB->slave LAW->
 420  * slave SRIO or PCIE outbound window->master inbound window->
 421  * master LAW->the ucode address in master's memory space.
 422  */
 423 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 424 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 425 #else
 426 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 427 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 428 #endif
 429 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 430 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 431 #endif /* CONFIG_NOBQFMAN */
 432
 433 #ifdef CONFIG_SYS_DPAA_FMAN
 434 #define CONFIG_FMAN_ENET
 435 #define CONFIG_PHYLIB_10G
 436 #define CONFIG_PHY_VITESSE
 437 #define CONFIG_PHY_TERANETICS
 438 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 439 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 440 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 441 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 442 #define FM1_10GEC1_PHY_ADDR     0x0
 443 #define FM1_10GEC2_PHY_ADDR     0x1
 444 #define FM2_10GEC1_PHY_ADDR     0x2
 445 #define FM2_10GEC2_PHY_ADDR     0x3
 446 #endif
 447
 448 /* SATA */
 449 #ifdef CONFIG_FSL_SATA_V2
 450 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 451 #define CONFIG_SATA1
 452 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 453 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 454 #define CONFIG_SATA2
 455 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 456 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 457
 458 #define CONFIG_LBA48
 459 #endif
 460
 461 #ifdef CONFIG_FMAN_ENET
 462 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 463 #endif
 464
 465 /*
 466 * USB
 467 */
 468 #define CONFIG_USB_EHCI_FSL
 469 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 470 #define CONFIG_HAS_FSL_DR_USB
 471
 472 #ifdef CONFIG_MMC
 473 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 474 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 475 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 476 #define CONFIG_ESDHC_DETECT_QUIRK \
 477         (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
 478         IS_SVR_REV(get_svr(), 1, 0))
 479 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
 480         (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 481 #endif
 482
 483
 484 #define __USB_PHY_TYPE  utmi
 485
 486 /*
 487  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 488  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 489  * interleaving. It can be cacheline, page, bank, superbank.
 490  * See doc/README.fsl-ddr for details.
 491  */
 492 #ifdef CONFIG_ARCH_T4240
 493 #define CTRL_INTLV_PREFERED 3way_4KB
 494 #else
 495 #define CTRL_INTLV_PREFERED cacheline
 496 #endif
 497
 498 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 499         "hwconfig=fsl_ddr:"                                     \
 500         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 501         "bank_intlv=auto;"                                      \
 502         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 503         "netdev=eth0\0"                                         \
 504         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 505         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 506         "tftpflash=tftpboot $loadaddr $uboot && "               \
 507         "protect off $ubootaddr +$filesize && "                 \
 508         "erase $ubootaddr +$filesize && "                       \
 509         "cp.b $loadaddr $ubootaddr $filesize && "               \
 510         "protect on $ubootaddr +$filesize && "                  \
 511         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 512         "consoledev=ttyS0\0"                                    \
 513         "ramdiskaddr=2000000\0"                                 \
 514         "ramdiskfile=t4240qds/ramdisk.uboot\0"                  \
 515         "fdtaddr=1e00000\0"                                     \
 516         "fdtfile=t4240qds/t4240qds.dtb\0"                               \
 517         "bdev=sda3\0"
 518
 519 #define CONFIG_HVBOOT                           \
 520         "setenv bootargs config-addr=0x60000000; "      \
 521         "bootm 0x01000000 - 0x00f00000"
 522
 523 #define CONFIG_ALU                              \
 524         "setenv bootargs root=/dev/$bdev rw "           \
 525         "console=$consoledev,$baudrate $othbootargs;"   \
 526         "cpu 1 release 0x01000000 - - -;"               \
 527         "cpu 2 release 0x01000000 - - -;"               \
 528         "cpu 3 release 0x01000000 - - -;"               \
 529         "cpu 4 release 0x01000000 - - -;"               \
 530         "cpu 5 release 0x01000000 - - -;"               \
 531         "cpu 6 release 0x01000000 - - -;"               \
 532         "cpu 7 release 0x01000000 - - -;"               \
 533         "go 0x01000000"
 534
 535 #define CONFIG_LINUX                            \
 536         "setenv bootargs root=/dev/ram rw "             \
 537         "console=$consoledev,$baudrate $othbootargs;"   \
 538         "setenv ramdiskaddr 0x02000000;"                \
 539         "setenv fdtaddr 0x00c00000;"                    \
 540         "setenv loadaddr 0x1000000;"                    \
 541         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 542
 543 #define CONFIG_HDBOOT                                   \
 544         "setenv bootargs root=/dev/$bdev rw "           \
 545         "console=$consoledev,$baudrate $othbootargs;"   \
 546         "tftp $loadaddr $bootfile;"                     \
 547         "tftp $fdtaddr $fdtfile;"                       \
 548         "bootm $loadaddr - $fdtaddr"
 549
 550 #define CONFIG_NFSBOOTCOMMAND                   \
 551         "setenv bootargs root=/dev/nfs rw "     \
 552         "nfsroot=$serverip:$rootpath "          \
 553         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 554         "console=$consoledev,$baudrate $othbootargs;"   \
 555         "tftp $loadaddr $bootfile;"             \
 556         "tftp $fdtaddr $fdtfile;"               \
 557         "bootm $loadaddr - $fdtaddr"
 558
 559 #define CONFIG_RAMBOOTCOMMAND                           \
 560         "setenv bootargs root=/dev/ram rw "             \
 561         "console=$consoledev,$baudrate $othbootargs;"   \
 562         "tftp $ramdiskaddr $ramdiskfile;"               \
 563         "tftp $loadaddr $bootfile;"                     \
 564         "tftp $fdtaddr $fdtfile;"                       \
 565         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 566
 567 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 568
 569 #include <asm/fsl_secure_boot.h>
 570
 571 #endif  /* __CONFIG_H */