2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T4240 QDS board configuration file
13 #define CONFIG_T4240QDS
15 #define CONFIG_FSL_SATA_V2
17 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
21 #ifdef CONFIG_RAMBOOT_PBL
22 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
23 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
24 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
28 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
29 #define CONFIG_SPL_ENV_SUPPORT
30 #define CONFIG_SPL_SERIAL_SUPPORT
31 #define CONFIG_SPL_FLUSH_IMAGE
32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
33 #define CONFIG_SPL_LIBGENERIC_SUPPORT
34 #define CONFIG_SPL_LIBCOMMON_SUPPORT
35 #define CONFIG_SPL_I2C_SUPPORT
36 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
37 #define CONFIG_FSL_LAW /* Use common FSL init code */
38 #define CONFIG_SYS_TEXT_BASE 0x00201000
39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
40 #define CONFIG_SPL_PAD_TO 0x40000
41 #define CONFIG_SPL_MAX_SIZE 0x28000
42 #define RESET_VECTOR_OFFSET 0x27FFC
43 #define BOOT_PAGE_OFFSET 0x27000
46 #define CONFIG_SPL_NAND_SUPPORT
47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
48 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
49 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
50 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
51 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
52 #define CONFIG_SPL_NAND_BOOT
56 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
57 #define CONFIG_SPL_MMC_SUPPORT
58 #define CONFIG_SPL_MMC_MINIMAL
59 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
60 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
61 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
62 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
63 #ifndef CONFIG_SPL_BUILD
64 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
66 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
67 #define CONFIG_SPL_MMC_BOOT
70 #ifdef CONFIG_SPL_BUILD
71 #define CONFIG_SPL_SKIP_RELOCATE
72 #define CONFIG_SPL_COMMON_INIT_DDR
73 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
74 #define CONFIG_SYS_NO_FLASH
78 #endif /* CONFIG_RAMBOOT_PBL */
80 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
81 /* Set 1M boot space */
82 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
83 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
84 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
85 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
86 #define CONFIG_SYS_NO_FLASH
89 #define CONFIG_SRIO_PCIE_BOOT_MASTER
90 #define CONFIG_DDR_ECC
94 #ifdef CONFIG_SYS_NO_FLASH
95 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
96 #define CONFIG_ENV_IS_NOWHERE
99 #define CONFIG_FLASH_CFI_DRIVER
100 #define CONFIG_SYS_FLASH_CFI
101 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
104 #if defined(CONFIG_SPIFLASH)
105 #define CONFIG_SYS_EXTRA_ENV_RELOC
106 #define CONFIG_ENV_IS_IN_SPI_FLASH
107 #define CONFIG_ENV_SPI_BUS 0
108 #define CONFIG_ENV_SPI_CS 0
109 #define CONFIG_ENV_SPI_MAX_HZ 10000000
110 #define CONFIG_ENV_SPI_MODE 0
111 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
112 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
113 #define CONFIG_ENV_SECT_SIZE 0x10000
114 #elif defined(CONFIG_SDCARD)
115 #define CONFIG_SYS_EXTRA_ENV_RELOC
116 #define CONFIG_ENV_IS_IN_MMC
117 #define CONFIG_SYS_MMC_ENV_DEV 0
118 #define CONFIG_ENV_SIZE 0x2000
119 #define CONFIG_ENV_OFFSET (512 * 0x800)
120 #elif defined(CONFIG_NAND)
121 #define CONFIG_SYS_EXTRA_ENV_RELOC
122 #define CONFIG_ENV_IS_IN_NAND
123 #define CONFIG_ENV_SIZE 0x2000
124 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
125 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
126 #define CONFIG_ENV_IS_IN_REMOTE
127 #define CONFIG_ENV_ADDR 0xffe20000
128 #define CONFIG_ENV_SIZE 0x2000
129 #elif defined(CONFIG_ENV_IS_NOWHERE)
130 #define CONFIG_ENV_SIZE 0x2000
132 #define CONFIG_ENV_IS_IN_FLASH
133 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
134 #define CONFIG_ENV_SIZE 0x2000
135 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
138 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
139 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
142 unsigned long get_board_sys_clk(void);
143 unsigned long get_board_ddr_clk(void);
147 #define CONFIG_ID_EEPROM
148 #define CONFIG_SYS_I2C_EEPROM_NXID
149 #define CONFIG_SYS_EEPROM_BUS_NUM 0
150 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
151 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
156 #define CONFIG_SYS_SPD_BUS_NUM 0
157 #define SPD_EEPROM_ADDRESS1 0x51
158 #define SPD_EEPROM_ADDRESS2 0x52
159 #define SPD_EEPROM_ADDRESS3 0x53
160 #define SPD_EEPROM_ADDRESS4 0x54
161 #define SPD_EEPROM_ADDRESS5 0x55
162 #define SPD_EEPROM_ADDRESS6 0x56
163 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
164 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
169 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
170 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
172 CSPR_PORT_SIZE_16 | \
175 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
176 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
177 CSPR_PORT_SIZE_16 | \
180 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
181 /* NOR Flash Timing Params */
182 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
184 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
185 FTIM0_NOR_TEADC(0x5) | \
186 FTIM0_NOR_TEAHC(0x5))
187 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
188 FTIM1_NOR_TRAD_NOR(0x1A) |\
189 FTIM1_NOR_TSEQRAD_NOR(0x13))
190 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
191 FTIM2_NOR_TCH(0x4) | \
192 FTIM2_NOR_TWPH(0x0E) | \
194 #define CONFIG_SYS_NOR_FTIM3 0x0
196 #define CONFIG_SYS_FLASH_QUIET_TEST
197 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
199 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
200 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
201 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
204 #define CONFIG_SYS_FLASH_EMPTY_INFO
205 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
206 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
208 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
209 #define QIXIS_BASE 0xffdf0000
210 #define QIXIS_LBMAP_SWITCH 6
211 #define QIXIS_LBMAP_MASK 0x0f
212 #define QIXIS_LBMAP_SHIFT 0
213 #define QIXIS_LBMAP_DFLTBANK 0x00
214 #define QIXIS_LBMAP_ALTBANK 0x04
215 #define QIXIS_RST_CTL_RESET 0x83
216 #define QIXIS_RST_FORCE_MEM 0x1
217 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
218 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
219 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
220 #define QIXIS_BRDCFG5 0x55
221 #define QIXIS_MUX_SDHC 2
222 #define QIXIS_MUX_SDHC_WIDTH8 1
223 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
225 #define CONFIG_SYS_CSPR3_EXT (0xf)
226 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
230 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
231 #define CONFIG_SYS_CSOR3 0x0
232 /* QIXIS Timing parameters for IFC CS3 */
233 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
234 FTIM0_GPCM_TEADC(0x0e) | \
235 FTIM0_GPCM_TEAHC(0x0e))
236 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
237 FTIM1_GPCM_TRAD(0x3f))
238 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
239 FTIM2_GPCM_TCH(0x8) | \
240 FTIM2_GPCM_TWP(0x1f))
241 #define CONFIG_SYS_CS3_FTIM3 0x0
243 /* NAND Flash on IFC */
244 #define CONFIG_NAND_FSL_IFC
245 #define CONFIG_SYS_NAND_BASE 0xff800000
246 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
248 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
249 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
250 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
251 | CSPR_MSEL_NAND /* MSEL = NAND */ \
253 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
255 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
256 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
257 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
258 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
259 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
260 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
261 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
263 #define CONFIG_SYS_NAND_ONFI_DETECTION
265 /* ONFI NAND Flash mode0 Timing Params */
266 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
267 FTIM0_NAND_TWP(0x18) | \
268 FTIM0_NAND_TWCHT(0x07) | \
269 FTIM0_NAND_TWH(0x0a))
270 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
271 FTIM1_NAND_TWBE(0x39) | \
272 FTIM1_NAND_TRR(0x0e) | \
273 FTIM1_NAND_TRP(0x18))
274 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
275 FTIM2_NAND_TREH(0x0a) | \
276 FTIM2_NAND_TWHRE(0x1e))
277 #define CONFIG_SYS_NAND_FTIM3 0x0
279 #define CONFIG_SYS_NAND_DDR_LAW 11
281 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
282 #define CONFIG_SYS_MAX_NAND_DEVICE 1
283 #define CONFIG_CMD_NAND
285 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
286 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
287 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
289 #if defined(CONFIG_NAND)
290 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
291 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
292 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
293 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
294 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
295 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
296 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
297 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
298 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
299 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
300 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
301 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
302 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
303 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
304 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
305 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
306 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
307 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
308 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
309 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
310 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
311 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
312 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
313 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
315 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
316 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
317 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
318 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
319 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
320 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
321 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
322 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
323 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
324 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
325 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
326 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
327 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
328 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
329 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
330 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
331 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
332 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
333 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
334 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
335 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
336 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
337 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
338 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
341 #if defined(CONFIG_RAMBOOT_PBL)
342 #define CONFIG_SYS_RAMBOOT
346 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
347 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
348 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
349 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
351 #define I2C_MUX_CH_DEFAULT 0x8
352 #define I2C_MUX_CH_VOL_MONITOR 0xa
353 #define I2C_MUX_CH_VSC3316_FS 0xc
354 #define I2C_MUX_CH_VSC3316_BS 0xd
356 /* Voltage monitor on channel 2*/
357 #define I2C_VOL_MONITOR_ADDR 0x40
358 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
359 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
360 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
362 /* VSC Crossbar switches */
363 #define CONFIG_VSC_CROSSBAR
364 #define VSC3316_FSM_TX_ADDR 0x70
365 #define VSC3316_FSM_RX_ADDR 0x71
372 * for slave u-boot IMAGE instored in master memory space,
373 * PHYS must be aligned based on the SIZE
375 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
376 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
377 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
378 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
380 * for slave UCODE and ENV instored in master memory space,
381 * PHYS must be aligned based on the SIZE
383 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
384 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
385 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
387 /* slave core release by master*/
388 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
389 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
392 * SRIO_PCIE_BOOT - SLAVE
394 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
395 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
396 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
397 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
400 * eSPI - Enhanced SPI
402 #define CONFIG_SF_DEFAULT_SPEED 10000000
403 #define CONFIG_SF_DEFAULT_MODE 0
406 #ifndef CONFIG_NOBQFMAN
407 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
408 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
409 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
410 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
411 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
412 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
413 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
414 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
415 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
416 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
417 CONFIG_SYS_BMAN_CENA_SIZE)
418 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
419 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
420 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
421 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
422 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
423 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
424 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
425 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
426 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
427 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
428 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
429 CONFIG_SYS_QMAN_CENA_SIZE)
430 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
431 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
433 #define CONFIG_SYS_DPAA_FMAN
434 #define CONFIG_SYS_DPAA_PME
435 #define CONFIG_SYS_PMAN
436 #define CONFIG_SYS_DPAA_DCE
437 #define CONFIG_SYS_DPAA_RMAN
438 #define CONFIG_SYS_INTERLAKEN
440 /* Default address of microcode for the Linux Fman driver */
441 #if defined(CONFIG_SPIFLASH)
443 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
444 * env, so we got 0x110000.
446 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
447 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
448 #elif defined(CONFIG_SDCARD)
450 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
451 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
452 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
454 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
455 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
456 #elif defined(CONFIG_NAND)
457 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
458 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
459 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
461 * Slave has no ucode locally, it can fetch this from remote. When implementing
462 * in two corenet boards, slave's ucode could be stored in master's memory
463 * space, the address can be mapped from slave TLB->slave LAW->
464 * slave SRIO or PCIE outbound window->master inbound window->
465 * master LAW->the ucode address in master's memory space.
467 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
468 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
470 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
471 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
473 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
474 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
475 #endif /* CONFIG_NOBQFMAN */
477 #ifdef CONFIG_SYS_DPAA_FMAN
478 #define CONFIG_FMAN_ENET
479 #define CONFIG_PHYLIB_10G
480 #define CONFIG_PHY_VITESSE
481 #define CONFIG_PHY_TERANETICS
482 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
483 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
484 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
485 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
486 #define FM1_10GEC1_PHY_ADDR 0x0
487 #define FM1_10GEC2_PHY_ADDR 0x1
488 #define FM2_10GEC1_PHY_ADDR 0x2
489 #define FM2_10GEC2_PHY_ADDR 0x3
493 #ifdef CONFIG_FSL_SATA_V2
494 #define CONFIG_LIBATA
495 #define CONFIG_FSL_SATA
497 #define CONFIG_SYS_SATA_MAX_DEVICE 2
499 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
500 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
502 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
503 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
506 #define CONFIG_CMD_SATA
507 #define CONFIG_DOS_PARTITION
510 #ifdef CONFIG_FMAN_ENET
511 #define CONFIG_MII /* MII PHY management */
512 #define CONFIG_ETHPRIME "FM1@DTSEC1"
513 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
516 /* Hash command with SHA acceleration supported in hardware */
517 #ifdef CONFIG_FSL_CAAM
518 #define CONFIG_CMD_HASH
519 #define CONFIG_SHA_HW_ACCEL
525 #define CONFIG_USB_STORAGE
526 #define CONFIG_USB_EHCI
527 #define CONFIG_USB_EHCI_FSL
528 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
529 #define CONFIG_HAS_FSL_DR_USB
534 #define CONFIG_FSL_ESDHC
535 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
536 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
537 #define CONFIG_GENERIC_MMC
538 #define CONFIG_DOS_PARTITION
539 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
540 #define CONFIG_ESDHC_DETECT_QUIRK \
541 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
542 IS_SVR_REV(get_svr(), 1, 0))
543 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
544 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
548 #define __USB_PHY_TYPE utmi
551 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
552 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
553 * interleaving. It can be cacheline, page, bank, superbank.
554 * See doc/README.fsl-ddr for details.
556 #ifdef CONFIG_PPC_T4240
557 #define CTRL_INTLV_PREFERED 3way_4KB
559 #define CTRL_INTLV_PREFERED cacheline
562 #define CONFIG_EXTRA_ENV_SETTINGS \
563 "hwconfig=fsl_ddr:" \
564 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
566 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
568 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
569 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
570 "tftpflash=tftpboot $loadaddr $uboot && " \
571 "protect off $ubootaddr +$filesize && " \
572 "erase $ubootaddr +$filesize && " \
573 "cp.b $loadaddr $ubootaddr $filesize && " \
574 "protect on $ubootaddr +$filesize && " \
575 "cmp.b $loadaddr $ubootaddr $filesize\0" \
576 "consoledev=ttyS0\0" \
577 "ramdiskaddr=2000000\0" \
578 "ramdiskfile=t4240qds/ramdisk.uboot\0" \
579 "fdtaddr=1e00000\0" \
580 "fdtfile=t4240qds/t4240qds.dtb\0" \
583 #define CONFIG_HVBOOT \
584 "setenv bootargs config-addr=0x60000000; " \
585 "bootm 0x01000000 - 0x00f00000"
588 "setenv bootargs root=/dev/$bdev rw " \
589 "console=$consoledev,$baudrate $othbootargs;" \
590 "cpu 1 release 0x01000000 - - -;" \
591 "cpu 2 release 0x01000000 - - -;" \
592 "cpu 3 release 0x01000000 - - -;" \
593 "cpu 4 release 0x01000000 - - -;" \
594 "cpu 5 release 0x01000000 - - -;" \
595 "cpu 6 release 0x01000000 - - -;" \
596 "cpu 7 release 0x01000000 - - -;" \
599 #define CONFIG_LINUX \
600 "setenv bootargs root=/dev/ram rw " \
601 "console=$consoledev,$baudrate $othbootargs;" \
602 "setenv ramdiskaddr 0x02000000;" \
603 "setenv fdtaddr 0x00c00000;" \
604 "setenv loadaddr 0x1000000;" \
605 "bootm $loadaddr $ramdiskaddr $fdtaddr"
607 #define CONFIG_HDBOOT \
608 "setenv bootargs root=/dev/$bdev rw " \
609 "console=$consoledev,$baudrate $othbootargs;" \
610 "tftp $loadaddr $bootfile;" \
611 "tftp $fdtaddr $fdtfile;" \
612 "bootm $loadaddr - $fdtaddr"
614 #define CONFIG_NFSBOOTCOMMAND \
615 "setenv bootargs root=/dev/nfs rw " \
616 "nfsroot=$serverip:$rootpath " \
617 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
618 "console=$consoledev,$baudrate $othbootargs;" \
619 "tftp $loadaddr $bootfile;" \
620 "tftp $fdtaddr $fdtfile;" \
621 "bootm $loadaddr - $fdtaddr"
623 #define CONFIG_RAMBOOTCOMMAND \
624 "setenv bootargs root=/dev/ram rw " \
625 "console=$consoledev,$baudrate $othbootargs;" \
626 "tftp $ramdiskaddr $ramdiskfile;" \
627 "tftp $loadaddr $bootfile;" \
628 "tftp $fdtaddr $fdtfile;" \
629 "bootm $loadaddr $ramdiskaddr $fdtaddr"
631 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
633 #include <asm/fsl_secure_boot.h>
635 #endif /* __CONFIG_H */