1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
7 * T4240 QDS board configuration file
12 #define CONFIG_FSL_SATA_V2
15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
19 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
20 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
21 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
23 #define CONFIG_SPL_FLUSH_IMAGE
24 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
25 #define CONFIG_SPL_PAD_TO 0x40000
26 #define CONFIG_SPL_MAX_SIZE 0x28000
27 #define RESET_VECTOR_OFFSET 0x27FFC
28 #define BOOT_PAGE_OFFSET 0x27000
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
32 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
33 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
34 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
35 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
37 #define CONFIG_SPL_NAND_BOOT
41 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
42 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
43 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
44 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
45 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
46 #ifndef CONFIG_SPL_BUILD
47 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
51 #define CONFIG_SPL_MMC_BOOT
54 #ifdef CONFIG_SPL_BUILD
55 #define CONFIG_SPL_SKIP_RELOCATE
56 #define CONFIG_SPL_COMMON_INIT_DDR
57 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
61 #endif /* CONFIG_RAMBOOT_PBL */
63 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
64 /* Set 1M boot space */
65 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
66 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
67 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
68 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
71 #define CONFIG_SRIO_PCIE_BOOT_MASTER
72 #define CONFIG_DDR_ECC
76 #ifndef CONFIG_MTD_NOR_FLASH
78 #define CONFIG_FLASH_CFI_DRIVER
79 #define CONFIG_SYS_FLASH_CFI
80 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
83 #if defined(CONFIG_SPIFLASH)
84 #define CONFIG_ENV_SPI_BUS 0
85 #define CONFIG_ENV_SPI_CS 0
86 #define CONFIG_ENV_SPI_MAX_HZ 10000000
87 #define CONFIG_ENV_SPI_MODE 0
88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
90 #define CONFIG_ENV_SECT_SIZE 0x10000
91 #elif defined(CONFIG_SDCARD)
92 #define CONFIG_SYS_MMC_ENV_DEV 0
93 #define CONFIG_ENV_SIZE 0x2000
94 #define CONFIG_ENV_OFFSET (512 * 0x800)
95 #elif defined(CONFIG_NAND)
96 #define CONFIG_ENV_SIZE 0x2000
97 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
98 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
99 #define CONFIG_ENV_ADDR 0xffe20000
100 #define CONFIG_ENV_SIZE 0x2000
101 #elif defined(CONFIG_ENV_IS_NOWHERE)
102 #define CONFIG_ENV_SIZE 0x2000
104 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
105 #define CONFIG_ENV_SIZE 0x2000
106 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
109 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
110 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
113 unsigned long get_board_sys_clk(void);
114 unsigned long get_board_ddr_clk(void);
118 #define CONFIG_ID_EEPROM
119 #define CONFIG_SYS_I2C_EEPROM_NXID
120 #define CONFIG_SYS_EEPROM_BUS_NUM 0
121 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
122 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
127 #define CONFIG_SYS_SPD_BUS_NUM 0
128 #define SPD_EEPROM_ADDRESS1 0x51
129 #define SPD_EEPROM_ADDRESS2 0x52
130 #define SPD_EEPROM_ADDRESS3 0x53
131 #define SPD_EEPROM_ADDRESS4 0x54
132 #define SPD_EEPROM_ADDRESS5 0x55
133 #define SPD_EEPROM_ADDRESS6 0x56
134 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
135 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
140 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
141 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
143 CSPR_PORT_SIZE_16 | \
146 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
147 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
148 CSPR_PORT_SIZE_16 | \
151 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
152 /* NOR Flash Timing Params */
153 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
155 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
156 FTIM0_NOR_TEADC(0x5) | \
157 FTIM0_NOR_TEAHC(0x5))
158 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
159 FTIM1_NOR_TRAD_NOR(0x1A) |\
160 FTIM1_NOR_TSEQRAD_NOR(0x13))
161 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
162 FTIM2_NOR_TCH(0x4) | \
163 FTIM2_NOR_TWPH(0x0E) | \
165 #define CONFIG_SYS_NOR_FTIM3 0x0
167 #define CONFIG_SYS_FLASH_QUIET_TEST
168 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
170 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
171 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
172 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
173 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
175 #define CONFIG_SYS_FLASH_EMPTY_INFO
176 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
177 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
179 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
180 #define QIXIS_BASE 0xffdf0000
181 #define QIXIS_LBMAP_SWITCH 6
182 #define QIXIS_LBMAP_MASK 0x0f
183 #define QIXIS_LBMAP_SHIFT 0
184 #define QIXIS_LBMAP_DFLTBANK 0x00
185 #define QIXIS_LBMAP_ALTBANK 0x04
186 #define QIXIS_RST_CTL_RESET 0x83
187 #define QIXIS_RST_FORCE_MEM 0x1
188 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
189 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
190 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
191 #define QIXIS_BRDCFG5 0x55
192 #define QIXIS_MUX_SDHC 2
193 #define QIXIS_MUX_SDHC_WIDTH8 1
194 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
196 #define CONFIG_SYS_CSPR3_EXT (0xf)
197 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
201 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
202 #define CONFIG_SYS_CSOR3 0x0
203 /* QIXIS Timing parameters for IFC CS3 */
204 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
205 FTIM0_GPCM_TEADC(0x0e) | \
206 FTIM0_GPCM_TEAHC(0x0e))
207 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
208 FTIM1_GPCM_TRAD(0x3f))
209 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
210 FTIM2_GPCM_TCH(0x8) | \
211 FTIM2_GPCM_TWP(0x1f))
212 #define CONFIG_SYS_CS3_FTIM3 0x0
214 /* NAND Flash on IFC */
215 #define CONFIG_NAND_FSL_IFC
216 #define CONFIG_SYS_NAND_BASE 0xff800000
217 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
219 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
220 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
221 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
222 | CSPR_MSEL_NAND /* MSEL = NAND */ \
224 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
226 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
227 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
228 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
229 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
230 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
231 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
232 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
234 #define CONFIG_SYS_NAND_ONFI_DETECTION
236 /* ONFI NAND Flash mode0 Timing Params */
237 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
238 FTIM0_NAND_TWP(0x18) | \
239 FTIM0_NAND_TWCHT(0x07) | \
240 FTIM0_NAND_TWH(0x0a))
241 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
242 FTIM1_NAND_TWBE(0x39) | \
243 FTIM1_NAND_TRR(0x0e) | \
244 FTIM1_NAND_TRP(0x18))
245 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
246 FTIM2_NAND_TREH(0x0a) | \
247 FTIM2_NAND_TWHRE(0x1e))
248 #define CONFIG_SYS_NAND_FTIM3 0x0
250 #define CONFIG_SYS_NAND_DDR_LAW 11
252 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
253 #define CONFIG_SYS_MAX_NAND_DEVICE 1
255 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
256 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
257 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
259 #if defined(CONFIG_NAND)
260 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
261 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
262 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
263 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
264 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
265 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
266 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
267 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
268 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
269 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
270 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
271 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
272 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
273 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
274 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
275 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
276 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
277 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
278 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
279 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
280 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
281 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
282 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
283 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
285 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
286 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
287 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
288 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
289 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
290 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
291 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
292 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
293 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
294 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
295 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
296 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
297 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
298 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
299 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
300 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
301 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
302 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
303 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
304 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
305 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
306 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
307 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
308 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
311 #if defined(CONFIG_RAMBOOT_PBL)
312 #define CONFIG_SYS_RAMBOOT
316 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
317 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
318 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
319 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
321 #define I2C_MUX_CH_DEFAULT 0x8
322 #define I2C_MUX_CH_VOL_MONITOR 0xa
323 #define I2C_MUX_CH_VSC3316_FS 0xc
324 #define I2C_MUX_CH_VSC3316_BS 0xd
326 /* Voltage monitor on channel 2*/
327 #define I2C_VOL_MONITOR_ADDR 0x40
328 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
329 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
330 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
332 /* VSC Crossbar switches */
333 #define CONFIG_VSC_CROSSBAR
334 #define VSC3316_FSM_TX_ADDR 0x70
335 #define VSC3316_FSM_RX_ADDR 0x71
342 * for slave u-boot IMAGE instored in master memory space,
343 * PHYS must be aligned based on the SIZE
345 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
346 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
347 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
348 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
350 * for slave UCODE and ENV instored in master memory space,
351 * PHYS must be aligned based on the SIZE
353 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
354 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
355 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
357 /* slave core release by master*/
358 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
359 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
362 * SRIO_PCIE_BOOT - SLAVE
364 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
365 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
366 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
367 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
370 * eSPI - Enhanced SPI
372 #define CONFIG_SF_DEFAULT_SPEED 10000000
373 #define CONFIG_SF_DEFAULT_MODE 0
376 #ifndef CONFIG_NOBQFMAN
377 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
378 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
379 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
380 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
381 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
382 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
383 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
384 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
385 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
386 CONFIG_SYS_BMAN_CENA_SIZE)
387 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
388 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
389 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
390 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
391 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
392 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
393 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
394 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
395 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
396 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
397 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
398 CONFIG_SYS_QMAN_CENA_SIZE)
399 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
400 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
402 #define CONFIG_SYS_DPAA_FMAN
403 #define CONFIG_SYS_DPAA_PME
404 #define CONFIG_SYS_PMAN
405 #define CONFIG_SYS_DPAA_DCE
406 #define CONFIG_SYS_DPAA_RMAN
407 #define CONFIG_SYS_INTERLAKEN
409 /* Default address of microcode for the Linux Fman driver */
410 #if defined(CONFIG_SPIFLASH)
412 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
413 * env, so we got 0x110000.
415 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
416 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
417 #elif defined(CONFIG_SDCARD)
419 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
420 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
421 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
423 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
424 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
425 #elif defined(CONFIG_NAND)
426 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
427 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
428 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
430 * Slave has no ucode locally, it can fetch this from remote. When implementing
431 * in two corenet boards, slave's ucode could be stored in master's memory
432 * space, the address can be mapped from slave TLB->slave LAW->
433 * slave SRIO or PCIE outbound window->master inbound window->
434 * master LAW->the ucode address in master's memory space.
436 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
437 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
439 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
440 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
442 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
443 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
444 #endif /* CONFIG_NOBQFMAN */
446 #ifdef CONFIG_SYS_DPAA_FMAN
447 #define CONFIG_FMAN_ENET
448 #define CONFIG_PHYLIB_10G
449 #define CONFIG_PHY_VITESSE
450 #define CONFIG_PHY_TERANETICS
451 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
452 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
453 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
454 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
455 #define FM1_10GEC1_PHY_ADDR 0x0
456 #define FM1_10GEC2_PHY_ADDR 0x1
457 #define FM2_10GEC1_PHY_ADDR 0x2
458 #define FM2_10GEC2_PHY_ADDR 0x3
462 #ifdef CONFIG_FSL_SATA_V2
463 #define CONFIG_SYS_SATA_MAX_DEVICE 2
465 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
466 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
468 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
469 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
474 #ifdef CONFIG_FMAN_ENET
475 #define CONFIG_ETHPRIME "FM1@DTSEC1"
481 #define CONFIG_USB_EHCI_FSL
482 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
483 #define CONFIG_HAS_FSL_DR_USB
486 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
487 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
488 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
489 #define CONFIG_ESDHC_DETECT_QUIRK \
490 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
491 IS_SVR_REV(get_svr(), 1, 0))
492 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
493 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
497 #define __USB_PHY_TYPE utmi
500 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
501 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
502 * interleaving. It can be cacheline, page, bank, superbank.
503 * See doc/README.fsl-ddr for details.
505 #ifdef CONFIG_ARCH_T4240
506 #define CTRL_INTLV_PREFERED 3way_4KB
508 #define CTRL_INTLV_PREFERED cacheline
511 #define CONFIG_EXTRA_ENV_SETTINGS \
512 "hwconfig=fsl_ddr:" \
513 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
515 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
517 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
518 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
519 "tftpflash=tftpboot $loadaddr $uboot && " \
520 "protect off $ubootaddr +$filesize && " \
521 "erase $ubootaddr +$filesize && " \
522 "cp.b $loadaddr $ubootaddr $filesize && " \
523 "protect on $ubootaddr +$filesize && " \
524 "cmp.b $loadaddr $ubootaddr $filesize\0" \
525 "consoledev=ttyS0\0" \
526 "ramdiskaddr=2000000\0" \
527 "ramdiskfile=t4240qds/ramdisk.uboot\0" \
528 "fdtaddr=1e00000\0" \
529 "fdtfile=t4240qds/t4240qds.dtb\0" \
532 #define CONFIG_HVBOOT \
533 "setenv bootargs config-addr=0x60000000; " \
534 "bootm 0x01000000 - 0x00f00000"
537 "setenv bootargs root=/dev/$bdev rw " \
538 "console=$consoledev,$baudrate $othbootargs;" \
539 "cpu 1 release 0x01000000 - - -;" \
540 "cpu 2 release 0x01000000 - - -;" \
541 "cpu 3 release 0x01000000 - - -;" \
542 "cpu 4 release 0x01000000 - - -;" \
543 "cpu 5 release 0x01000000 - - -;" \
544 "cpu 6 release 0x01000000 - - -;" \
545 "cpu 7 release 0x01000000 - - -;" \
548 #define CONFIG_LINUX \
549 "setenv bootargs root=/dev/ram rw " \
550 "console=$consoledev,$baudrate $othbootargs;" \
551 "setenv ramdiskaddr 0x02000000;" \
552 "setenv fdtaddr 0x00c00000;" \
553 "setenv loadaddr 0x1000000;" \
554 "bootm $loadaddr $ramdiskaddr $fdtaddr"
556 #define CONFIG_HDBOOT \
557 "setenv bootargs root=/dev/$bdev rw " \
558 "console=$consoledev,$baudrate $othbootargs;" \
559 "tftp $loadaddr $bootfile;" \
560 "tftp $fdtaddr $fdtfile;" \
561 "bootm $loadaddr - $fdtaddr"
563 #define CONFIG_NFSBOOTCOMMAND \
564 "setenv bootargs root=/dev/nfs rw " \
565 "nfsroot=$serverip:$rootpath " \
566 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
567 "console=$consoledev,$baudrate $othbootargs;" \
568 "tftp $loadaddr $bootfile;" \
569 "tftp $fdtaddr $fdtfile;" \
570 "bootm $loadaddr - $fdtaddr"
572 #define CONFIG_RAMBOOTCOMMAND \
573 "setenv bootargs root=/dev/ram rw " \
574 "console=$consoledev,$baudrate $othbootargs;" \
575 "tftp $ramdiskaddr $ramdiskfile;" \
576 "tftp $loadaddr $bootfile;" \
577 "tftp $fdtaddr $fdtfile;" \
578 "bootm $loadaddr $ramdiskaddr $fdtaddr"
580 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
582 #include <asm/fsl_secure_boot.h>
584 #endif /* __CONFIG_H */