include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17
  18 /* High Level Configuration Options */
  19 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  20
  21 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  22 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  23
  24 #ifdef CONFIG_RAMBOOT_PBL
  25 #define RESET_VECTOR_OFFSET             0x27FFC
  26 #define BOOT_PAGE_OFFSET                0x27000
  27
  28 #ifdef CONFIG_MTD_RAW_NAND
  29 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  30 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  31 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  32 #endif
  33
  34 #ifdef CONFIG_SPIFLASH
  35 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  38 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  39 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  40 #endif
  41
  42 #ifdef CONFIG_SDCARD
  43 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  44 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  45 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  46 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  47 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  48 #endif
  49
  50 #endif /* CONFIG_RAMBOOT_PBL */
  51
  52 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  53 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  54 /* Set 1M boot space */
  55 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  56 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  57                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  58 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  59 #endif
  60
  61 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  62 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  63 #endif
  64
  65 /*
  66  * These can be toggled for performance analysis, otherwise use default.
  67  */
  68 #define CONFIG_SYS_CACHE_STASHING
  69 #ifdef CONFIG_DDR_ECC
  70 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  71 #endif
  72
  73 /*
  74  * Config the L3 Cache as L3 SRAM
  75  */
  76 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  77 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  78 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  79
  80 #define CONFIG_SYS_DCSRBAR      0xf0000000
  81 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  82
  83 /* EEPROM */
  84 #define CONFIG_SYS_I2C_EEPROM_NXID
  85 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  86
  87 /*
  88  * DDR Setup
  89  */
  90 #define CONFIG_VERY_BIG_RAM
  91 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  92 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  93 #define CONFIG_SYS_SPD_BUS_NUM  0
  94 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
  95 #define SPD_EEPROM_ADDRESS1     0x51
  96 #define SPD_EEPROM_ADDRESS2     0x52
  97 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  98 #define CTRL_INTLV_PREFERED     cacheline
  99
 100 /*
 101  * IFC Definitions
 102  */
 103 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 104 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 105 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 106 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 107                                 CSPR_PORT_SIZE_16 | \
 108                                 CSPR_MSEL_NOR | \
 109                                 CSPR_V)
 110 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 111
 112 /* NOR Flash Timing Params */
 113 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 114
 115 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 116                                 FTIM0_NOR_TEADC(0x5) | \
 117                                 FTIM0_NOR_TEAHC(0x5))
 118 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 119                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 120                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 121 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 122                                 FTIM2_NOR_TCH(0x4) | \
 123                                 FTIM2_NOR_TWPH(0x0E) | \
 124                                 FTIM2_NOR_TWP(0x1c))
 125 #define CONFIG_SYS_NOR_FTIM3    0x0
 126
 127 #define CONFIG_SYS_FLASH_QUIET_TEST
 128 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 129
 130 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 131 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 132 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 133 #define CONFIG_SYS_FLASH_EMPTY_INFO
 134 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 135
 136 /* CPLD on IFC */
 137 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 138 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 139 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 140 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 141                                 | CSPR_PORT_SIZE_8 \
 142                                 | CSPR_MSEL_GPCM \
 143                                 | CSPR_V)
 144 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 145 #define CONFIG_SYS_CSOR2        0x0
 146
 147 /* CPLD Timing parameters for IFC CS2 */
 148 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 149                                         FTIM0_GPCM_TEADC(0x0e) | \
 150                                         FTIM0_GPCM_TEAHC(0x0e))
 151 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 152                                         FTIM1_GPCM_TRAD(0x1f))
 153 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 154                                         FTIM2_GPCM_TCH(0x8) | \
 155                                         FTIM2_GPCM_TWP(0x1f))
 156 #define CONFIG_SYS_CS2_FTIM3            0x0
 157
 158 /* NAND Flash on IFC */
 159 #define CONFIG_SYS_NAND_BASE            0xff800000
 160 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 161
 162 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 163 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 164                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 165                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 166                                 | CSPR_V)
 167 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 168
 169 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 170                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 171                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 172                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 173                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 174                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 175                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 176
 177 /* ONFI NAND Flash mode0 Timing Params */
 178 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 179                                         FTIM0_NAND_TWP(0x18)    | \
 180                                         FTIM0_NAND_TWCHT(0x07)  | \
 181                                         FTIM0_NAND_TWH(0x0a))
 182 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 183                                         FTIM1_NAND_TWBE(0x39)   | \
 184                                         FTIM1_NAND_TRR(0x0e)    | \
 185                                         FTIM1_NAND_TRP(0x18))
 186 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 187                                         FTIM2_NAND_TREH(0x0a)   | \
 188                                         FTIM2_NAND_TWHRE(0x1e))
 189 #define CONFIG_SYS_NAND_FTIM3           0x0
 190
 191 #define CONFIG_SYS_NAND_DDR_LAW         11
 192 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 193 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 194
 195 #if defined(CONFIG_MTD_RAW_NAND)
 196 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 197 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 198 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 199 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 200 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 201 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 202 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 203 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 204 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 205 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 206 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 207 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 208 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 209 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 210 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 211 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 212 #else
 213 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 214 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 215 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 216 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 217 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 218 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 219 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 220 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 221 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 222 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 223 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 224 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 225 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 226 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 227 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 228 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 229 #endif
 230
 231 #if defined(CONFIG_RAMBOOT_PBL)
 232 #define CONFIG_SYS_RAMBOOT
 233 #endif
 234
 235 #define CONFIG_HWCONFIG
 236
 237 /* define to use L1 as initial stack */
 238 #define CONFIG_L1_INIT_RAM
 239 #define CONFIG_SYS_INIT_RAM_LOCK
 240 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 241 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 242 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 243 /* The assembler doesn't like typecast */
 244 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 245                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 246                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 247 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 248 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 249 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 250
 251 /*
 252  * Serial Port
 253  */
 254 #define CONFIG_SYS_NS16550_SERIAL
 255 #define CONFIG_SYS_NS16550_REG_SIZE     1
 256 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 257 #define CONFIG_SYS_BAUDRATE_TABLE       \
 258         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 259 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 260 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 261 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 262 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 263
 264 /*
 265  * I2C
 266  */
 267
 268 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 269 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 270 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 271 #define I2C_MUX_CH_DEFAULT      0x8
 272
 273 #define I2C_MUX_CH_VOL_MONITOR  0xa
 274
 275 /* The lowest and highest voltage allowed for T208xRDB */
 276 #define VDD_MV_MIN                      819
 277 #define VDD_MV_MAX                      1212
 278
 279 /*
 280  * RapidIO
 281  */
 282 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 283 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 284 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 285 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 286 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 287 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 288 /*
 289  * for slave u-boot IMAGE instored in master memory space,
 290  * PHYS must be aligned based on the SIZE
 291  */
 292 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 293 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 294 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 295 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 296 /*
 297  * for slave UCODE and ENV instored in master memory space,
 298  * PHYS must be aligned based on the SIZE
 299  */
 300 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 301 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 302 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 303
 304 /* slave core release by master*/
 305 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 306 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 307
 308 /*
 309  * SRIO_PCIE_BOOT - SLAVE
 310  */
 311 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 312 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 313 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 314                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 315 #endif
 316
 317 /*
 318  * eSPI - Enhanced SPI
 319  */
 320
 321 /*
 322  * General PCI
 323  * Memory space is mapped 1-1, but I/O space must start from 0.
 324  */
 325 #define CONFIG_PCIE1            /* PCIE controller 1 */
 326 #define CONFIG_PCIE2            /* PCIE controller 2 */
 327 #define CONFIG_PCIE3            /* PCIE controller 3 */
 328 #define CONFIG_PCIE4            /* PCIE controller 4 */
 329 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 330 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 331 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 332 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 333 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 334
 335 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 336 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 337 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 338 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 339 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 340
 341 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 342 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 343 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 344 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 345 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 346
 347 /* controller 4, Base address 203000 */
 348 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 349 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 350 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 351
 352 #ifdef CONFIG_PCI
 353 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 354 #endif
 355
 356 /* Qman/Bman */
 357 #ifndef CONFIG_NOBQFMAN
 358 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 359 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 360 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 361 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 362 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 363 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 364 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 365 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 366 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 367                                         CONFIG_SYS_BMAN_CENA_SIZE)
 368 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 369 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 370 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 371 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 372 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 373 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 374 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 375 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 376 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 377 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 378 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 379                                         CONFIG_SYS_QMAN_CENA_SIZE)
 380 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 381 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 382
 383 #define CONFIG_SYS_DPAA_FMAN
 384 #define CONFIG_SYS_DPAA_PME
 385 #define CONFIG_SYS_PMAN
 386 #define CONFIG_SYS_DPAA_DCE
 387 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 388 #define CONFIG_SYS_INTERLAKEN
 389
 390 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 391 #endif /* CONFIG_NOBQFMAN */
 392
 393 #ifdef CONFIG_SYS_DPAA_FMAN
 394 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 395 #define RGMII_PHY2_ADDR         0x02
 396 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 397 #define CORTINA_PHY_ADDR2       0x0d
 398 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 399 #define FM1_10GEC3_PHY_ADDR     0x00
 400 #define FM1_10GEC4_PHY_ADDR     0x01
 401 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 402 #define AQR113C_PHY_ADDR1       0x00
 403 #define AQR113C_PHY_ADDR2       0x08
 404 #endif
 405
 406 /*
 407  * USB
 408  */
 409
 410 /*
 411  * SDHC
 412  */
 413 #ifdef CONFIG_MMC
 414 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 415 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 416 #endif
 417
 418 /*
 419  * Dynamic MTD Partition support with mtdparts
 420  */
 421
 422 /*
 423  * Environment
 424  */
 425
 426 /*
 427  * Miscellaneous configurable options
 428  */
 429
 430 /*
 431  * For booting Linux, the board info and command line data
 432  * have to be in the first 64 MB of memory, since this is
 433  * the maximum mapped by the Linux kernel during initialization.
 434  */
 435 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 436 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 437
 438 /*
 439  * Environment Configuration
 440  */
 441 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 442 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 443
 444 #define __USB_PHY_TYPE          utmi
 445
 446 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 447         "hwconfig=fsl_ddr:"                                     \
 448         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 449         "bank_intlv=auto;"                                      \
 450         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 451         "netdev=eth0\0"                                         \
 452         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 453         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 454         "tftpflash=tftpboot $loadaddr $uboot && "               \
 455         "protect off $ubootaddr +$filesize && "                 \
 456         "erase $ubootaddr +$filesize && "                       \
 457         "cp.b $loadaddr $ubootaddr $filesize && "               \
 458         "protect on $ubootaddr +$filesize && "                  \
 459         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 460         "consoledev=ttyS0\0"                                    \
 461         "ramdiskaddr=2000000\0"                                 \
 462         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 463         "fdtaddr=1e00000\0"                                     \
 464         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 465         "bdev=sda3\0"
 466
 467 /*
 468  * For emulation this causes u-boot to jump to the start of the
 469  * proof point app code automatically
 470  */
 471 #define PROOF_POINTS                            \
 472         "setenv bootargs root=/dev/$bdev rw "           \
 473         "console=$consoledev,$baudrate $othbootargs;"   \
 474         "cpu 1 release 0x29000000 - - -;"               \
 475         "cpu 2 release 0x29000000 - - -;"               \
 476         "cpu 3 release 0x29000000 - - -;"               \
 477         "cpu 4 release 0x29000000 - - -;"               \
 478         "cpu 5 release 0x29000000 - - -;"               \
 479         "cpu 6 release 0x29000000 - - -;"               \
 480         "cpu 7 release 0x29000000 - - -;"               \
 481         "go 0x29000000"
 482
 483 #define HVBOOT                          \
 484         "setenv bootargs config-addr=0x60000000; "      \
 485         "bootm 0x01000000 - 0x00f00000"
 486
 487 #define ALU                             \
 488         "setenv bootargs root=/dev/$bdev rw "           \
 489         "console=$consoledev,$baudrate $othbootargs;"   \
 490         "cpu 1 release 0x01000000 - - -;"               \
 491         "cpu 2 release 0x01000000 - - -;"               \
 492         "cpu 3 release 0x01000000 - - -;"               \
 493         "cpu 4 release 0x01000000 - - -;"               \
 494         "cpu 5 release 0x01000000 - - -;"               \
 495         "cpu 6 release 0x01000000 - - -;"               \
 496         "cpu 7 release 0x01000000 - - -;"               \
 497         "go 0x01000000"
 498
 499 #include <asm/fsl_secure_boot.h>
 500
 501 #endif  /* __T2080RDB_H */