Convert CONFIG_SYS_FSL_CPC et al to Kconfig
[platform/kernel/u-boot.git] / include / configs / T208xRDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  * Copyright 2020-2021 NXP
5  */
6
7 /*
8  * T2080 RDB/PCIe board configuration file
9  */
10
11 #ifndef __T2080RDB_H
12 #define __T2080RDB_H
13
14 #include <linux/stringify.h>
15
16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
17
18 /* High Level Configuration Options */
19
20 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
21
22 #ifdef CONFIG_RAMBOOT_PBL
23 #define RESET_VECTOR_OFFSET             0x27FFC
24 #define BOOT_PAGE_OFFSET                0x27000
25
26 #ifdef CONFIG_MTD_RAW_NAND
27 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
28 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
29 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
30 #endif
31
32 #ifdef CONFIG_SPIFLASH
33 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
34 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
35 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
36 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
37 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
38 #endif
39
40 #ifdef CONFIG_SDCARD
41 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
42 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
43 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
44 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
45 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
46 #endif
47
48 #endif /* CONFIG_RAMBOOT_PBL */
49
50 #define CONFIG_SRIO_PCIE_BOOT_MASTER
51 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
52 /* Set 1M boot space */
53 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
54 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
55                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
56 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
57 #endif
58
59 #ifndef CONFIG_RESET_VECTOR_ADDRESS
60 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
61 #endif
62
63 /*
64  * These can be toggled for performance analysis, otherwise use default.
65  */
66 #define CONFIG_SYS_CACHE_STASHING
67 #ifdef CONFIG_DDR_ECC
68 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
69 #endif
70
71 /*
72  * Config the L3 Cache as L3 SRAM
73  */
74 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
75 #define CONFIG_SYS_L3_SIZE              (512 << 10)
76 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
77
78 #define CONFIG_SYS_DCSRBAR      0xf0000000
79 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
80
81 /* EEPROM */
82 #define CONFIG_SYS_I2C_EEPROM_NXID
83 #define CONFIG_SYS_EEPROM_BUS_NUM       0
84
85 /*
86  * DDR Setup
87  */
88 #define CONFIG_VERY_BIG_RAM
89 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
90 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
91 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
92 #define SPD_EEPROM_ADDRESS1     0x51
93 #define SPD_EEPROM_ADDRESS2     0x52
94 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
95 #define CTRL_INTLV_PREFERED     cacheline
96
97 /*
98  * IFC Definitions
99  */
100 #define CONFIG_SYS_FLASH_BASE           0xe8000000
101 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
102 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
103 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
104                                 CSPR_PORT_SIZE_16 | \
105                                 CSPR_MSEL_NOR | \
106                                 CSPR_V)
107 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
108
109 /* NOR Flash Timing Params */
110 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
111
112 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
113                                 FTIM0_NOR_TEADC(0x5) | \
114                                 FTIM0_NOR_TEAHC(0x5))
115 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
116                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
117                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
118 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
119                                 FTIM2_NOR_TCH(0x4) | \
120                                 FTIM2_NOR_TWPH(0x0E) | \
121                                 FTIM2_NOR_TWP(0x1c))
122 #define CONFIG_SYS_NOR_FTIM3    0x0
123
124 #define CONFIG_SYS_FLASH_QUIET_TEST
125 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
126
127 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
128 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
129 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
130 #define CONFIG_SYS_FLASH_EMPTY_INFO
131 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
132
133 /* CPLD on IFC */
134 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
135 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
136 #define CONFIG_SYS_CSPR2_EXT    (0xf)
137 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
138                                 | CSPR_PORT_SIZE_8 \
139                                 | CSPR_MSEL_GPCM \
140                                 | CSPR_V)
141 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
142 #define CONFIG_SYS_CSOR2        0x0
143
144 /* CPLD Timing parameters for IFC CS2 */
145 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
146                                         FTIM0_GPCM_TEADC(0x0e) | \
147                                         FTIM0_GPCM_TEAHC(0x0e))
148 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
149                                         FTIM1_GPCM_TRAD(0x1f))
150 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
151                                         FTIM2_GPCM_TCH(0x8) | \
152                                         FTIM2_GPCM_TWP(0x1f))
153 #define CONFIG_SYS_CS2_FTIM3            0x0
154
155 /* NAND Flash on IFC */
156 #define CONFIG_SYS_NAND_BASE            0xff800000
157 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
158
159 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
160 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
161                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
162                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
163                                 | CSPR_V)
164 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
165
166 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
167                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
168                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
169                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
170                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
171                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
172                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
173
174 /* ONFI NAND Flash mode0 Timing Params */
175 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
176                                         FTIM0_NAND_TWP(0x18)    | \
177                                         FTIM0_NAND_TWCHT(0x07)  | \
178                                         FTIM0_NAND_TWH(0x0a))
179 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
180                                         FTIM1_NAND_TWBE(0x39)   | \
181                                         FTIM1_NAND_TRR(0x0e)    | \
182                                         FTIM1_NAND_TRP(0x18))
183 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
184                                         FTIM2_NAND_TREH(0x0a)   | \
185                                         FTIM2_NAND_TWHRE(0x1e))
186 #define CONFIG_SYS_NAND_FTIM3           0x0
187
188 #define CONFIG_SYS_NAND_DDR_LAW         11
189 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
190 #define CONFIG_SYS_MAX_NAND_DEVICE      1
191
192 #if defined(CONFIG_MTD_RAW_NAND)
193 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
194 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
195 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
196 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
197 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
198 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
199 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
200 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
201 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
202 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
203 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
204 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
205 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
206 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
207 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
208 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
209 #else
210 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
211 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
212 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
213 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
214 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
215 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
216 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
217 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
218 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
219 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
220 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
221 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
222 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
223 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
224 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
225 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
226 #endif
227
228 #define CONFIG_HWCONFIG
229
230 /* define to use L1 as initial stack */
231 #define CONFIG_L1_INIT_RAM
232 #define CONFIG_SYS_INIT_RAM_LOCK
233 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
234 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
235 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
236 /* The assembler doesn't like typecast */
237 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
238                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
239                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
240 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
241 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
242 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
243
244 /*
245  * Serial Port
246  */
247 #define CONFIG_SYS_NS16550_SERIAL
248 #define CONFIG_SYS_NS16550_REG_SIZE     1
249 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
250 #define CONFIG_SYS_BAUDRATE_TABLE       \
251         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
252 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
253 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
254 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
255 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
256
257 /*
258  * I2C
259  */
260
261 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
262 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
263 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
264 #define I2C_MUX_CH_DEFAULT      0x8
265
266 #define I2C_MUX_CH_VOL_MONITOR  0xa
267
268 /* The lowest and highest voltage allowed for T208xRDB */
269 #define VDD_MV_MIN                      819
270 #define VDD_MV_MAX                      1212
271
272 /*
273  * RapidIO
274  */
275 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
276 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
277 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
278 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
279 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
280 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
281 /*
282  * for slave u-boot IMAGE instored in master memory space,
283  * PHYS must be aligned based on the SIZE
284  */
285 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
286 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
287 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
288 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
289 /*
290  * for slave UCODE and ENV instored in master memory space,
291  * PHYS must be aligned based on the SIZE
292  */
293 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
294 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
295 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
296
297 /* slave core release by master*/
298 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
299 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
300
301 /*
302  * SRIO_PCIE_BOOT - SLAVE
303  */
304 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
305 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
306 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
307                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
308 #endif
309
310 /*
311  * eSPI - Enhanced SPI
312  */
313
314 /*
315  * General PCI
316  * Memory space is mapped 1-1, but I/O space must start from 0.
317  */
318 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
319 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
320 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
321 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
322 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
323
324 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
325 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
326 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
327 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
328 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
329
330 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
331 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
332 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
333 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
334 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
335
336 /* controller 4, Base address 203000 */
337 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
338 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
339 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
340
341 /* Qman/Bman */
342 #ifndef CONFIG_NOBQFMAN
343 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
344 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
345 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
346 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
347 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
348 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
349 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
350 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
351 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
352                                         CONFIG_SYS_BMAN_CENA_SIZE)
353 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
354 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
355 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
356 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
357 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
358 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
359 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
360 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
361 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
362 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
363 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
364                                         CONFIG_SYS_QMAN_CENA_SIZE)
365 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
366 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
367
368 #define CONFIG_SYS_DPAA_FMAN
369 #define CONFIG_SYS_DPAA_PME
370 #define CONFIG_SYS_PMAN
371 #define CONFIG_SYS_DPAA_DCE
372 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
373 #define CONFIG_SYS_INTERLAKEN
374
375 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
376 #endif /* CONFIG_NOBQFMAN */
377
378 #ifdef CONFIG_SYS_DPAA_FMAN
379 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
380 #define RGMII_PHY2_ADDR         0x02
381 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
382 #define CORTINA_PHY_ADDR2       0x0d
383 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
384 #define FM1_10GEC3_PHY_ADDR     0x00
385 #define FM1_10GEC4_PHY_ADDR     0x01
386 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
387 #define AQR113C_PHY_ADDR1       0x00
388 #define AQR113C_PHY_ADDR2       0x08
389 #endif
390
391 /*
392  * USB
393  */
394
395 /*
396  * SDHC
397  */
398 #ifdef CONFIG_MMC
399 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
400 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
401 #endif
402
403 /*
404  * Dynamic MTD Partition support with mtdparts
405  */
406
407 /*
408  * Environment
409  */
410
411 /*
412  * Miscellaneous configurable options
413  */
414
415 /*
416  * For booting Linux, the board info and command line data
417  * have to be in the first 64 MB of memory, since this is
418  * the maximum mapped by the Linux kernel during initialization.
419  */
420 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
421 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
422
423 /*
424  * Environment Configuration
425  */
426 #define CONFIG_ROOTPATH  "/opt/nfsroot"
427 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
428
429 #define __USB_PHY_TYPE          utmi
430
431 #define CONFIG_EXTRA_ENV_SETTINGS                               \
432         "hwconfig=fsl_ddr:"                                     \
433         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
434         "bank_intlv=auto;"                                      \
435         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
436         "netdev=eth0\0"                                         \
437         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
438         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
439         "tftpflash=tftpboot $loadaddr $uboot && "               \
440         "protect off $ubootaddr +$filesize && "                 \
441         "erase $ubootaddr +$filesize && "                       \
442         "cp.b $loadaddr $ubootaddr $filesize && "               \
443         "protect on $ubootaddr +$filesize && "                  \
444         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
445         "consoledev=ttyS0\0"                                    \
446         "ramdiskaddr=2000000\0"                                 \
447         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
448         "fdtaddr=1e00000\0"                                     \
449         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
450         "bdev=sda3\0"
451
452 /*
453  * For emulation this causes u-boot to jump to the start of the
454  * proof point app code automatically
455  */
456 #define PROOF_POINTS                            \
457         "setenv bootargs root=/dev/$bdev rw "           \
458         "console=$consoledev,$baudrate $othbootargs;"   \
459         "cpu 1 release 0x29000000 - - -;"               \
460         "cpu 2 release 0x29000000 - - -;"               \
461         "cpu 3 release 0x29000000 - - -;"               \
462         "cpu 4 release 0x29000000 - - -;"               \
463         "cpu 5 release 0x29000000 - - -;"               \
464         "cpu 6 release 0x29000000 - - -;"               \
465         "cpu 7 release 0x29000000 - - -;"               \
466         "go 0x29000000"
467
468 #define HVBOOT                          \
469         "setenv bootargs config-addr=0x60000000; "      \
470         "bootm 0x01000000 - 0x00f00000"
471
472 #define ALU                             \
473         "setenv bootargs root=/dev/$bdev rw "           \
474         "console=$consoledev,$baudrate $othbootargs;"   \
475         "cpu 1 release 0x01000000 - - -;"               \
476         "cpu 2 release 0x01000000 - - -;"               \
477         "cpu 3 release 0x01000000 - - -;"               \
478         "cpu 4 release 0x01000000 - - -;"               \
479         "cpu 5 release 0x01000000 - - -;"               \
480         "cpu 6 release 0x01000000 - - -;"               \
481         "cpu 7 release 0x01000000 - - -;"               \
482         "go 0x01000000"
483
484 #include <asm/fsl_secure_boot.h>
485
486 #endif  /* __T2080RDB_H */