Merge branch 'master' of git://git.denx.de/u-boot-samsung
[platform/kernel/u-boot.git] / include / configs / T208xRDB.h
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  * T2080 RDB/PCIe board configuration file
9  */
10
11 #ifndef __T2080RDB_H
12 #define __T2080RDB_H
13
14 #define CONFIG_DISPLAY_BOARDINFO
15 #define CONFIG_T2080RDB
16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
17 #define CONFIG_MMC
18 #define CONFIG_USB_EHCI
19 #define CONFIG_FSL_SATA_V2
20
21 /* High Level Configuration Options */
22 #define CONFIG_PHYS_64BIT
23 #define CONFIG_BOOKE
24 #define CONFIG_E500             /* BOOKE e500 family */
25 #define CONFIG_E500MC           /* BOOKE e500mc family */
26 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
27 #define CONFIG_MP               /* support multiple processors */
28 #define CONFIG_ENABLE_36BIT_PHYS
29
30 #ifdef CONFIG_PHYS_64BIT
31 #define CONFIG_ADDR_MAP 1
32 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
33 #endif
34
35 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
36 #define CONFIG_SYS_NUM_CPC      CONFIG_NUM_DDR_CONTROLLERS
37 #define CONFIG_FSL_IFC          /* Enable IFC Support */
38 #define CONFIG_FSL_CAAM         /* Enable SEC/CAAM */
39 #define CONFIG_FSL_LAW          /* Use common FSL init code */
40 #define CONFIG_ENV_OVERWRITE
41
42 #ifdef CONFIG_RAMBOOT_PBL
43 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
44 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
45
46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
47 #define CONFIG_SPL_ENV_SUPPORT
48 #define CONFIG_SPL_SERIAL_SUPPORT
49 #define CONFIG_SPL_FLUSH_IMAGE
50 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
51 #define CONFIG_SPL_LIBGENERIC_SUPPORT
52 #define CONFIG_SPL_LIBCOMMON_SUPPORT
53 #define CONFIG_SPL_I2C_SUPPORT
54 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
55 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
56 #define CONFIG_SYS_TEXT_BASE            0x00201000
57 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
58 #define CONFIG_SPL_PAD_TO               0x40000
59 #define CONFIG_SPL_MAX_SIZE             0x28000
60 #define RESET_VECTOR_OFFSET             0x27FFC
61 #define BOOT_PAGE_OFFSET                0x27000
62 #ifdef CONFIG_SPL_BUILD
63 #define CONFIG_SPL_SKIP_RELOCATE
64 #define CONFIG_SPL_COMMON_INIT_DDR
65 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
66 #define CONFIG_SYS_NO_FLASH
67 #endif
68
69 #ifdef CONFIG_NAND
70 #define CONFIG_SPL_NAND_SUPPORT
71 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
72 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
73 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
74 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
75 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
76 #define CONFIG_SPL_NAND_BOOT
77 #endif
78
79 #ifdef CONFIG_SPIFLASH
80 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
81 #define CONFIG_SPL_SPI_SUPPORT
82 #define CONFIG_SPL_SPI_FLASH_SUPPORT
83 #define CONFIG_SPL_SPI_FLASH_MINIMAL
84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
88 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
89 #ifndef CONFIG_SPL_BUILD
90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
91 #endif
92 #define CONFIG_SPL_SPI_BOOT
93 #endif
94
95 #ifdef CONFIG_SDCARD
96 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
97 #define CONFIG_SPL_MMC_SUPPORT
98 #define CONFIG_SPL_MMC_MINIMAL
99 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
100 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
101 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
102 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
103 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
104 #ifndef CONFIG_SPL_BUILD
105 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
106 #endif
107 #define CONFIG_SPL_MMC_BOOT
108 #endif
109
110 #endif /* CONFIG_RAMBOOT_PBL */
111
112 #define CONFIG_SRIO_PCIE_BOOT_MASTER
113 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
114 /* Set 1M boot space */
115 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
116 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
117                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
118 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
119 #define CONFIG_SYS_NO_FLASH
120 #endif
121
122 #ifndef CONFIG_SYS_TEXT_BASE
123 #define CONFIG_SYS_TEXT_BASE    0xeff40000
124 #endif
125
126 #ifndef CONFIG_RESET_VECTOR_ADDRESS
127 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
128 #endif
129
130 /*
131  * These can be toggled for performance analysis, otherwise use default.
132  */
133 #define CONFIG_SYS_CACHE_STASHING
134 #define CONFIG_BTB              /* toggle branch predition */
135 #define CONFIG_DDR_ECC
136 #ifdef CONFIG_DDR_ECC
137 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
138 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
139 #endif
140
141 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
142 #define CONFIG_SYS_MEMTEST_END          0x00400000
143 #define CONFIG_SYS_ALT_MEMTEST
144
145 #ifndef CONFIG_SYS_NO_FLASH
146 #define CONFIG_FLASH_CFI_DRIVER
147 #define CONFIG_SYS_FLASH_CFI
148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
149 #endif
150
151 #if defined(CONFIG_SPIFLASH)
152 #define CONFIG_SYS_EXTRA_ENV_RELOC
153 #define CONFIG_ENV_IS_IN_SPI_FLASH
154 #define CONFIG_ENV_SPI_BUS      0
155 #define CONFIG_ENV_SPI_CS       0
156 #define CONFIG_ENV_SPI_MAX_HZ   10000000
157 #define CONFIG_ENV_SPI_MODE     0
158 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
159 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
160 #define CONFIG_ENV_SECT_SIZE    0x10000
161 #elif defined(CONFIG_SDCARD)
162 #define CONFIG_SYS_EXTRA_ENV_RELOC
163 #define CONFIG_ENV_IS_IN_MMC
164 #define CONFIG_SYS_MMC_ENV_DEV  0
165 #define CONFIG_ENV_SIZE         0x2000
166 #define CONFIG_ENV_OFFSET       (512 * 0x800)
167 #elif defined(CONFIG_NAND)
168 #define CONFIG_SYS_EXTRA_ENV_RELOC
169 #define CONFIG_ENV_IS_IN_NAND
170 #define CONFIG_ENV_SIZE         0x2000
171 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
172 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
173 #define CONFIG_ENV_IS_IN_REMOTE
174 #define CONFIG_ENV_ADDR         0xffe20000
175 #define CONFIG_ENV_SIZE         0x2000
176 #elif defined(CONFIG_ENV_IS_NOWHERE)
177 #define CONFIG_ENV_SIZE         0x2000
178 #else
179 #define CONFIG_ENV_IS_IN_FLASH
180 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
181 #define CONFIG_ENV_SIZE         0x2000
182 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
183 #endif
184
185 #ifndef __ASSEMBLY__
186 unsigned long get_board_sys_clk(void);
187 unsigned long get_board_ddr_clk(void);
188 #endif
189
190 #define CONFIG_SYS_CLK_FREQ     66660000
191 #define CONFIG_DDR_CLK_FREQ     133330000
192
193 /*
194  * Config the L3 Cache as L3 SRAM
195  */
196 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
197 #define CONFIG_SYS_L3_SIZE              (512 << 10)
198 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
199 #ifdef CONFIG_RAMBOOT_PBL
200 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
201 #endif
202 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
203 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
204 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
205 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
206
207 #define CONFIG_SYS_DCSRBAR      0xf0000000
208 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
209
210 /* EEPROM */
211 #define CONFIG_ID_EEPROM
212 #define CONFIG_SYS_I2C_EEPROM_NXID
213 #define CONFIG_SYS_EEPROM_BUS_NUM       0
214 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
215 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
216
217 /*
218  * DDR Setup
219  */
220 #define CONFIG_VERY_BIG_RAM
221 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
222 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
223 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
224 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
225 #define CONFIG_DDR_SPD
226 #define CONFIG_SYS_FSL_DDR3
227 #undef CONFIG_FSL_DDR_INTERACTIVE
228 #define CONFIG_SYS_SPD_BUS_NUM  0
229 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
230 #define SPD_EEPROM_ADDRESS1     0x51
231 #define SPD_EEPROM_ADDRESS2     0x52
232 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
233 #define CTRL_INTLV_PREFERED     cacheline
234
235 /*
236  * IFC Definitions
237  */
238 #define CONFIG_SYS_FLASH_BASE           0xe8000000
239 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
240 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
241 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
242                                 CSPR_PORT_SIZE_16 | \
243                                 CSPR_MSEL_NOR | \
244                                 CSPR_V)
245 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
246
247 /* NOR Flash Timing Params */
248 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
249
250 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
251                                 FTIM0_NOR_TEADC(0x5) | \
252                                 FTIM0_NOR_TEAHC(0x5))
253 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
254                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
255                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
256 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
257                                 FTIM2_NOR_TCH(0x4) | \
258                                 FTIM2_NOR_TWPH(0x0E) | \
259                                 FTIM2_NOR_TWP(0x1c))
260 #define CONFIG_SYS_NOR_FTIM3    0x0
261
262 #define CONFIG_SYS_FLASH_QUIET_TEST
263 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
264
265 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
266 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
267 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
268 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
269 #define CONFIG_SYS_FLASH_EMPTY_INFO
270 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
271
272 /* CPLD on IFC */
273 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
274 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
275 #define CONFIG_SYS_CSPR2_EXT    (0xf)
276 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
277                                 | CSPR_PORT_SIZE_8 \
278                                 | CSPR_MSEL_GPCM \
279                                 | CSPR_V)
280 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
281 #define CONFIG_SYS_CSOR2        0x0
282
283 /* CPLD Timing parameters for IFC CS2 */
284 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
285                                         FTIM0_GPCM_TEADC(0x0e) | \
286                                         FTIM0_GPCM_TEAHC(0x0e))
287 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
288                                         FTIM1_GPCM_TRAD(0x1f))
289 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
290                                         FTIM2_GPCM_TCH(0x8) | \
291                                         FTIM2_GPCM_TWP(0x1f))
292 #define CONFIG_SYS_CS2_FTIM3            0x0
293
294 /* NAND Flash on IFC */
295 #define CONFIG_NAND_FSL_IFC
296 #define CONFIG_SYS_NAND_BASE            0xff800000
297 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
298
299 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
300 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
301                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
302                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
303                                 | CSPR_V)
304 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
305
306 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
307                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
308                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
309                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
310                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
311                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
312                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
313
314 #define CONFIG_SYS_NAND_ONFI_DETECTION
315
316 /* ONFI NAND Flash mode0 Timing Params */
317 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
318                                         FTIM0_NAND_TWP(0x18)    | \
319                                         FTIM0_NAND_TWCHT(0x07)  | \
320                                         FTIM0_NAND_TWH(0x0a))
321 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
322                                         FTIM1_NAND_TWBE(0x39)   | \
323                                         FTIM1_NAND_TRR(0x0e)    | \
324                                         FTIM1_NAND_TRP(0x18))
325 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
326                                         FTIM2_NAND_TREH(0x0a)   | \
327                                         FTIM2_NAND_TWHRE(0x1e))
328 #define CONFIG_SYS_NAND_FTIM3           0x0
329
330 #define CONFIG_SYS_NAND_DDR_LAW         11
331 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
332 #define CONFIG_SYS_MAX_NAND_DEVICE      1
333 #define CONFIG_CMD_NAND
334 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
335
336 #if defined(CONFIG_NAND)
337 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
338 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
339 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
340 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
341 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
342 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
343 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
344 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
345 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
346 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
347 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
348 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
349 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
350 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
351 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
352 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
353 #else
354 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
355 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
356 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
357 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
358 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
359 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
360 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
361 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
362 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
363 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
364 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
365 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
366 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
367 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
368 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
369 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
370 #endif
371
372 #if defined(CONFIG_RAMBOOT_PBL)
373 #define CONFIG_SYS_RAMBOOT
374 #endif
375
376 #ifdef CONFIG_SPL_BUILD
377 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
378 #else
379 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
380 #endif
381
382 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
383 #define CONFIG_MISC_INIT_R
384 #define CONFIG_HWCONFIG
385
386 /* define to use L1 as initial stack */
387 #define CONFIG_L1_INIT_RAM
388 #define CONFIG_SYS_INIT_RAM_LOCK
389 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
392 /* The assembler doesn't like typecast */
393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
394                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
395                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
396 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
397 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
398                                                 GENERATED_GBL_DATA_SIZE)
399 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
400 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
401 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
402
403 /*
404  * Serial Port
405  */
406 #define CONFIG_CONS_INDEX               1
407 #define CONFIG_SYS_NS16550_SERIAL
408 #define CONFIG_SYS_NS16550_REG_SIZE     1
409 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
410 #define CONFIG_SYS_BAUDRATE_TABLE       \
411         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
412 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
413 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
414 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
415 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
416
417 /*
418  * I2C
419  */
420 #define CONFIG_SYS_I2C
421 #define CONFIG_SYS_I2C_FSL
422 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
423 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
424 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
425 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
426 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
427 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
428 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
429 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
430 #define CONFIG_SYS_FSL_I2C_SPEED   100000
431 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
432 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
433 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
434 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
435 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
436 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
437 #define I2C_MUX_CH_DEFAULT      0x8
438
439 #define I2C_MUX_CH_VOL_MONITOR  0xa
440
441 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
442 #ifndef CONFIG_SPL_BUILD
443 #define CONFIG_VID
444 #endif
445 #define CONFIG_VOL_MONITOR_IR36021_SET
446 #define CONFIG_VOL_MONITOR_IR36021_READ
447 /* The lowest and highest voltage allowed for T208xRDB */
448 #define VDD_MV_MIN                      819
449 #define VDD_MV_MAX                      1212
450
451 /*
452  * RapidIO
453  */
454 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
455 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
456 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
457 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
458 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
459 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
460 /*
461  * for slave u-boot IMAGE instored in master memory space,
462  * PHYS must be aligned based on the SIZE
463  */
464 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
465 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
466 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
467 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
468 /*
469  * for slave UCODE and ENV instored in master memory space,
470  * PHYS must be aligned based on the SIZE
471  */
472 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
473 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
474 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
475
476 /* slave core release by master*/
477 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
478 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
479
480 /*
481  * SRIO_PCIE_BOOT - SLAVE
482  */
483 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
484 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
485 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
486                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
487 #endif
488
489 /*
490  * eSPI - Enhanced SPI
491  */
492 #ifdef CONFIG_SPI_FLASH
493 #define CONFIG_SPI_FLASH_BAR
494 #define CONFIG_SF_DEFAULT_SPEED  10000000
495 #define CONFIG_SF_DEFAULT_MODE    0
496 #endif
497
498 /*
499  * General PCI
500  * Memory space is mapped 1-1, but I/O space must start from 0.
501  */
502 #define CONFIG_PCI              /* Enable PCI/PCIE */
503 #define CONFIG_PCIE1            /* PCIE controler 1 */
504 #define CONFIG_PCIE2            /* PCIE controler 2 */
505 #define CONFIG_PCIE3            /* PCIE controler 3 */
506 #define CONFIG_PCIE4            /* PCIE controler 4 */
507 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
508 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
509 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
510 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
511 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
512 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
513 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
514 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
515 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
516 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
517 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
518
519 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
520 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
521 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
522 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
523 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
524 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
525 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
526 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
527 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
528
529 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
530 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
531 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
532 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
533 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
534 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
535 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
536 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
537 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
538
539 /* controller 4, Base address 203000 */
540 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
541 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
542 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
543 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
544 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
545 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
546 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
547
548 #ifdef CONFIG_PCI
549 #define CONFIG_PCI_INDIRECT_BRIDGE
550 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
551 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
552 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
553 #define CONFIG_DOS_PARTITION
554 #endif
555
556 /* Qman/Bman */
557 #ifndef CONFIG_NOBQFMAN
558 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
559 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
560 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
561 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
562 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
563 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
564 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
565 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
566 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
567 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
568                                         CONFIG_SYS_BMAN_CENA_SIZE)
569 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
570 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
571 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
572 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
573 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
574 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
575 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
576 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
577 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
578 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
579 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
580                                         CONFIG_SYS_QMAN_CENA_SIZE)
581 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
582 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
583
584 #define CONFIG_SYS_DPAA_FMAN
585 #define CONFIG_SYS_DPAA_PME
586 #define CONFIG_SYS_PMAN
587 #define CONFIG_SYS_DPAA_DCE
588 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
589 #define CONFIG_SYS_INTERLAKEN
590
591 /* Default address of microcode for the Linux Fman driver */
592 #if defined(CONFIG_SPIFLASH)
593 /*
594  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
595  * env, so we got 0x110000.
596  */
597 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
598 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
599 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
600 #define CONFIG_CORTINA_FW_ADDR          0x120000
601
602 #elif defined(CONFIG_SDCARD)
603 /*
604  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
605  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
606  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
607  */
608 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
609 #define CONFIG_SYS_CORTINA_FW_IN_MMC
610 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
611 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
612
613 #elif defined(CONFIG_NAND)
614 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
615 #define CONFIG_SYS_CORTINA_FW_IN_NAND
616 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
617 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
618 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
619 /*
620  * Slave has no ucode locally, it can fetch this from remote. When implementing
621  * in two corenet boards, slave's ucode could be stored in master's memory
622  * space, the address can be mapped from slave TLB->slave LAW->
623  * slave SRIO or PCIE outbound window->master inbound window->
624  * master LAW->the ucode address in master's memory space.
625  */
626 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
627 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
628 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
629 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
630 #else
631 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
632 #define CONFIG_SYS_CORTINA_FW_IN_NOR
633 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
634 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
635 #endif
636 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
637 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
638 #endif /* CONFIG_NOBQFMAN */
639
640 #ifdef CONFIG_SYS_DPAA_FMAN
641 #define CONFIG_FMAN_ENET
642 #define CONFIG_PHYLIB_10G
643 #define CONFIG_PHY_AQUANTIA
644 #define CONFIG_PHY_CORTINA
645 #define CONFIG_PHY_REALTEK
646 #define CONFIG_CORTINA_FW_LENGTH        0x40000
647 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
648 #define RGMII_PHY2_ADDR         0x02
649 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
650 #define CORTINA_PHY_ADDR2       0x0d
651 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
652 #define FM1_10GEC4_PHY_ADDR     0x01
653 #endif
654
655 #ifdef CONFIG_FMAN_ENET
656 #define CONFIG_MII              /* MII PHY management */
657 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
658 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
659 #endif
660
661 /*
662  * SATA
663  */
664 #ifdef CONFIG_FSL_SATA_V2
665 #define CONFIG_LIBATA
666 #define CONFIG_FSL_SATA
667 #define CONFIG_SYS_SATA_MAX_DEVICE      2
668 #define CONFIG_SATA1
669 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
670 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
671 #define CONFIG_SATA2
672 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
673 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
674 #define CONFIG_LBA48
675 #define CONFIG_CMD_SATA
676 #define CONFIG_DOS_PARTITION
677 #endif
678
679 /*
680  * USB
681  */
682 #ifdef CONFIG_USB_EHCI
683 #define CONFIG_USB_STORAGE
684 #define CONFIG_USB_EHCI_FSL
685 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
686 #define CONFIG_HAS_FSL_DR_USB
687 #endif
688
689 /*
690  * SDHC
691  */
692 #ifdef CONFIG_MMC
693 #define CONFIG_FSL_ESDHC
694 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
695 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
696 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
697 #define CONFIG_GENERIC_MMC
698 #define CONFIG_DOS_PARTITION
699 #endif
700
701 /*
702  * Dynamic MTD Partition support with mtdparts
703  */
704 #ifndef CONFIG_SYS_NO_FLASH
705 #define CONFIG_MTD_DEVICE
706 #define CONFIG_MTD_PARTITIONS
707 #define CONFIG_CMD_MTDPARTS
708 #define CONFIG_FLASH_CFI_MTD
709 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
710                         "spi0=spife110000.1"
711 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
712                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
713                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
714                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
715 #endif
716
717 /*
718  * Environment
719  */
720
721 /*
722  * Command line configuration.
723  */
724 #define CONFIG_CMD_ERRATA
725 #define CONFIG_CMD_REGINFO
726
727 #ifdef CONFIG_PCI
728 #define CONFIG_CMD_PCI
729 #endif
730
731 /* Hash command with SHA acceleration supported in hardware */
732 #ifdef CONFIG_FSL_CAAM
733 #define CONFIG_CMD_HASH
734 #define CONFIG_SHA_HW_ACCEL
735 #endif
736
737 /*
738  * Miscellaneous configurable options
739  */
740 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
741 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
742 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
743 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
744 #ifdef CONFIG_CMD_KGDB
745 #define CONFIG_SYS_CBSIZE       1024      /* Console I/O Buffer Size */
746 #else
747 #define CONFIG_SYS_CBSIZE       256       /* Console I/O Buffer Size */
748 #endif
749 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
750 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
751 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
752
753 /*
754  * For booting Linux, the board info and command line data
755  * have to be in the first 64 MB of memory, since this is
756  * the maximum mapped by the Linux kernel during initialization.
757  */
758 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
759 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
760
761 #ifdef CONFIG_CMD_KGDB
762 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
763 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
764 #endif
765
766 /*
767  * Environment Configuration
768  */
769 #define CONFIG_ROOTPATH  "/opt/nfsroot"
770 #define CONFIG_BOOTFILE  "uImage"
771 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
772
773 /* default location for tftp and bootm */
774 #define CONFIG_LOADADDR         1000000
775 #define CONFIG_BAUDRATE         115200
776 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
777 #define __USB_PHY_TYPE          utmi
778
779 #define CONFIG_EXTRA_ENV_SETTINGS                               \
780         "hwconfig=fsl_ddr:"                                     \
781         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
782         "bank_intlv=auto;"                                      \
783         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
784         "netdev=eth0\0"                                         \
785         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
786         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
787         "tftpflash=tftpboot $loadaddr $uboot && "               \
788         "protect off $ubootaddr +$filesize && "                 \
789         "erase $ubootaddr +$filesize && "                       \
790         "cp.b $loadaddr $ubootaddr $filesize && "               \
791         "protect on $ubootaddr +$filesize && "                  \
792         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
793         "consoledev=ttyS0\0"                                    \
794         "ramdiskaddr=2000000\0"                                 \
795         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
796         "fdtaddr=c00000\0"                                      \
797         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
798         "bdev=sda3\0"
799
800 /*
801  * For emulation this causes u-boot to jump to the start of the
802  * proof point app code automatically
803  */
804 #define CONFIG_PROOF_POINTS                             \
805         "setenv bootargs root=/dev/$bdev rw "           \
806         "console=$consoledev,$baudrate $othbootargs;"   \
807         "cpu 1 release 0x29000000 - - -;"               \
808         "cpu 2 release 0x29000000 - - -;"               \
809         "cpu 3 release 0x29000000 - - -;"               \
810         "cpu 4 release 0x29000000 - - -;"               \
811         "cpu 5 release 0x29000000 - - -;"               \
812         "cpu 6 release 0x29000000 - - -;"               \
813         "cpu 7 release 0x29000000 - - -;"               \
814         "go 0x29000000"
815
816 #define CONFIG_HVBOOT                           \
817         "setenv bootargs config-addr=0x60000000; "      \
818         "bootm 0x01000000 - 0x00f00000"
819
820 #define CONFIG_ALU                              \
821         "setenv bootargs root=/dev/$bdev rw "           \
822         "console=$consoledev,$baudrate $othbootargs;"   \
823         "cpu 1 release 0x01000000 - - -;"               \
824         "cpu 2 release 0x01000000 - - -;"               \
825         "cpu 3 release 0x01000000 - - -;"               \
826         "cpu 4 release 0x01000000 - - -;"               \
827         "cpu 5 release 0x01000000 - - -;"               \
828         "cpu 6 release 0x01000000 - - -;"               \
829         "cpu 7 release 0x01000000 - - -;"               \
830         "go 0x01000000"
831
832 #define CONFIG_LINUX                            \
833         "setenv bootargs root=/dev/ram rw "             \
834         "console=$consoledev,$baudrate $othbootargs;"   \
835         "setenv ramdiskaddr 0x02000000;"                \
836         "setenv fdtaddr 0x00c00000;"                    \
837         "setenv loadaddr 0x1000000;"                    \
838         "bootm $loadaddr $ramdiskaddr $fdtaddr"
839
840 #define CONFIG_HDBOOT                                   \
841         "setenv bootargs root=/dev/$bdev rw "           \
842         "console=$consoledev,$baudrate $othbootargs;"   \
843         "tftp $loadaddr $bootfile;"                     \
844         "tftp $fdtaddr $fdtfile;"                       \
845         "bootm $loadaddr - $fdtaddr"
846
847 #define CONFIG_NFSBOOTCOMMAND                   \
848         "setenv bootargs root=/dev/nfs rw "     \
849         "nfsroot=$serverip:$rootpath "          \
850         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
851         "console=$consoledev,$baudrate $othbootargs;"   \
852         "tftp $loadaddr $bootfile;"             \
853         "tftp $fdtaddr $fdtfile;"               \
854         "bootm $loadaddr - $fdtaddr"
855
856 #define CONFIG_RAMBOOTCOMMAND                           \
857         "setenv bootargs root=/dev/ram rw "             \
858         "console=$consoledev,$baudrate $othbootargs;"   \
859         "tftp $ramdiskaddr $ramdiskfile;"               \
860         "tftp $loadaddr $bootfile;"                     \
861         "tftp $fdtaddr $fdtfile;"                       \
862         "bootm $loadaddr $ramdiskaddr $fdtaddr"
863
864 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
865
866 #include <asm/fsl_secure_boot.h>
867
868 #endif  /* __T2080RDB_H */