1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
8 * T2080 RDB/PCIe board configuration file
14 #include <linux/stringify.h>
16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #define CONFIG_FSL_SATA_V2
19 /* High Level Configuration Options */
20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
21 #define CONFIG_ENABLE_36BIT_PHYS
23 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
24 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
26 #ifdef CONFIG_RAMBOOT_PBL
27 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
29 #define CONFIG_SPL_FLUSH_IMAGE
30 #define CONFIG_SPL_PAD_TO 0x40000
31 #define CONFIG_SPL_MAX_SIZE 0x28000
32 #define RESET_VECTOR_OFFSET 0x27FFC
33 #define BOOT_PAGE_OFFSET 0x27000
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SPL_SKIP_RELOCATE
36 #define CONFIG_SPL_COMMON_INIT_DDR
37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
40 #ifdef CONFIG_MTD_RAW_NAND
41 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
42 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
43 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
44 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
48 #ifdef CONFIG_SPIFLASH
49 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
50 #define CONFIG_SPL_SPI_FLASH_MINIMAL
51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
55 #ifndef CONFIG_SPL_BUILD
56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
62 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
63 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
64 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
65 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
66 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
67 #ifndef CONFIG_SPL_BUILD
68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
73 #endif /* CONFIG_RAMBOOT_PBL */
75 #define CONFIG_SRIO_PCIE_BOOT_MASTER
76 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
77 /* Set 1M boot space */
78 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
79 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
80 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
81 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
84 #ifndef CONFIG_RESET_VECTOR_ADDRESS
85 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
89 * These can be toggled for performance analysis, otherwise use default.
91 #define CONFIG_SYS_CACHE_STASHING
92 #define CONFIG_BTB /* toggle branch predition */
93 #define CONFIG_DDR_ECC
95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
96 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
99 #if defined(CONFIG_SPIFLASH)
100 #elif defined(CONFIG_SDCARD)
101 #define CONFIG_SYS_MMC_ENV_DEV 0
105 unsigned long get_board_sys_clk(void);
106 unsigned long get_board_ddr_clk(void);
109 #define CONFIG_SYS_CLK_FREQ 66660000
110 #define CONFIG_DDR_CLK_FREQ 133330000
113 * Config the L3 Cache as L3 SRAM
115 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
116 #define CONFIG_SYS_L3_SIZE (512 << 10)
117 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
118 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
119 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
120 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
121 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
123 #define CONFIG_SYS_DCSRBAR 0xf0000000
124 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
127 #define CONFIG_ID_EEPROM
128 #define CONFIG_SYS_I2C_EEPROM_NXID
129 #define CONFIG_SYS_EEPROM_BUS_NUM 0
130 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
131 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
136 #define CONFIG_VERY_BIG_RAM
137 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
138 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
139 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
140 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
141 #define CONFIG_DDR_SPD
142 #define CONFIG_SYS_SPD_BUS_NUM 0
143 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
144 #define SPD_EEPROM_ADDRESS1 0x51
145 #define SPD_EEPROM_ADDRESS2 0x52
146 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
147 #define CTRL_INTLV_PREFERED cacheline
152 #define CONFIG_SYS_FLASH_BASE 0xe8000000
153 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
154 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
155 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
156 CSPR_PORT_SIZE_16 | \
159 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
161 /* NOR Flash Timing Params */
162 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
164 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
165 FTIM0_NOR_TEADC(0x5) | \
166 FTIM0_NOR_TEAHC(0x5))
167 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
168 FTIM1_NOR_TRAD_NOR(0x1A) |\
169 FTIM1_NOR_TSEQRAD_NOR(0x13))
170 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
171 FTIM2_NOR_TCH(0x4) | \
172 FTIM2_NOR_TWPH(0x0E) | \
174 #define CONFIG_SYS_NOR_FTIM3 0x0
176 #define CONFIG_SYS_FLASH_QUIET_TEST
177 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
179 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
180 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
181 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
182 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
183 #define CONFIG_SYS_FLASH_EMPTY_INFO
184 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
187 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
188 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
189 #define CONFIG_SYS_CSPR2_EXT (0xf)
190 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
194 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
195 #define CONFIG_SYS_CSOR2 0x0
197 /* CPLD Timing parameters for IFC CS2 */
198 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
199 FTIM0_GPCM_TEADC(0x0e) | \
200 FTIM0_GPCM_TEAHC(0x0e))
201 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
202 FTIM1_GPCM_TRAD(0x1f))
203 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
204 FTIM2_GPCM_TCH(0x8) | \
205 FTIM2_GPCM_TWP(0x1f))
206 #define CONFIG_SYS_CS2_FTIM3 0x0
208 /* NAND Flash on IFC */
209 #define CONFIG_NAND_FSL_IFC
210 #define CONFIG_SYS_NAND_BASE 0xff800000
211 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
213 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
214 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
215 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
216 | CSPR_MSEL_NAND /* MSEL = NAND */ \
218 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
220 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
221 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
222 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
223 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
224 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
225 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
226 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
228 #define CONFIG_SYS_NAND_ONFI_DETECTION
230 /* ONFI NAND Flash mode0 Timing Params */
231 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
232 FTIM0_NAND_TWP(0x18) | \
233 FTIM0_NAND_TWCHT(0x07) | \
234 FTIM0_NAND_TWH(0x0a))
235 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
236 FTIM1_NAND_TWBE(0x39) | \
237 FTIM1_NAND_TRR(0x0e) | \
238 FTIM1_NAND_TRP(0x18))
239 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
240 FTIM2_NAND_TREH(0x0a) | \
241 FTIM2_NAND_TWHRE(0x1e))
242 #define CONFIG_SYS_NAND_FTIM3 0x0
244 #define CONFIG_SYS_NAND_DDR_LAW 11
245 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
246 #define CONFIG_SYS_MAX_NAND_DEVICE 1
247 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
249 #if defined(CONFIG_MTD_RAW_NAND)
250 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
251 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
252 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
253 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
254 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
255 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
256 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
257 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
258 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
259 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
260 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
261 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
262 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
263 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
264 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
265 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
267 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
268 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
269 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
270 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
271 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
272 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
273 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
274 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
275 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
276 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
277 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
278 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
279 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
280 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
281 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
282 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
285 #if defined(CONFIG_RAMBOOT_PBL)
286 #define CONFIG_SYS_RAMBOOT
289 #ifdef CONFIG_SPL_BUILD
290 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
292 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
295 #define CONFIG_HWCONFIG
297 /* define to use L1 as initial stack */
298 #define CONFIG_L1_INIT_RAM
299 #define CONFIG_SYS_INIT_RAM_LOCK
300 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
303 /* The assembler doesn't like typecast */
304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
305 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
306 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
307 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
308 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
309 GENERATED_GBL_DATA_SIZE)
310 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
311 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
312 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
317 #define CONFIG_SYS_NS16550_SERIAL
318 #define CONFIG_SYS_NS16550_REG_SIZE 1
319 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
320 #define CONFIG_SYS_BAUDRATE_TABLE \
321 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
322 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
323 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
324 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
325 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
330 #ifndef CONFIG_DM_I2C
331 #define CONFIG_SYS_I2C
332 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
333 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
334 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
335 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
336 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
337 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
338 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
339 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
340 #define CONFIG_SYS_FSL_I2C_SPEED 100000
341 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
342 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
343 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
345 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
346 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
349 #define CONFIG_SYS_I2C_FSL
351 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
352 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
353 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
354 #define I2C_MUX_CH_DEFAULT 0x8
356 #define I2C_MUX_CH_VOL_MONITOR 0xa
358 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
359 #ifndef CONFIG_SPL_BUILD
362 #define CONFIG_VOL_MONITOR_IR36021_SET
363 #define CONFIG_VOL_MONITOR_IR36021_READ
364 /* The lowest and highest voltage allowed for T208xRDB */
365 #define VDD_MV_MIN 819
366 #define VDD_MV_MAX 1212
371 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
372 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
373 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
374 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
375 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
376 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
378 * for slave u-boot IMAGE instored in master memory space,
379 * PHYS must be aligned based on the SIZE
381 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
382 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
383 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
384 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
386 * for slave UCODE and ENV instored in master memory space,
387 * PHYS must be aligned based on the SIZE
389 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
390 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
391 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
393 /* slave core release by master*/
394 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
395 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
398 * SRIO_PCIE_BOOT - SLAVE
400 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
401 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
402 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
403 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
407 * eSPI - Enhanced SPI
412 * Memory space is mapped 1-1, but I/O space must start from 0.
414 #define CONFIG_PCIE1 /* PCIE controller 1 */
415 #define CONFIG_PCIE2 /* PCIE controller 2 */
416 #define CONFIG_PCIE3 /* PCIE controller 3 */
417 #define CONFIG_PCIE4 /* PCIE controller 4 */
418 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
419 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
420 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
421 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
422 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
423 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
425 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
426 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
427 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
428 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
429 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
431 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
432 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
433 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
434 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
435 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
437 /* controller 4, Base address 203000 */
438 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
439 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
440 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
443 #if !defined(CONFIG_DM_PCI)
444 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
445 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
446 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
447 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
448 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
449 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
450 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
451 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
452 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
453 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
454 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
455 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
456 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
457 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
458 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
459 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
460 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
461 #define CONFIG_PCI_INDIRECT_BRIDGE
463 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
467 #ifndef CONFIG_NOBQFMAN
468 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
469 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
470 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
471 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
472 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
473 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
474 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
475 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
476 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
477 CONFIG_SYS_BMAN_CENA_SIZE)
478 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
479 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
480 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
481 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
482 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
483 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
484 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
485 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
486 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
487 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
488 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
489 CONFIG_SYS_QMAN_CENA_SIZE)
490 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
491 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
493 #define CONFIG_SYS_DPAA_FMAN
494 #define CONFIG_SYS_DPAA_PME
495 #define CONFIG_SYS_PMAN
496 #define CONFIG_SYS_DPAA_DCE
497 #define CONFIG_SYS_DPAA_RMAN /* RMan */
498 #define CONFIG_SYS_INTERLAKEN
500 /* Default address of microcode for the Linux Fman driver */
501 #if defined(CONFIG_SPIFLASH)
503 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
504 * env, so we got 0x110000.
506 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
507 #define CONFIG_CORTINA_FW_ADDR 0x120000
509 #elif defined(CONFIG_SDCARD)
511 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
512 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
513 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
515 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
516 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
518 #elif defined(CONFIG_MTD_RAW_NAND)
519 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
520 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
521 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
523 * Slave has no ucode locally, it can fetch this from remote. When implementing
524 * in two corenet boards, slave's ucode could be stored in master's memory
525 * space, the address can be mapped from slave TLB->slave LAW->
526 * slave SRIO or PCIE outbound window->master inbound window->
527 * master LAW->the ucode address in master's memory space.
529 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
530 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
532 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
533 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
535 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
536 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
537 #endif /* CONFIG_NOBQFMAN */
539 #ifdef CONFIG_SYS_DPAA_FMAN
540 #define CONFIG_CORTINA_FW_LENGTH 0x40000
541 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
542 #define RGMII_PHY2_ADDR 0x02
543 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
544 #define CORTINA_PHY_ADDR2 0x0d
545 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
546 #define FM1_10GEC4_PHY_ADDR 0x01
549 #ifdef CONFIG_FMAN_ENET
550 #define CONFIG_ETHPRIME "FM1@DTSEC3"
556 #ifdef CONFIG_FSL_SATA_V2
557 #define CONFIG_SYS_SATA_MAX_DEVICE 2
559 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
560 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
562 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
563 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
570 #ifdef CONFIG_USB_EHCI_HCD
571 #define CONFIG_USB_EHCI_FSL
572 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
573 #define CONFIG_HAS_FSL_DR_USB
580 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
581 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
582 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
586 * Dynamic MTD Partition support with mtdparts
594 * Miscellaneous configurable options
596 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
599 * For booting Linux, the board info and command line data
600 * have to be in the first 64 MB of memory, since this is
601 * the maximum mapped by the Linux kernel during initialization.
603 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
604 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
606 #ifdef CONFIG_CMD_KGDB
607 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
608 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
612 * Environment Configuration
614 #define CONFIG_ROOTPATH "/opt/nfsroot"
615 #define CONFIG_BOOTFILE "uImage"
616 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
618 /* default location for tftp and bootm */
619 #define CONFIG_LOADADDR 1000000
620 #define __USB_PHY_TYPE utmi
622 #define CONFIG_EXTRA_ENV_SETTINGS \
623 "hwconfig=fsl_ddr:" \
624 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
626 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
628 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
629 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
630 "tftpflash=tftpboot $loadaddr $uboot && " \
631 "protect off $ubootaddr +$filesize && " \
632 "erase $ubootaddr +$filesize && " \
633 "cp.b $loadaddr $ubootaddr $filesize && " \
634 "protect on $ubootaddr +$filesize && " \
635 "cmp.b $loadaddr $ubootaddr $filesize\0" \
636 "consoledev=ttyS0\0" \
637 "ramdiskaddr=2000000\0" \
638 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
639 "fdtaddr=1e00000\0" \
640 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
644 * For emulation this causes u-boot to jump to the start of the
645 * proof point app code automatically
647 #define CONFIG_PROOF_POINTS \
648 "setenv bootargs root=/dev/$bdev rw " \
649 "console=$consoledev,$baudrate $othbootargs;" \
650 "cpu 1 release 0x29000000 - - -;" \
651 "cpu 2 release 0x29000000 - - -;" \
652 "cpu 3 release 0x29000000 - - -;" \
653 "cpu 4 release 0x29000000 - - -;" \
654 "cpu 5 release 0x29000000 - - -;" \
655 "cpu 6 release 0x29000000 - - -;" \
656 "cpu 7 release 0x29000000 - - -;" \
659 #define CONFIG_HVBOOT \
660 "setenv bootargs config-addr=0x60000000; " \
661 "bootm 0x01000000 - 0x00f00000"
664 "setenv bootargs root=/dev/$bdev rw " \
665 "console=$consoledev,$baudrate $othbootargs;" \
666 "cpu 1 release 0x01000000 - - -;" \
667 "cpu 2 release 0x01000000 - - -;" \
668 "cpu 3 release 0x01000000 - - -;" \
669 "cpu 4 release 0x01000000 - - -;" \
670 "cpu 5 release 0x01000000 - - -;" \
671 "cpu 6 release 0x01000000 - - -;" \
672 "cpu 7 release 0x01000000 - - -;" \
675 #define CONFIG_LINUX \
676 "setenv bootargs root=/dev/ram rw " \
677 "console=$consoledev,$baudrate $othbootargs;" \
678 "setenv ramdiskaddr 0x02000000;" \
679 "setenv fdtaddr 0x00c00000;" \
680 "setenv loadaddr 0x1000000;" \
681 "bootm $loadaddr $ramdiskaddr $fdtaddr"
683 #define CONFIG_HDBOOT \
684 "setenv bootargs root=/dev/$bdev rw " \
685 "console=$consoledev,$baudrate $othbootargs;" \
686 "tftp $loadaddr $bootfile;" \
687 "tftp $fdtaddr $fdtfile;" \
688 "bootm $loadaddr - $fdtaddr"
690 #define CONFIG_NFSBOOTCOMMAND \
691 "setenv bootargs root=/dev/nfs rw " \
692 "nfsroot=$serverip:$rootpath " \
693 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
694 "console=$consoledev,$baudrate $othbootargs;" \
695 "tftp $loadaddr $bootfile;" \
696 "tftp $fdtaddr $fdtfile;" \
697 "bootm $loadaddr - $fdtaddr"
699 #define CONFIG_RAMBOOTCOMMAND \
700 "setenv bootargs root=/dev/ram rw " \
701 "console=$consoledev,$baudrate $othbootargs;" \
702 "tftp $ramdiskaddr $ramdiskfile;" \
703 "tftp $loadaddr $bootfile;" \
704 "tftp $fdtaddr $fdtfile;" \
705 "bootm $loadaddr $ramdiskaddr $fdtaddr"
707 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
709 #include <asm/fsl_secure_boot.h>
711 #endif /* __T2080RDB_H */