include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * T2080 RDB/PCIe board configuration file
   9  */
  10
  11 #ifndef __T2080RDB_H
  12 #define __T2080RDB_H
  13
  14 #include <linux/stringify.h>
  15
  16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17 #define CONFIG_FSL_SATA_V2
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  21 #define CONFIG_ENABLE_36BIT_PHYS
  22
  23 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  24 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  25
  26 #ifdef CONFIG_RAMBOOT_PBL
  27 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  28
  29 #define CONFIG_SPL_FLUSH_IMAGE
  30 #define CONFIG_SPL_PAD_TO               0x40000
  31 #define CONFIG_SPL_MAX_SIZE             0x28000
  32 #define RESET_VECTOR_OFFSET             0x27FFC
  33 #define BOOT_PAGE_OFFSET                0x27000
  34 #ifdef CONFIG_SPL_BUILD
  35 #define CONFIG_SPL_SKIP_RELOCATE
  36 #define CONFIG_SPL_COMMON_INIT_DDR
  37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  38 #endif
  39
  40 #ifdef CONFIG_MTD_RAW_NAND
  41 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  42 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  43 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  44 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  46 #endif
  47
  48 #ifdef CONFIG_SPIFLASH
  49 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  50 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  55 #ifndef CONFIG_SPL_BUILD
  56 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  57 #endif
  58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  59 #endif
  60
  61 #ifdef CONFIG_SDCARD
  62 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  63 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  64 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  65 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  66 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  67 #ifndef CONFIG_SPL_BUILD
  68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  69 #endif
  70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  71 #endif
  72
  73 #endif /* CONFIG_RAMBOOT_PBL */
  74
  75 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  76 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  77 /* Set 1M boot space */
  78 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  79 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  80                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  81 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  82 #endif
  83
  84 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  85 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  86 #endif
  87
  88 /*
  89  * These can be toggled for performance analysis, otherwise use default.
  90  */
  91 #define CONFIG_SYS_CACHE_STASHING
  92 #define CONFIG_BTB              /* toggle branch predition */
  93 #define CONFIG_DDR_ECC
  94 #ifdef CONFIG_DDR_ECC
  95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  96 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  97 #endif
  98
  99 #ifndef __ASSEMBLY__
 100 unsigned long get_board_sys_clk(void);
 101 unsigned long get_board_ddr_clk(void);
 102 #endif
 103
 104 #define CONFIG_SYS_CLK_FREQ     66660000
 105 #define CONFIG_DDR_CLK_FREQ     133330000
 106
 107 /*
 108  * Config the L3 Cache as L3 SRAM
 109  */
 110 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 111 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 112 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 113 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
 114 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 115 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 116 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 117
 118 #define CONFIG_SYS_DCSRBAR      0xf0000000
 119 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 120
 121 /* EEPROM */
 122 #define CONFIG_SYS_I2C_EEPROM_NXID
 123 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 124 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 126
 127 /*
 128  * DDR Setup
 129  */
 130 #define CONFIG_VERY_BIG_RAM
 131 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 132 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 133 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 134 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 135 #define CONFIG_DDR_SPD
 136 #define CONFIG_SYS_SPD_BUS_NUM  0
 137 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 138 #define SPD_EEPROM_ADDRESS1     0x51
 139 #define SPD_EEPROM_ADDRESS2     0x52
 140 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 141 #define CTRL_INTLV_PREFERED     cacheline
 142
 143 /*
 144  * IFC Definitions
 145  */
 146 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 147 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 148 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 149 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 150                                 CSPR_PORT_SIZE_16 | \
 151                                 CSPR_MSEL_NOR | \
 152                                 CSPR_V)
 153 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 154
 155 /* NOR Flash Timing Params */
 156 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 157
 158 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 159                                 FTIM0_NOR_TEADC(0x5) | \
 160                                 FTIM0_NOR_TEAHC(0x5))
 161 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 162                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 163                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 164 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 165                                 FTIM2_NOR_TCH(0x4) | \
 166                                 FTIM2_NOR_TWPH(0x0E) | \
 167                                 FTIM2_NOR_TWP(0x1c))
 168 #define CONFIG_SYS_NOR_FTIM3    0x0
 169
 170 #define CONFIG_SYS_FLASH_QUIET_TEST
 171 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 172
 173 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 174 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 175 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 176 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 177 #define CONFIG_SYS_FLASH_EMPTY_INFO
 178 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 179
 180 /* CPLD on IFC */
 181 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 182 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 183 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 184 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 185                                 | CSPR_PORT_SIZE_8 \
 186                                 | CSPR_MSEL_GPCM \
 187                                 | CSPR_V)
 188 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 189 #define CONFIG_SYS_CSOR2        0x0
 190
 191 /* CPLD Timing parameters for IFC CS2 */
 192 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 193                                         FTIM0_GPCM_TEADC(0x0e) | \
 194                                         FTIM0_GPCM_TEAHC(0x0e))
 195 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 196                                         FTIM1_GPCM_TRAD(0x1f))
 197 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 198                                         FTIM2_GPCM_TCH(0x8) | \
 199                                         FTIM2_GPCM_TWP(0x1f))
 200 #define CONFIG_SYS_CS2_FTIM3            0x0
 201
 202 /* NAND Flash on IFC */
 203 #define CONFIG_NAND_FSL_IFC
 204 #define CONFIG_SYS_NAND_BASE            0xff800000
 205 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 206
 207 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 208 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 209                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 210                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 211                                 | CSPR_V)
 212 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 213
 214 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 215                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 216                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 217                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 218                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 219                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 220                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 221
 222 #define CONFIG_SYS_NAND_ONFI_DETECTION
 223
 224 /* ONFI NAND Flash mode0 Timing Params */
 225 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 226                                         FTIM0_NAND_TWP(0x18)    | \
 227                                         FTIM0_NAND_TWCHT(0x07)  | \
 228                                         FTIM0_NAND_TWH(0x0a))
 229 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 230                                         FTIM1_NAND_TWBE(0x39)   | \
 231                                         FTIM1_NAND_TRR(0x0e)    | \
 232                                         FTIM1_NAND_TRP(0x18))
 233 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 234                                         FTIM2_NAND_TREH(0x0a)   | \
 235                                         FTIM2_NAND_TWHRE(0x1e))
 236 #define CONFIG_SYS_NAND_FTIM3           0x0
 237
 238 #define CONFIG_SYS_NAND_DDR_LAW         11
 239 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 240 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 241 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 242
 243 #if defined(CONFIG_MTD_RAW_NAND)
 244 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 245 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 246 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 247 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 248 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 249 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 250 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 251 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 252 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 253 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 254 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 255 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 256 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 257 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 258 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 259 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 260 #else
 261 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 262 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 263 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 264 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 265 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 266 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 267 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 268 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 269 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 270 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 271 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 272 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 273 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 274 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 275 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 276 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 277 #endif
 278
 279 #if defined(CONFIG_RAMBOOT_PBL)
 280 #define CONFIG_SYS_RAMBOOT
 281 #endif
 282
 283 #ifdef CONFIG_SPL_BUILD
 284 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 285 #else
 286 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 287 #endif
 288
 289 #define CONFIG_HWCONFIG
 290
 291 /* define to use L1 as initial stack */
 292 #define CONFIG_L1_INIT_RAM
 293 #define CONFIG_SYS_INIT_RAM_LOCK
 294 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 297 /* The assembler doesn't like typecast */
 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 299                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 300                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 301 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 302 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 303                                                 GENERATED_GBL_DATA_SIZE)
 304 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 305 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 306 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 307
 308 /*
 309  * Serial Port
 310  */
 311 #define CONFIG_SYS_NS16550_SERIAL
 312 #define CONFIG_SYS_NS16550_REG_SIZE     1
 313 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 314 #define CONFIG_SYS_BAUDRATE_TABLE       \
 315         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 316 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 317 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 318 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 319 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 320
 321 /*
 322  * I2C
 323  */
 324 #if !CONFIG_IS_ENABLED(DM_I2C)
 325 #define CONFIG_SYS_I2C_LEGACY
 326 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 327 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 328 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 329 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 330 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 331 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 332 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 333 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 334 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 335 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 336 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 337 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 338 #else
 339 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 340 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 341 #endif
 342
 343 #define CONFIG_SYS_I2C_FSL
 344
 345 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 346 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 347 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 348 #define I2C_MUX_CH_DEFAULT      0x8
 349
 350 #define I2C_MUX_CH_VOL_MONITOR  0xa
 351
 352 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 353 #ifndef CONFIG_SPL_BUILD
 354 #define CONFIG_VID
 355 #endif
 356 #define CONFIG_VOL_MONITOR_IR36021_SET
 357 #define CONFIG_VOL_MONITOR_IR36021_READ
 358 /* The lowest and highest voltage allowed for T208xRDB */
 359 #define VDD_MV_MIN                      819
 360 #define VDD_MV_MAX                      1212
 361
 362 /*
 363  * RapidIO
 364  */
 365 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 366 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 367 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 368 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 369 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 370 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 371 /*
 372  * for slave u-boot IMAGE instored in master memory space,
 373  * PHYS must be aligned based on the SIZE
 374  */
 375 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 376 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 377 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 378 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 379 /*
 380  * for slave UCODE and ENV instored in master memory space,
 381  * PHYS must be aligned based on the SIZE
 382  */
 383 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 384 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 385 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 386
 387 /* slave core release by master*/
 388 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 389 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 390
 391 /*
 392  * SRIO_PCIE_BOOT - SLAVE
 393  */
 394 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 395 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 396 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 397                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 398 #endif
 399
 400 /*
 401  * eSPI - Enhanced SPI
 402  */
 403
 404 /*
 405  * General PCI
 406  * Memory space is mapped 1-1, but I/O space must start from 0.
 407  */
 408 #define CONFIG_PCIE1            /* PCIE controller 1 */
 409 #define CONFIG_PCIE2            /* PCIE controller 2 */
 410 #define CONFIG_PCIE3            /* PCIE controller 3 */
 411 #define CONFIG_PCIE4            /* PCIE controller 4 */
 412 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 413 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 414 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 415 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 416 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 417 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 418
 419 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 420 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 421 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 422 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 423 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 424
 425 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 426 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 427 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 428 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 429 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 430
 431 /* controller 4, Base address 203000 */
 432 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 433 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 434 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 435
 436 #ifdef CONFIG_PCI
 437 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 438 #endif
 439
 440 /* Qman/Bman */
 441 #ifndef CONFIG_NOBQFMAN
 442 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 443 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 444 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 445 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 446 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 447 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 448 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 449 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 450 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 451                                         CONFIG_SYS_BMAN_CENA_SIZE)
 452 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 453 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 454 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 455 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 456 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 457 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 458 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 459 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 460 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 461 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 462 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 463                                         CONFIG_SYS_QMAN_CENA_SIZE)
 464 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 465 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 466
 467 #define CONFIG_SYS_DPAA_FMAN
 468 #define CONFIG_SYS_DPAA_PME
 469 #define CONFIG_SYS_PMAN
 470 #define CONFIG_SYS_DPAA_DCE
 471 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 472 #define CONFIG_SYS_INTERLAKEN
 473
 474 /* Default address of microcode for the Linux Fman driver */
 475 #if defined(CONFIG_SPIFLASH)
 476 /*
 477  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 478  * env, so we got 0x110000.
 479  */
 480 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 481
 482 #elif defined(CONFIG_SDCARD)
 483 /*
 484  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 485  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 486  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 487  */
 488 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 489
 490 #elif defined(CONFIG_MTD_RAW_NAND)
 491 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 492 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 493 /*
 494  * Slave has no ucode locally, it can fetch this from remote. When implementing
 495  * in two corenet boards, slave's ucode could be stored in master's memory
 496  * space, the address can be mapped from slave TLB->slave LAW->
 497  * slave SRIO or PCIE outbound window->master inbound window->
 498  * master LAW->the ucode address in master's memory space.
 499  */
 500 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 501 #else
 502 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 503 #endif
 504 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 505 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 506 #endif /* CONFIG_NOBQFMAN */
 507
 508 #ifdef CONFIG_SYS_DPAA_FMAN
 509 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 510 #define RGMII_PHY2_ADDR         0x02
 511 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 512 #define CORTINA_PHY_ADDR2       0x0d
 513 /* Aquantia AQ1202 10G Base-T used by board revisions up to C */
 514 #define FM1_10GEC3_PHY_ADDR     0x00
 515 #define FM1_10GEC4_PHY_ADDR     0x01
 516 /* Aquantia AQR113C 10G Base-T used by board revisions D and up */
 517 #define AQR113C_PHY_ADDR1       0x00
 518 #define AQR113C_PHY_ADDR2       0x08
 519 #endif
 520
 521 #ifdef CONFIG_FMAN_ENET
 522 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 523 #endif
 524
 525 /*
 526  * SATA
 527  */
 528 #ifdef CONFIG_FSL_SATA_V2
 529 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 530 #define CONFIG_SATA1
 531 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 532 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 533 #define CONFIG_SATA2
 534 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 535 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 536 #define CONFIG_LBA48
 537 #endif
 538
 539 /*
 540  * USB
 541  */
 542 #ifdef CONFIG_USB_EHCI_HCD
 543 #define CONFIG_USB_EHCI_FSL
 544 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 545 #define CONFIG_HAS_FSL_DR_USB
 546 #endif
 547
 548 /*
 549  * SDHC
 550  */
 551 #ifdef CONFIG_MMC
 552 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 553 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 554 #endif
 555
 556 /*
 557  * Dynamic MTD Partition support with mtdparts
 558  */
 559
 560 /*
 561  * Environment
 562  */
 563
 564 /*
 565  * Miscellaneous configurable options
 566  */
 567 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 568
 569 /*
 570  * For booting Linux, the board info and command line data
 571  * have to be in the first 64 MB of memory, since this is
 572  * the maximum mapped by the Linux kernel during initialization.
 573  */
 574 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 575 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 576
 577 #ifdef CONFIG_CMD_KGDB
 578 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 579 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 580 #endif
 581
 582 /*
 583  * Environment Configuration
 584  */
 585 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 586 #define CONFIG_BOOTFILE  "uImage"
 587 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 588
 589 /* default location for tftp and bootm */
 590 #define CONFIG_LOADADDR         1000000
 591 #define __USB_PHY_TYPE          utmi
 592
 593 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 594         "hwconfig=fsl_ddr:"                                     \
 595         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 596         "bank_intlv=auto;"                                      \
 597         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 598         "netdev=eth0\0"                                         \
 599         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 600         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 601         "tftpflash=tftpboot $loadaddr $uboot && "               \
 602         "protect off $ubootaddr +$filesize && "                 \
 603         "erase $ubootaddr +$filesize && "                       \
 604         "cp.b $loadaddr $ubootaddr $filesize && "               \
 605         "protect on $ubootaddr +$filesize && "                  \
 606         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 607         "consoledev=ttyS0\0"                                    \
 608         "ramdiskaddr=2000000\0"                                 \
 609         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 610         "fdtaddr=1e00000\0"                                     \
 611         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 612         "bdev=sda3\0"
 613
 614 /*
 615  * For emulation this causes u-boot to jump to the start of the
 616  * proof point app code automatically
 617  */
 618 #define CONFIG_PROOF_POINTS                             \
 619         "setenv bootargs root=/dev/$bdev rw "           \
 620         "console=$consoledev,$baudrate $othbootargs;"   \
 621         "cpu 1 release 0x29000000 - - -;"               \
 622         "cpu 2 release 0x29000000 - - -;"               \
 623         "cpu 3 release 0x29000000 - - -;"               \
 624         "cpu 4 release 0x29000000 - - -;"               \
 625         "cpu 5 release 0x29000000 - - -;"               \
 626         "cpu 6 release 0x29000000 - - -;"               \
 627         "cpu 7 release 0x29000000 - - -;"               \
 628         "go 0x29000000"
 629
 630 #define CONFIG_HVBOOT                           \
 631         "setenv bootargs config-addr=0x60000000; "      \
 632         "bootm 0x01000000 - 0x00f00000"
 633
 634 #define CONFIG_ALU                              \
 635         "setenv bootargs root=/dev/$bdev rw "           \
 636         "console=$consoledev,$baudrate $othbootargs;"   \
 637         "cpu 1 release 0x01000000 - - -;"               \
 638         "cpu 2 release 0x01000000 - - -;"               \
 639         "cpu 3 release 0x01000000 - - -;"               \
 640         "cpu 4 release 0x01000000 - - -;"               \
 641         "cpu 5 release 0x01000000 - - -;"               \
 642         "cpu 6 release 0x01000000 - - -;"               \
 643         "cpu 7 release 0x01000000 - - -;"               \
 644         "go 0x01000000"
 645
 646 #define CONFIG_LINUX                            \
 647         "setenv bootargs root=/dev/ram rw "             \
 648         "console=$consoledev,$baudrate $othbootargs;"   \
 649         "setenv ramdiskaddr 0x02000000;"                \
 650         "setenv fdtaddr 0x00c00000;"                    \
 651         "setenv loadaddr 0x1000000;"                    \
 652         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 653
 654 #define CONFIG_HDBOOT                                   \
 655         "setenv bootargs root=/dev/$bdev rw "           \
 656         "console=$consoledev,$baudrate $othbootargs;"   \
 657         "tftp $loadaddr $bootfile;"                     \
 658         "tftp $fdtaddr $fdtfile;"                       \
 659         "bootm $loadaddr - $fdtaddr"
 660
 661 #define CONFIG_NFSBOOTCOMMAND                   \
 662         "setenv bootargs root=/dev/nfs rw "     \
 663         "nfsroot=$serverip:$rootpath "          \
 664         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 665         "console=$consoledev,$baudrate $othbootargs;"   \
 666         "tftp $loadaddr $bootfile;"             \
 667         "tftp $fdtaddr $fdtfile;"               \
 668         "bootm $loadaddr - $fdtaddr"
 669
 670 #define CONFIG_RAMBOOTCOMMAND                           \
 671         "setenv bootargs root=/dev/ram rw "             \
 672         "console=$consoledev,$baudrate $othbootargs;"   \
 673         "tftp $ramdiskaddr $ramdiskfile;"               \
 674         "tftp $loadaddr $bootfile;"                     \
 675         "tftp $fdtaddr $fdtfile;"                       \
 676         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 677
 678 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 679
 680 #include <asm/fsl_secure_boot.h>
 681
 682 #endif  /* __T2080RDB_H */